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/Zephyr-Core-3.5.0/tests/lib/cmsis_dsp/filtering/src/
Dmisc_q15.c53 DEFINE_CORRELATE_TEST(14, 17);
58 DEFINE_CORRELATE_TEST(15, 17);
63 DEFINE_CORRELATE_TEST(16, 17);
66 DEFINE_CORRELATE_TEST(17, 15);
67 DEFINE_CORRELATE_TEST(17, 16);
68 DEFINE_CORRELATE_TEST(17, 17);
69 DEFINE_CORRELATE_TEST(17, 18);
70 DEFINE_CORRELATE_TEST(17, 33);
73 DEFINE_CORRELATE_TEST(32, 17);
110 DEFINE_CONV_TEST(14, 17);
[all …]
/Zephyr-Core-3.5.0/boards/shields/waveshare_epaper/
Dwaveshare_epaper_gdew075t7.overlay26 softstart = [17 17 17 17];
Dwaveshare_epaper_gdew042t2.overlay25 softstart = [17 17 17];
Dwaveshare_epaper_gdew042t2-p.overlay30 softstart = [ 17 17 17 ];
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a77951.h46 #define PIN_A17 RCAR_GP_PIN(1, 17)
106 #define PIN_SD3_DS RCAR_GP_PIN(4, 17)
124 #define PIN_MSIOF0_SCK RCAR_GP_PIN(5, 17)
150 #define PIN_SSI_SCK78 RCAR_GP_PIN(6, 17)
185 #define PIN_DU_DOTCLKIN1 RCAR_NOGP_PIN(17)
867 #define FUNC_AUDIO_CLKA_A IPSR(17, 0, 0)
868 #define FUNC_AUDIO_CLKB_B IPSR(17, 4, 0)
869 #define FUNC_SCIF_CLK_A IPSR(17, 4, 1)
870 #define FUNC_STP_IVCXO27_1_D IPSR(17, 4, 6)
871 #define FUNC_REMOCON_A IPSR(17, 4, 7)
[all …]
/Zephyr-Core-3.5.0/dts/arm/microchip/
Dmec172xnsz.dtsi83 direct-capable-girqs = <13 14 15 16 17 18 19 20 21 23>;
97 16 17 18 21 22 24 25
108 16 17 18 19 20 21 22 23
119 16 17 18 19 20 21 22 23
130 16 17 18 19 20 21 22 23
141 16 17 18 19 20 21 22 23
169 16 17 18 19 20 22>;
186 16 17 20 21 22 23>;
237 sources = <0 1 2 3 4 5 6 7 8 9 10 16 17>;
246 12 13 14 15 16 17 18 19
[all …]
Dmec1501hsz.dtsi91 sources = <0 1 2 4 5 10 16 17>;
156 interrupts = <17 2>;
354 girqs = <23 17>;
443 girqs = <17 8>, <17 9>;
463 girqs = <17 0>;
489 girqs = <17 1>;
499 girqs = <17 2>;
509 girqs = <17 3>;
519 girqs = <17 4>;
528 girqs = <17 13>;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/pinctrl/
Dite,it8xxx2-pinctrl-func.yaml42 If KSO[17:0] is in KBS mode, setting 1 selects open-drain mode,
50 pull-up (KSO[17:16] setting internal pull-up by GPIO port GPCR register).
57 (include KSO[17:16]), otherwise setting pin configure to keyboard scan
Dsifive,pinctrl.yaml15 For example, setting pins 16 and 17 both to IOF0 would look like this:
24 pinmux = <17 SIFIVE_PINMUX_IOF0>;
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/reset/
Dgd32f3x0.h36 #define GD32_RESET_TIMER15 GD32_RESET_CONFIG(APB2RST, 17U)
46 #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U)
53 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHBRST, 17U)
/Zephyr-Core-3.5.0/samples/userspace/shared_mem/src/
Dmain.h54 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25}
56 17, 18, 19, 20, 21, 22, 23, 24, 25, 5, 0, 4, 1, 3, 2}
58 15, 14, 17, 16, 19, 18, 21, 20, 23, 22, 25, 24}
/Zephyr-Core-3.5.0/boards/arm/nrf9160dk_nrf9160/dts/
Dnrf9160dk_uart1_on_if0_3.dtsi11 <NRF_PSEL(UART_RX, 0, 17)>,
20 <NRF_PSEL(UART_RX, 0, 17)>,
/Zephyr-Core-3.5.0/tests/subsys/dsp/basicmath/src/
Dq15.c19 #define ABS_ERROR_THRESH_Q63 ((q63_t)(1 << 17))
51 17);
53 17);
87 ref_add_possat, 17);
89 ref_add_negsat, 17);
123 17);
125 17);
159 ref_sub_possat, 17);
161 ref_sub_negsat, 17);
195 17);
[all …]
/Zephyr-Core-3.5.0/soc/x86/apollo_lake/
Dsoc_gpio.h40 #define APL_GPIO_17 17
74 #define APL_GPIO_49 17
124 #define APL_GPIO_204 17
158 #define APL_GPIO_89 17
207 #define APL_GPIO_147 17
258 #define APL_GPIO_169 17
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/clock/
Dgd32f3x0-clocks.h35 #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHBEN, 17U)
49 #define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U)
63 #define GD32_CLOCK_TIMER15 GD32_CLOCK_CONFIG(APB2EN, 17U)
/Zephyr-Core-3.5.0/tests/drivers/flash/common/boards/
Dnrf52840dk_mx25r_high_perf.overlay6 cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
12 jedec-id = [c2 28 17];
/Zephyr-Core-3.5.0/subsys/net/lib/lwm2m/
Ducifi_lpwan.h11 #define MAC_ADDRESS_SIZE 17 /* 16 hex digits, eg. "01a2b3c4d5e6f708\0" */
31 #define UCIFI_LPWAN_NUMBER_REPEATS_RID 17
/Zephyr-Core-3.5.0/boards/arm/nrf9160dk_nrf52840/dts/
Dnrf9160dk_uart1_on_if0_3.dtsi18 psels = <NRF_PSEL(UART_TX, 0, 17)>,
27 psels = <NRF_PSEL(UART_TX, 0, 17)>,
/Zephyr-Core-3.5.0/boards/arm/ebyte_e73_tbb_nrf52832/
Debyte_e73_tbb_nrf52832-pinctrl.dtsi28 psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
35 psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
/Zephyr-Core-3.5.0/samples/boards/nrf/nrfx_prs/boards/
Dnrf9160dk_nrf9160.overlay5 <NRF_PSEL(SPIM_MOSI, 0, 17)>;
16 <NRF_PSEL(SPIM_MOSI, 0, 17)>,
84 * to the spi1 node (17, 18, and 19).
/Zephyr-Core-3.5.0/tests/drivers/rtc/shell/src/
Dmain.c133 err = shell_execute_cmd(sh, "rtc set " FAKE_RTC_NAME " 2022-05-17"); in ZTEST()
137 assert_set_time(2022, 5, 17, get_time_mock.rtc.tm_hour, get_time_mock.rtc.tm_min, in ZTEST()
164 err = shell_execute_cmd(sh, "rtc set " FAKE_RTC_NAME " 2022-05-17T23:45:16"); in ZTEST()
168 assert_set_time(2022, 5, 17, 23, 45, 16); in ZTEST()
179 err = shell_execute_cmd(sh, "rtc set " FAKE_RTC_NAME " 2022:05:17T23:45:16"); in ZTEST()
/Zephyr-Core-3.5.0/samples/drivers/jesd216/boards/
Dnrf52840dk_nrf52840_spi.overlay23 cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
31 jedec-id = [c2 28 17];
/Zephyr-Core-3.5.0/boards/arm/nrf52_adafruit_feather/
Dnrf52_adafruit_feather-pinctrl.dtsi39 psels = <NRF_PSEL(PWM_OUT0, 0, 17)>,
46 psels = <NRF_PSEL(PWM_OUT0, 0, 17)>,
/Zephyr-Core-3.5.0/boards/arm/actinius_icarus_som_dk/
Darduino_connector.dtsi15 <2 0 &gpio0 17 0>, /* A2 */
30 <17 0 &gpio0 13 0>, /* D11 */
42 <2 &adc 4>, /* A2 = P0.17 = AIN4 */
/Zephyr-Core-3.5.0/samples/kernel/condition_variables/simple/
DREADME.rst55 [thread 17] working (0/5)
75 [thread 17] working (1/5)
96 [thread 17] working (2/5)
116 [thread 17] working (3/5)
136 [thread 17] working (4/5)
187 [thread 16] done is now 17. Signalling cond.
189 [thread zephyr_app_main] done is 17 which is < 20 so waiting on cond
190 [thread 17] done is now 18. Signalling cond.

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