| /Zephyr-Core-3.5.0/soc/riscv/riscv-ite/common/ |
| D | vector.S | 53 * The content of 16-bytes must be the following and at offset 0x80 of binary.
55 * 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th 16th
71 .balign 16
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| /Zephyr-Core-3.5.0/arch/xtensa/core/ |
| D | crt1.S | 41 # define ARG4 a5 /* 4th outgoing call argument */
42 # define ARG5 a6 /* 5th outgoing call argument */
49 # define ARG4 a9 /* 4th outgoing call argument */
50 # define ARG5 a10 /* 5th outgoing call argument */
179 s32i a0, a8, 0 /* clear 8 bytes to make len multiple of 16 */
182 .L2zte: srli a10, a10, 4 /* len is now multiple of 16, divide by 16 */
184 s32i a0, a8, 0 /* clear 16 bytes at a time... */
188 addi a8, a8, 16
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| /Zephyr-Core-3.5.0/dts/bindings/serial/ |
| D | st,stm32-uart-base.yaml | 73 It is expressed in 16th of a bit time.
81 It is expressed in 16th of a bit time.
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/misc/ft8xx/ |
| D | ft8xx_dl.h | 33 * Anti-aliased lines, with width from 0 to 4095 1/16th of pixel units.
114 (((uint32_t)(red) & 0xff) << 16) | \
129 (((uint32_t)(red) & 0xff) << 16) | \
153 * the line to the outermost drawn pixel, in units of 1/16 pixel. The valid
154 * range is from 16 to 4095 in terms of 1/16th pixel units.
160 * @param width Line width in 1/16 pixel
188 * The range of coordinates is from -16384 to +16383 in terms of 1/16th pixel
194 * @param x Signed x-coordinate in 1/16 pixel precision
195 * @param y Signed y-coordinate in 1/16 pixel precision
204 * The valid range of @p handle is from 0 to 31. From 16 to 31 the bitmap handle
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| D | ft8xx_reference_api.h | 53 * @brief Write 2 bytes (16 bits) to FT8xx memory
87 * @brief Read 2 bytes (16 bits) from FT8xx memory
184 * @param font Font to use for text, 0-31. 16-31 are ROM fonts
211 * @param font Font to use for text, 0-31. 16-31 are ROM fonts
246 * Anti-aliased lines, with width from 0 to 4095 1/16th of pixel units.
357 * the line to the outermost drawn pixel, in units of 1/16 pixel. The valid
358 * range is from 16 to 4095 in terms of 1/16th pixel units.
363 * @param width Line width in 1/16 pixel
390 * The range of coordinates is from -16384 to +16383 in terms of 1/16th pixel
396 * @param x Signed x-coordinate in 1/16 pixel precision
[all …]
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| /Zephyr-Core-3.5.0/subsys/mgmt/osdp/src/ |
| D | osdp_sc.c | 16 static const uint8_t osdp_scbk_default[16] = {
40 for (i = 8; i < 16; i++) { in osdp_compute_scbk()
43 osdp_encrypt(master_key, NULL, scbk, 16); in osdp_compute_scbk()
50 uint8_t scbk[16]; in osdp_compute_session_keys()
53 memcpy(scbk, osdp_scbk_default, 16); in osdp_compute_session_keys()
58 memcpy(scbk, pd->sc.scbk, 16); in osdp_compute_session_keys()
62 memset(pd->sc.s_enc, 0, 16); in osdp_compute_session_keys()
63 memset(pd->sc.s_mac1, 0, 16); in osdp_compute_session_keys()
64 memset(pd->sc.s_mac2, 0, 16); in osdp_compute_session_keys()
79 osdp_encrypt(scbk, NULL, pd->sc.s_enc, 16); in osdp_compute_session_keys()
[all …]
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| /Zephyr-Core-3.5.0/drivers/interrupt_controller/ |
| D | intc_ioapic_priv.h | 36 #define IOAPIC_MRE_POS 16
50 #define IOAPIC_VTD_REMAP_FORMAT BIT(16)
52 * The 15th bits is in the first 32bits of RTE but since
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| /Zephyr-Core-3.5.0/subsys/net/ip/ |
| D | tcp.c | 150 struct tcphdr *th = NULL; in th_get() local
159 if (!net_pkt_is_contiguous(pkt, sizeof(*th))) { in th_get()
160 if (tcp_pkt_linearize(pkt, ip_len, sizeof(*th)) < 0) { in th_get()
167 th = net_pkt_cursor_get_pos(pkt); in th_get()
169 return th; in th_get()
187 struct tcphdr *th; in tcp_endpoint_set() local
189 th = th_get(pkt); in tcp_endpoint_set()
190 if (!th) { in tcp_endpoint_set()
196 ep->sin.sin_port = src == TCP_EP_SRC ? th_sport(th) : in tcp_endpoint_set()
197 th_dport(th); in tcp_endpoint_set()
[all …]
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| /Zephyr-Core-3.5.0/samples/boards/nrf/system_off/src/ |
| D | retained.c | 21 * * A 9th block of with 32 KiBy "large" sections
25 * sections in the 9th block, and possibly more blocks.
98 /* RAM[x] supports only 16 sections, each its own bit in ram_range_retain()
99 * for POWER (0..15) and RETENTION (16..31). We don't in ram_range_retain()
104 sections_per_block = 16; in ram_range_retain()
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| /Zephyr-Core-3.5.0/tests/subsys/logging/log_syst/src/ |
| D | mock_backend.c | 89 * 3rd bit = Sys-t Checksum, 4th bit = Sys-t Timestamp. Support for validating the in validate_msg()
94 size_t skip_bytes[5] = {0, 18, 4, 8, 16}; in validate_msg()
97 if (is_kth_bit_set(strtol(optional_flags, 0, 16), i)) { in validate_msg()
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| /Zephyr-Core-3.5.0/arch/arm64/core/ |
| D | fpu.c | 31 static void DBG(char *msg, struct k_thread *th) in DBG() argument
43 strcat(buf, th->name); in DBG()
46 v = *(unsigned char *)&th->arch.saved_fp_context; in DBG()
185 * where 0 <= <n> <= 7 and <pimm> is a 12-bits multiple of 16. in simulate_str_q_insn()
194 *(__int128 *)(sp + pimm * 16) = 0; in simulate_str_q_insn()
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| /Zephyr-Core-3.5.0/samples/subsys/nvs/src/ |
| D | main.c | 23 * At the 10th reboot the string item with id=4 is deleted (or marked for
26 * At the 11th reboot the string item with id=4 can no longer be read with the
30 * At the 78th reboot the first sector is full and a new sector is taken into
71 char buf[16]; in main()
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| /Zephyr-Core-3.5.0/include/zephyr/display/ |
| D | mb_display.h | 53 * First 16 bits are reserved for modes, last 16 for flags.
68 MB_DISPLAY_FLAG_LOOP = BIT(16),
81 * and bottom-right corner is the last value of the last (5th) row. As an
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| /Zephyr-Core-3.5.0/drivers/timer/ |
| D | cc13xx_cc26xx_rtc_timer.c | 123 next = (uint32_t)((uint64_t)newThreshold >> 16); in rtc_isr()
165 * For a very small period round up to interrupt upon 4th tick in in startDevice()
173 compare = period >> 16; in startDevice()
213 setThreshold(timeout >> 16); in sys_clock_set_timeout()
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| /Zephyr-Core-3.5.0/drivers/cache/ |
| D | cache_aspeed.c | 19 * bit[22]: 23th 32KB from 0x000a_8000 to 0x000a_ffff
20 * bit[23]: 24th 32KB from 0x000b_0000 to 0x000b_ffff
33 #define DCACHE_INVALID(addr) (BIT(31) | ((addr & GENMASK(10, 0)) << 16))
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| /Zephyr-Core-3.5.0/tests/kernel/sched/preempt/src/ |
| D | main.c | 105 k_tid_t th = &worker_threads[i]; in wakeup_src_thread() local
106 char buffer[16]; in wakeup_src_thread()
109 str = k_thread_state_str(th, buffer, sizeof(buffer)); in wakeup_src_thread()
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| /Zephyr-Core-3.5.0/drivers/sensor/iis2dlpc/ |
| D | iis2dlpc.c | 32 * @range: Full scale range (2, 4, 8 and 16 G)
142 static int ii2sdlpc_set_slope_th(const struct device *dev, uint16_t th) in ii2sdlpc_set_slope_th() argument
148 err = iis2dlpc_wkup_threshold_set(ctx, th & 0x3F); in ii2sdlpc_set_slope_th()
151 th & 0x03, err); in ii2sdlpc_set_slope_th()
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/ |
| D | dmic_regs.h | 149 #define OUTCONTROL_BFTH_MAX 4 /* Max depth 16 */
171 #define OUTCONTROL_IPM GENMASK(17, 16)
182 /* Source decimator for 4th stereo/mono data placeholder. */
212 #define CIC_CONTROL_SOFT_RESET BIT(16)
284 #define FIR_CONFIG_FIR_DECIMATION GENMASK(20, 16)
325 #define GLOBAL_CAP_FIR_A_RF_DEPTH GENMASK(23, 16)
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| /Zephyr-Core-3.5.0/subsys/bluetooth/controller/ll_sw/nordic/lll/ |
| D | lll_adv_iso.c | 317 pdu->payload[6] = payload_count >> 16; in prepare_cb_common()
479 /* transmit the (bn_curr)th Tx PDU of bis_curr */ in isr_tx_common()
485 /* transmit the (bn_curr)th Tx PDU of bis_curr */ in isr_tx_common()
493 /* transmit the (ptc_curr * bn)th Tx PDU */ in isr_tx_common()
501 /* transmit the (bn_curr)th PDU of bis_curr */ in isr_tx_common()
678 pdu->payload[6] = payload_count >> 16; in isr_tx_common()
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/include/ |
| D | dmic_regs.h | 152 #define OUTCONTROL_BFTH_MAX 4 /* Max depth 16 */
185 /* Source decimator for 4th stereo/mono data placeholder. */
215 #define CIC_CONTROL_SOFT_RESET BIT(16)
302 #define FIR_CONFIG_FIR_DECIMATION GENMASK(20, 16)
343 #define GLOBAL_CAP_FIR_A_RF_DEPTH GENMASK(23, 16)
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| /Zephyr-Core-3.5.0/doc/_doxygen/ |
| D | doxygen-awesome.css | 54 --spacing-large: 16px;
161 --page-font-size: 16px;
162 --navigation-font-size: 16px;
954 padding: 14px 16px;
1255 th.markdownTableHeadLeft, th.markdownTableHeadRight, th.markdownTableHeadCenter, th.markdownTableHe…
1262 table.markdownTable td, table.markdownTable th, table.fieldtable dt {
1267 table.fieldtable th {
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| /Zephyr-Core-3.5.0/kernel/ |
| D | sched.c | 255 static inline bool should_queue_thread(struct k_thread *th) in should_queue_thread() argument
257 return !IS_ENABLED(CONFIG_SMP) || th != _current; in should_queue_thread()
506 void k_thread_time_slice_set(struct k_thread *th, int32_t thread_slice_ticks, in k_thread_time_slice_set() argument
510 th->base.slice_ticks = thread_slice_ticks; in k_thread_time_slice_set()
511 th->base.slice_expired = expired; in k_thread_time_slice_set()
512 th->base.slice_data = data; in k_thread_time_slice_set()
1353 struct k_thread *th = (struct k_thread *)thread; in z_impl_k_thread_priority_set() local
1355 z_thread_priority_set(th, prio); in z_impl_k_thread_priority_set()
1634 BUILD_ASSERT(CONFIG_MP_MAX_NUM_CPUS <= 16, "Too many CPUs for mask word");
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| /Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/spigen/ |
| D | mec_spi_gen.py | 37 # 4th digit (if present) - dummy clocks between address and data phase
116 (hdr_spi_loc >> 16) & 0xff,
151 elif spi_config['spi_freq_mhz'] == 16:
193 hdr[0xA] = (pld_load_addr >> 16) & 0xff
199 hdr[0xE] = (pld_entry_addr >> 16) & 0xff
202 # payload size (16-bit) in granularity units
213 hdr[0x16] = (pld_offset >> 16) & 0xff
241 # Use a lambda to handle base 10 or base 16 (hex) input
271 choices = [12, 16, 24, 48],
273 help="SPI frequency: 12, 16, 24, or 48 MHz")
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| /Zephyr-Core-3.5.0/drivers/ieee802154/ |
| D | ieee802154_dw1000_regs.h | 54 /* PAN ID (31:16) and Short Address (15:0) */
105 #define DWT_SYS_CFG_PHR_MODE_SHFT 16
169 #define DWT_TX_FCTRL_TXPRF_SHFT 16
172 /* Transmit Pulse Repetition Frequency = 16 Mhz */
183 /* Bit mask to access Preamble Extension = 16 */
409 * These bits are the 16 high bits of status register TXPUTE and
470 * 00 = 16 symbols, 01 = 64 symbols, 10 = 1024 symbols, 11 = 4096 symbols
512 /* PRF being employed in the receiver = 16M */
516 #define DWT_RX_FINFO_RXPRF_SHIFT 16
537 #define DWT_RX_EQUAL_FP_AMPL2_SHIFT 16
[all …]
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| /Zephyr-Core-3.5.0/drivers/i2c/ |
| D | i2c_mchp_xec.c | 72 /* Recommended programming values based on 16MHz
74 * bus_clk_reg (16MHz/100KHz -2) = 0x4F + 0x4F
75 * (16MHz/400KHz -2) = 0x0F + 0x17
76 * (16MHz/1MHz -2) = 0x05 + 0x09
230 * PIN == 0: I2C Status LRB is valid and contains ACK/NACK data on 9th clock.
266 /* PIN == 0. LRB contains state of 9th bit */ in wait_completion()
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