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12 default 163
14 default 163
3 # Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
4 * Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
2 * Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
24 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=163
24 see Register 163 (0xA3): Global Control 20 for more details
4 <rect x="163" y="109" width="137" height="64" rx="5" fill="#3A8BF1"/>8 …38.732 243.732C238.263 244.201 238 244.837 238 245.5V268L243 263H260.5C261.163 263 261.799 262.737…13 …23.732 243.732C123.263 244.201 123 244.837 123 245.5V268L128 263H145.5C146.163 263 146.799 262.737…16 <path d="M358 163L343 154.34L343 171.66L358 163ZM300 164.5L344.5 164.5L344.5 161.5L300 161.5L300 16…
7 …34 173.732 12.7322C173.263 13.2011 173 13.837 173 14.5V37L178 32H195.5C196.163 32 196.799 31.7366 …10 <rect x="431.5" y="0.5" width="163" height="49" rx="4.5" fill="#EBEBEB"/>12 …51 23.88 544.231 24.72 544.231 26.24V31.5H541.691ZM549.363 19.62V17.18H552.163V19.62H549.363ZM549.…13 <rect x="431.5" y="0.5" width="163" height="49" rx="4.5" stroke="#DEDEDE"/>
18 …163 165 533.01 165.94 532.703 166.74C532.41 167.527 531.923 168.14 531.243 168.58C530.577 169.007 …20 …163 161.1 674.73 161.76 675.197 162.52C675.677 163.267 675.917 164.173 675.917 165.24C675.917 166.…26 …34 430.732 12.7322C430.263 13.2011 430 13.837 430 14.5V37L435 32H452.5C453.163 32 453.799 31.7366 …30 …34 612.732 12.7322C612.263 13.2011 612 13.837 612 14.5V37L617 32H634.5C635.163 32 635.799 31.7366 …
55 #define RSTMGR_ETRSTALLREQ_RSTLINE 163
324 A6 = 163358 A8 = 163426 A5 = 163
153 #define IT8XXX2_IRQ_ESPI_VW 163
296 #define ESP_PWM0_F0_IN 163297 #define ESP_PWM0_OUT1B 163
245 #define ESP_I2S0O_DATA_OUT20 163
93 * 2:1,5,7,9-11_5:36-48,100,163-167
85 #define SPI_RESERVED5_3 163
192 M7_SPI_RESERVED5_3 = 163,
193 M7_SPI_RESERVED5_3 = 163,