| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | particle-gen3-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 "shields" but use a different orientation and pin numbering scheme.
11 * A 12-pin header on the right. 9 pins on this header are exposed
13 * A 16-pin header. 13 pins on this header are exposed by this
17 0 through 8 correspond to the pins on the 12-pin header, starting
19 16-pin header, skipping the bottom pin then assigning 9 through 19,
20 skipping over GND, and replacing the lower 3V3 with pin 20. The
24 - 3V3
26 - GND
27 19 ADC0 LiPo+ -
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| D | microchip,mcp23xxx.yaml | 6 # SPDX-License-Identifier: Apache-2.0
9 include: [gpio-controller.yaml]
12 "#gpio-cells":
15 int-gpios:
16 type: phandle-array
18 GPIO connected to the controller INT pin. This pin is active-low.
20 reset-gpios:
21 type: phandle-array
23 GPIO connected to the controller RESET pin. This pin is active-low.
28 - 8
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| D | adafruit-feather-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 Proceeding counter-clockwise:
10 * A 16-pin header. 12 pins on this header are exposed
12 * A 12-pin header. 9 pins on this header are exposed
19 - RESET
20 - 3V3
21 - 3V3
22 - GND
23 0 A0 - VBAT
24 1 A1 - EN
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| D | ti,boosterpack-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
10 20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
11 10 x 2 pin headers. Both variants are compatible and stackable.
13 The pins of the 20 pin variant and the outer row of the 40 pin variant are
14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
21 5 GPIO 25 Analog 36 GPIO 16 RESET
32 compatible: "ti,boosterpack-header"
34 include: [gpio-nexus.yaml, base.yaml]
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| /Zephyr-Core-3.5.0/dts/bindings/sensor/ |
| D | nordic,nrf-qdec.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nordic,nrf-qdec"
8 include: [sensor-device.yaml, pinctrl-device.yaml]
17 pinctrl-0:
20 enable-pin:
23 The enable pin to use, to enable a connected QDEC device
25 For pins P0.0 through P0.31, use the pin number. For example,
26 to use P0.16 for the A pin, set:
28 enable-pin = <16>;
30 For pins P1.0 through P1.31, add 32 to the pin number. For
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| D | st,ism330dhcx-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: sensor-device.yaml
7 drdy-gpios:
8 type: phandle-array
10 DRDY gpio pin
12 This pin defaults to active high when produced by the sensor.
16 int-pin:
20 Select DRDY pin number (1 or 2).
29 configuration at power-up.
31 - 1
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| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | gpio_numicro.c | 4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/gpio/numicro-gpio.h>
19 #define MODE_PIN_SHIFT(pin) ((pin) * 2) argument
20 #define MODE_MASK(pin) (3 << MODE_PIN_SHIFT(pin)) argument
21 #define DINOFF_PIN_SHIFT(pin) ((pin) + 16) argument
22 #define DINOFF_MASK(pin) (1 << DINOFF_PIN_SHIFT(pin)) argument
23 #define PUSEL_PIN_SHIFT(pin) ((pin) * 2) argument
24 #define PUSEL_MASK(pin) (3 << PUSEL_PIN_SHIFT(pin)) argument
50 gpio_pin_t pin, gpio_flags_t flags) in gpio_numicro_configure() argument
52 const struct gpio_numicro_config *cfg = dev->config; in gpio_numicro_configure()
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| D | gpio_mcp23xxx.c | 5 * SPDX-License-Identifier: Apache-2.0
9 * @file Driver for MPC23xxx I2C/SPI-based GPIO driver.
42 const struct mcp23xxx_config *config = dev->config; in read_port_regs()
44 if (config->ngpios == 16U) { in read_port_regs()
48 return config->read_fn(dev, reg, buf); in read_port_regs()
65 const struct mcp23xxx_config *config = dev->config; in write_port_regs()
67 if (config->ngpios == 16U) { in write_port_regs()
71 return config->write_fn(dev, reg, value); in write_port_regs()
77 * IOCON is the only register that is not 16 bits wide on 16-pin devices; instead, it is mirrored in
78 * two adjacent memory locations. Because the underlying `write_fn` always does a 16-bit write for
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| D | gpio_xmc4xxx.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/infineon-xmc4xxx-gpio.h>
42 return -ENOTSUP; in gpio_xmc4xxx_convert_flags()
46 return -ENOTSUP; in gpio_xmc4xxx_convert_flags()
50 pin_config->mode = XMC_GPIO_MODE_INPUT_TRISTATE; in gpio_xmc4xxx_convert_flags()
52 pin_config->mode = XMC_GPIO_MODE_INPUT_PULL_DOWN; in gpio_xmc4xxx_convert_flags()
55 pin_config->mode = XMC_GPIO_MODE_INPUT_PULL_UP; in gpio_xmc4xxx_convert_flags()
61 return -EINVAL; in gpio_xmc4xxx_convert_flags()
65 pin_config->mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL; in gpio_xmc4xxx_convert_flags()
67 pin_config->mode = XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN; in gpio_xmc4xxx_convert_flags()
[all …]
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| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | sifive,pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 value of IOF_EN/IOF_SEL registers to control pin settings.
9 Device pin configuration should be placed in the child nodes of this node.
10 Populate the 'pinmux' field with a pair consisting of a pin number and its IO
12 - SIFIVE_PINMUX_IOF0
13 - SIFIVE_PINMUX_IOF1
15 For example, setting pins 16 and 17 both to IOF0 would look like this:
17 #include <dt-bindings/pinctrl/sifive-pinctrl.h>
21 pinmux = <16 SIFIVE_PINMUX_IOF0>;
36 child-binding:
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| D | st,stm32-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Pin controller Node
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32-pinctrl"
20 remap-pa11:
22 description: Remaps the PA11 pin to operate as PA9 pin.
25 remap-pa12:
27 description: Remaps the PA12 pin to operate as PA10 pin.
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| D | ite,it8xxx2-pinctrl-func.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: ITE IT8XXX2 pin controller function node
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
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| /Zephyr-Core-3.5.0/boards/shields/x_nucleo_eeprma2/ |
| D | x_nucleo_eeprma2.overlay | 4 * SPDX-License-Identifier: Apache-2.0
12 eeprom-0 = &eeprom0_x_nucleo_eeprma2;
13 eeprom-1 = &eeprom4_x_nucleo_eeprma2;
19 clock-frequency = <I2C_BITRATE_FAST>;
22 /* M24C02-FMC6TG aka U1 (2 kbit eeprom in DFN8 package) */
26 pagesize = <16>;
27 address-width = <8>;
30 /* if solder-bridge closed: arduino A1 pin on CN8 can wp */
31 /* wp-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; */
35 /* M24256-DFDW6TP aka U2 (256 kbit eeprom in TSSOP package) */
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| /Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/common/ |
| D | pinctrl_soc.h | 4 * SPDX-License-Identifier: Apache-2.0
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
89 #define MIO_PIN_SPECIAL_MASK_SDIO0_CD GENMASK(21, 16)
90 #define MIO_PIN_SPECIAL_SHIFT_SDIO0_CD 16
99 #define MIO_PIN_SPECIAL_MASK_SDIO1_CD GENMASK(21, 16)
100 #define MIO_PIN_SPECIAL_SHIFT_SDIO1_CD 16
107 /* MIO pin numbers */
124 #define MIO16 16
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
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| /Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/common/ |
| D | Kconfig.soc | 2 # SPDX-License-Identifier: Apache-2.0
16 bool "Support for external, SPI-connected RAM"
66 bool "ESP-PSRAM16 or APS1604"
69 bool "ESP-PSRAM32 or IS25WP032"
72 bool "ESP-PSRAM64 or LY68L6400"
124 menu "PSRAM clock and cs IO for ESP32-DOWD"
132 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
137 default 16
140 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
142 endmenu # PSRAM clock and cs IO for ESP32-DOWD
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| /Zephyr-Core-3.5.0/tests/drivers/gpio/gpio_basic_api/boards/ |
| D | gd32f450i_eval.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "test-gpio-basic-api";
10 /* unplug camera from JP27 and bridge D0-D1 (pins 16 and 15) */
11 out-gpios = <&gpioc 6 0>; /* DCI D0 (JP27 pin 16)*/
12 in-gpios = <&gpioc 7 0>; /* DCI D1 (JP27 pin 15) */
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| /Zephyr-Core-3.5.0/soc/riscv/riscv-ite/common/ |
| D | pinctrl_soc.h | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
15 * @brief ITE IT8XXX2 pin type.
21 * Pin configuration
22 * kSI[7:0] and KSO[15:0] pins only support pull-up, push-pull/open-drain.
23 * GPIO group pinctrl pins (include KSO[17:16]) support impedance,
24 * pull-up/down, voltage selection, input.
27 /* GPIO pin */
28 uint8_t pin; member
36 * @brief PIN configuration bitfield.
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| /Zephyr-Core-3.5.0/samples/drivers/adc/boards/ |
| D | lpcxpresso55s69_cpu0.overlay | 2 * SPDX-License-Identifier: Apache-2.0
4 * Copyright 2022-2023 NXP
7 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
11 io-channels = <&adc0 0 &adc0 1 &adc0 2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 * - Connect VREFN_TARGET to GND, and VREFP_TARGET to 3v3
24 * - Connect LPADC0 CH0A signal to voltage between 0~3.3V (P19 pin 4)
25 * - Connect LPADC0 CH0B signal to voltage between 0~3.3V (P19 pin 2)
27 * - Connect LPADC0 CH4A signal to voltage between 0~3.3V (P17 pin 19)
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/ |
| D | gecko-pinctrl-s1.h | 3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
31 /** Position of the pin field. */
33 /** Mask for the pin field. */
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| D | nrf-pinctrl.h | 3 * SPDX-License-Identifier: Apache-2.0
10 * The whole nRF pin configuration information is encoded in a 32-bit bitfield
13 * - 31..16: Pin function.
14 * - 15: Reserved.
15 * - 14: Pin inversion mode.
16 * - 13: Pin low power mode.
17 * - 12..9: Pin output drive configuration.
18 * - 8..7: Pin pull configuration.
19 * - 6..0: Pin number (combination of port and pin).
23 * @name nRF pin configuration bit field positions and masks.
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| /Zephyr-Core-3.5.0/dts/bindings/pwm/ |
| D | silabs,gecko-pwm.yaml | 3 compatible: "silabs,gecko-pwm"
5 include: [pwm-controller.yaml, base.yaml]
8 pin-location:
11 description: pwm pin configuration defined as <location port pin>
18 - 1
19 - 2
20 - 4
21 - 8
22 - 16
23 - 32
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| /Zephyr-Core-3.5.0/dts/bindings/serial/ |
| D | st,stm32-uart-base.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 description: STM32 UART-BASE
7 include: [uart-controller.yaml, pinctrl-device.yaml, reset-device.yaml]
22 single-wire:
25 Enable the single wire half-duplex communication.
27 only TX pin is used afterwards and should be configured.
30 tx-rx-swap:
35 tx-invert:
38 Invert the binary logic of tx pin. When enabled, physical logic levels are inverted and
41 rx-invert:
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| /Zephyr-Core-3.5.0/samples/boards/up_squared/gpio_counter/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
22 * as a 4-bit value (bin 0, 1, 2, 3 -> HAT Pin 35, 37, 38, 40).
23 * The counter increments for each change from 0 to 1 on HAT Pin 16.
27 * () Advanced -> HAT Configurations:
28 * - HD-Audio / I2S6 Selec -> Disabled
29 * - GPIO / PWM3 Selection -> GPIO
30 * - GPIO / I2S2 Selection -> GPIO
32 * - GPIO 19 (Pin16) Confi -> Input
34 * - GPIO 14 (Pin35) Confi -> Output
35 * - GPIO 15 (Pin37) Confi -> Output
[all …]
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| /Zephyr-Core-3.5.0/tests/drivers/adc/adc_api/boards/ |
| D | lpcxpresso55s69_cpu0.overlay | 2 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
11 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 * CH0A is routed to P19 pin 4
27 zephyr,vref-mv = <3300>;
28 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
30 zephyr,input-positive = <MCUX_LPADC_CH0A>;
34 * Channel 1 is used in single ended mode, with 16 bit resolution
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| /Zephyr-Core-3.5.0/drivers/serial/ |
| D | uart_stm32.h | 2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
4 * SPDX-License-Identifier: Apache-2.0
38 /* enable tx/rx pin swap */
40 /* enable rx pin inversion */
42 /* enable tx pin inversion */
46 /* de signal assertion time in 1/16 of a bit */
48 /* de signal deassertion time in 1/16 of a bit */
50 /* enable de pin inversion */
52 /* pin muxing */
59 /* Device defined as wake-up source */
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