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/Zephyr-Core-3.5.0/dts/bindings/display/
Dnxp,dcnano-lcdif.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,dcnano-lcdif"
8 include: [lcd-controller.yaml, pinctrl-device.yaml]
17 backlight-gpios:
18 type: phandle-array
23 data-bus-width:
25 default: "24-bit"
27 - "16-bit-config1" # 16 bit configuration 1. RGB565: XXXXXXXX_RRRRRGGG_GGGBBBBB
28 - "16-bit-config2" # 16 bit configuration 2. RGB565: XXXRRRRR_XXGGGGGG_XXXBBBBB
29 - "16-bit-config3" # 16-bit configuration 3. RGB565: XXRRRRRX_XXGGGGGG_XXBBBBBX
[all …]
Dnxp,imx-elcdif.yaml1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-elcdif"
8 include: [lcd-controller.yaml, pinctrl-device.yaml]
17 data-bus-width:
19 default: "16-bit"
21 - "16-bit"
22 - "8-bit"
23 - "18-bit"
24 - "24-bit"
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/Zephyr-Core-3.5.0/include/zephyr/sys/
Dbyteorder.h6 * Copyright (c) 2015-2016, Intel Corporation.
8 * SPDX-License-Identifier: Apache-2.0
21 #define __bswap_24(x) ((uint32_t) ((((x) >> 16) & 0xff) | \
23 (((x) & 0xff) << 16)))
44 * @brief Convert 16-bit integer from little-endian to host endianness.
46 * @param val 16-bit integer in little-endian format.
48 * @return 16-bit integer in host endianness.
52 * @brief Convert 16-bit integer from host endianness to little-endian.
54 * @param val 16-bit integer in host endianness.
56 * @return 16-bit integer in little-endian format.
[all …]
Dsys_io.h6 * SPDX-License-Identifier: Apache-2.0
48 * @brief Output a 16 bits to an I/O port
50 * This function writes a 16 bits to the given port.
52 * @param data the 16 bits to write
53 * @param port the port address where to write the 16 bits
58 * @brief Input 16 bits from an I/O port
60 * This function reads 16 bits from the port.
62 * @param port the port address from where to read the 16 bits
64 * @return the 16 bits read
89 * @fn static inline void sys_io_set_bit(io_port_t port, unsigned int bit)
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/Zephyr-Core-3.5.0/subsys/bluetooth/crypto/
Dbt_crypto.h2 * SPDX-License-Identifier: Apache-2.0
14 * @brief Cypher based Message Authentication Code (CMAC) with AES 128 bit
18 * @param[in] key 128-bit key
24 * @retval -EIO Computation failed.
33 * @param[in] u 256-bit
34 * @param[in] v 256-bit
35 * @param[in] x 128-bit key
36 * @param[in] z 8-bit
40 * @retval -EIO Computation failed.
42 int bt_crypto_f4(const uint8_t *u, const uint8_t *v, const uint8_t *x, uint8_t z, uint8_t res[16]);
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/Zephyr-Core-3.5.0/dts/bindings/sensor/
Dbosch,bmp388.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 200 - 200 - 5ms (default; chip reset value)
17 100 - 100 - 10ms
18 50 - 50 - 20ms
19 25 - 25 - 40ms
20 12.5 - 25/2 - 80ms
21 6.25 - 25/4 - 160ms
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Dti,ina219.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 lsb-microamp:
17 example: 100 -> ~3A
18 shunt-milliohm:
28 0 = 16 V FSR
31 The default of 32V is the power-on reset value of the device.
33 Should the expected bus voltage be below 16V set this to 0.
35 - 0
36 - 1
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/Zephyr-Core-3.5.0/dts/bindings/mipi-dsi/
Dnxp,imx-mipi-dsi.yaml4 # SPDX-License-Identifier: Apache-2.0
8 compatible: "nxp,imx-mipi-dsi"
10 include: mipi-dsi-host.yaml
22 dpi-color-coding:
25 - "16-bit-config-1"
26 - "16-bit-config-2"
27 - "16-bit-config-3"
28 - "18-bit-config-1"
29 - "18-bit-config-2"
30 - "24-bit"
[all …]
Dnxp,mipi-dsi-2l.yaml4 # SPDX-License-Identifier: Apache-2.0
8 compatible: "nxp,mipi-dsi-2l"
10 include: mipi-dsi-host.yaml
21 dpi-color-coding:
24 - "16-bit-config-1"
25 - "16-bit-config-2"
26 - "16-bit-config-3"
27 - "18-bit-config-1"
28 - "18-bit-config-2"
29 - "24-bit"
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/Zephyr-Core-3.5.0/drivers/can/
Dcan_mcp251xfd.h5 * SPDX-License-Identifier: Apache-2.0
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
82 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
87 #define MCP251XFD_REG_CON_ABAT BIT(27)
98 #define MCP251XFD_REG_CON_TXQEN BIT(20)
99 #define MCP251XFD_REG_CON_STEF BIT(19)
100 #define MCP251XFD_REG_CON_SERR2LOM BIT(18)
101 #define MCP251XFD_REG_CON_ESIGM BIT(17)
102 #define MCP251XFD_REG_CON_RTXAT BIT(16)
103 #define MCP251XFD_REG_CON_BRSDIS BIT(12)
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/Zephyr-Core-3.5.0/drivers/ethernet/
Deth_dwmac_priv.h6 * SPDX-License-Identifier: Apache-2.0
10 * DesignWare Cores Ethernet Quality-of-Service Databook
76 #define REG_READ(r) sys_read32(p->base_addr + (r))
77 #define REG_WRITE(r, v) sys_write32((v), p->base_addr + (r))
97 #define MAC_CONF_ARPEN BIT(31)
99 #define MAC_CONF_IPC BIT(27)
101 #define MAC_CONF_GPSLCE BIT(23)
102 #define MAC_CONF_S2KP BIT(22)
103 #define MAC_CONF_CST BIT(21)
104 #define MAC_CONF_ACS BIT(20)
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/Zephyr-Core-3.5.0/include/zephyr/bluetooth/
Dbyteorder.h8 * SPDX-License-Identifier: Apache-2.0
26 /** @brief Encode 16-bit value into array values in little-endian format.
28 * Helper macro to encode 16-bit values into comma separated values.
32 * @param _v 16-bit integer in host endianness.
34 * @return The comma separated values for the 16-bit value.
40 /** @brief Encode 24-bit value into array values in little-endian format.
42 * Helper macro to encode 24-bit values into comma separated values.
46 * @param _v 24-bit integer in host endianness.
48 * @return The comma separated values for the 24-bit value.
52 (((_v) >> 16) & 0xFFU) \
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Dcrypto.h6 * Copyright (c) 2017-2020 Nordic Semiconductor ASA
7 * Copyright (c) 2015-2017 Intel Corporation
9 * SPDX-License-Identifier: Apache-2.0
41 /** @brief AES encrypt little-endian data.
47 * @param key 128 bit LS byte first key for the encryption of the plaintext
48 * @param plaintext 128 bit LS byte first plaintext data block to be encrypted
49 * @param enc_data 128 bit LS byte first encrypted data block
53 int bt_encrypt_le(const uint8_t key[16], const uint8_t plaintext[16],
54 uint8_t enc_data[16]);
56 /** @brief AES encrypt big-endian data.
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/Zephyr-Core-3.5.0/drivers/dai/intel/ssp/
Dssp.h4 * SPDX-License-Identifier: Apache-2.0
12 #include "dai-params-intel-ipc3.h"
13 #include "dai-params-intel-ipc4.h"
16 (((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo))
19 (((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo))
24 #define DAI_INTEL_SSP_IS_BIT_SET(reg, bit) (((reg >> bit) & (0x1)) != 0) argument
28 #define DAI_INTEL_SSP_MAX_FREQ_INDEX (DAI_INTEL_SSP_NUM_FREQ - 1)
32 #define DAI_INTEL_SSP_FIFO_DEPTH 16
65 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
72 #define SSCR0_ECS BIT(6)
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/Zephyr-Core-3.5.0/drivers/spi/
Dspi_pw.h1 /* spi_pw.h - Penwell SPI driver definitions */
6 * SPDX-License-Identifier: Apache-2.0
41 #define PW_SPI_CTRLR0_SSE_BIT BIT(7)
42 #define PW_SPI_CTRLR0_EDSS_BIT BIT(20)
43 #define PW_SPI_CTRLR0_RIM_BIT BIT(22)
44 #define PW_SPI_CTRLR0_TIM_BIT BIT(23)
45 #define PW_SPI_CTRLR0_MOD_BIT BIT(31)
71 #define PW_SPI_CTRL1_RIE_BIT BIT(0)
72 #define PW_SPI_CTRL1_TIE_BIT BIT(1)
73 #define PW_SPI_CTRL1_LBM_BIT BIT(2)
[all …]
Dspi_andes_atcspi200.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SPI_BASE (((const struct spi_atcspi200_cfg *)(dev)->config)->base)
46 #define TFMAT_CPHA_MSK BIT(0)
47 #define TFMAT_CPOL_MSK BIT(1)
48 #define TFMAT_SLVMODE_MSK BIT(2)
49 #define TFMAT_LSB_MSK BIT(3)
50 #define TFMAT_DATA_MERGE_MSK BIT(7)
52 #define TFMAT_ADDR_LEN_MSK GENMASK(18, 16)
68 #define IEN_RX_FIFO_MSK BIT(2)
69 #define IEN_TX_FIFO_MSK BIT(3)
[all …]
/Zephyr-Core-3.5.0/include/zephyr/drivers/mfd/
Dnpm1300.h3 * SPDX-License-Identifier: Apache-2.0
41 * @param base Register base address (bits 15..8 of 16-bit address)
42 * @param offset Register offset address (bits 7..0 of 16-bit address)
46 * @retval -errno In case of any bus error (see i2c_write_read_dt())
55 * @param base Register base address (bits 15..8 of 16-bit address)
56 * @param offset Register offset address (bits 7..0 of 16-bit address)
59 * @retval -errno In case of any bus error (see i2c_write_read_dt())
67 * @param base Register base address (bits 15..8 of 16-bit address)
68 * @param offset Register offset address (bits 7..0 of 16-bit address)
71 * @retval -errno In case of any bus error (see i2c_write_dt())
[all …]
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/reg/
Dmec_timers.h4 * SPDX-License-Identifier: Apache-2.0
25 * 32-bit R/W
26 * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
32 * 32-bit R/W
33 * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
54 #define MCHP_BTMR_CTRL_PRESCALE_POS 16u
74 /** @brief Basic Timer(32 and 16 bit) registers. Total size = 20(0x14) bytes */
87 * Set count resolution in bit[0]
93 #define MCHP_HTMR_CTRL_RESOL_MASK BIT(MCHP_HTMR_CTRL_EN_POS)
95 #define MCHP_HTMR_CTRL_RESOL_125MS BIT(MCHP_HTMR_CTRL_EN_POS)
[all …]
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/reg/
Dmec172x_qspi.h4 * SPDX-License-Identifier: Apache-2.0
17 #define MCHP_QMSPI_MAX_DESCR 16u
130 #define MCHP_QMSPI_M_ACTIVATE BIT(0)
131 #define MCHP_QMSPI_M_SRST BIT(1)
132 #define MCHP_QMSPI_M_SAF_DMA_MODE_EN BIT(2)
133 #define MCHP_QMSPI_M_LDMA_RX_EN BIT(3)
134 #define MCHP_QMSPI_M_LDMA_TX_EN BIT(4)
137 #define MCHP_QMSPI_M_CPOL_CLK_IDLE_HI BIT(8)
143 #define MCHP_QMSPI_M_CPHA_MOSI_CE2 BIT(9)
149 #define MCHP_QMSPI_M_CPHA_MISO_CE2 BIT(10)
[all …]
Dmec172x_i2c_smb.h4 * SPDX-License-Identifier: Apache-2.0
36 * Size 8-bit
40 #define MCHP_I2C_SMB_CTRL_ACK BIT(0)
41 #define MCHP_I2C_SMB_CTRL_STO BIT(1)
42 #define MCHP_I2C_SMB_CTRL_STA BIT(2)
43 #define MCHP_I2C_SMB_CTRL_ENI BIT(3)
45 #define MCHP_I2C_SMB_CTRL_ESO BIT(6)
46 #define MCHP_I2C_SMB_CTRL_PIN BIT(7)
47 /* Status Read-only */
49 #define MCHP_I2C_SMB_STS_NBB BIT(0)
[all …]
Dmec172x_espi_vw.h4 * SPDX-License-Identifier: Apache-2.0
13 /* Master to Slave VW register: 96-bit (3 32 bit registers) */
14 /* 32-bit word 0 (bits[31:0]) */
28 /* 32-bit word 1 (bits[63:32]) */
35 #define ESPI_M2SW1_SRC2_SEL_POS 16
43 /* 32-bit word 2 (bits[95:64]) */
50 #define ESPI_M2SW2_SRC2_POS 16u
77 /* Slave to Master VW register: 64-bit (2 32 bit registers) */
78 /* 32-bit word 0 (bits[31:0]) */
95 #define ESPI_S2MW0_CHG0_POS 16u
[all …]
/Zephyr-Core-3.5.0/drivers/sensor/mcp9808/
Dmcp9808.h5 * SPDX-License-Identifier: Apache-2.0
26 /* 16 bits control configuration and state.
28 * * Bit 0 controls alert signal output mode
29 * * Bit 1 controls interrupt polarity
30 * * Bit 2 disables upper and lower threshold checking
31 * * Bit 3 enables alert signal output
32 * * Bit 4 records alert status
33 * * Bit 5 records interrupt status
34 * * Bit 6 locks the upper/lower window registers
35 * * Bit 7 locks the critical register
[all …]
/Zephyr-Core-3.5.0/drivers/flash/
Djesd216.c4 * SPDX-License-Identifier: Apache-2.0
19 res->instr = packed >> 8; in extract_instr()
20 res->mode_clocks = (packed >> 5) & 0x07; in extract_instr()
21 res->wait_states = packed & 0x1F; in extract_instr()
31 int rv = -ENOTSUP; in jesd216_bfp_read_support()
35 if ((php->len_dw >= 15) in jesd216_bfp_read_support()
36 && (sys_le32_to_cpu(bfp->dw10[5]) & BIT(9))) { in jesd216_bfp_read_support()
41 if ((php->len_dw >= 19) in jesd216_bfp_read_support()
42 && (sys_le32_to_cpu(bfp->dw10[9]) & BIT(9))) { in jesd216_bfp_read_support()
50 if (sys_le32_to_cpu(bfp->dw1) & BIT(16)) { in jesd216_bfp_read_support()
[all …]
/Zephyr-Core-3.5.0/boards/posix/nrf_bsim/common/cmsis/
Dcmsis_instr.h4 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
6 * SPDX-License-Identifier: Apache-2.0
11 * ARM Cortex-M CMSIS intrinsics.
17 /* Implement the following ARM intrinsics as no-op:
18 * - ARM Data Synchronization Barrier
19 * - ARM Data Memory Synchronization Barrier
20 * - ARM Instruction Synchronization Barrier
21 * - ARM No Operation
44 * Implement the following ARM intrinsics as non-exclusive accesses
46 * - STR Exclusive(8,16 & 32bit) (__STREX{B,H,W})
[all …]
/Zephyr-Core-3.5.0/drivers/pcie/endpoint/
Dpcie_ep_iproc.h4 * SPDX-License-Identifier: Apache-2.0
16 #define PCIE_LINKSPEED_SHIFT 16
34 #define MSIX_FUNC_MASK BIT(30)
45 #define MSIX_TABLE_SIZE 16 /* we support 16 MSI-X */
46 #define MSIX_TBL_ENTRY_SIZE 16
50 #define MSIX_VECTOR_MASK BIT(0)
59 #define PAXB_OARR_VALID BIT(0)
63 #define SNOOP_VALID_INTR BIT(3)
64 #define SNOOP_ADDR1_EN BIT(31)
74 #define AXI_FILTER_0_ENABLE (BIT(30) | BIT(2) | \
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