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/Zephyr-Core-3.5.0/tests/lib/cmsis_dsp/filtering/src/
Dmisc_q15.c3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
52 DEFINE_CORRELATE_TEST(14, 16);
53 DEFINE_CORRELATE_TEST(14, 17);
57 DEFINE_CORRELATE_TEST(15, 16);
58 DEFINE_CORRELATE_TEST(15, 17);
61 DEFINE_CORRELATE_TEST(16, 15);
62 DEFINE_CORRELATE_TEST(16, 16);
63 DEFINE_CORRELATE_TEST(16, 17);
64 DEFINE_CORRELATE_TEST(16, 18);
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/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a77951.h4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
45 #define PIN_A16 RCAR_GP_PIN(1, 16)
46 #define PIN_A17 RCAR_GP_PIN(1, 17)
105 #define PIN_SD3_DATA7 RCAR_GP_PIN(4, 16)
106 #define PIN_SD3_DS RCAR_GP_PIN(4, 17)
123 #define PIN_HRTS0 RCAR_GP_PIN(5, 16)
124 #define PIN_MSIOF0_SCK RCAR_GP_PIN(5, 17)
149 #define PIN_SSI_SDATA6 RCAR_GP_PIN(6, 16)
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/Zephyr-Core-3.5.0/tests/subsys/dsp/basicmath/src/
Dq15.c3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
19 #define ABS_ERROR_THRESH_Q63 ((q63_t)(1 << 17))
48 DEFINE_TEST_VARIANT4(basic_math_q15, zdsp_add_q15, 16, in_com1, in_com2, ref_add, 16);
51 17);
53 17);
84 DEFINE_TEST_VARIANT4(basic_math_q15, zdsp_add_q15_in_place, 16, in_com1, in_com2, ref_add, 16);
87 ref_add_possat, 17);
89 ref_add_negsat, 17);
120 DEFINE_TEST_VARIANT4(basic_math_q15, zdsp_sub_q15, 16, in_com1, in_com2, ref_sub, 16);
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/Zephyr-Core-3.5.0/samples/userspace/shared_mem/src/
Dmain.h4 * SPDX-License-Identifier: Apache-2.0
54 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25}
55 #define START_WHEEL2 {6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, \
56 17, 18, 19, 20, 21, 22, 23, 24, 25, 5, 0, 4, 1, 3, 2}
58 15, 14, 17, 16, 19, 18, 21, 20, 23, 22, 25, 24}
/Zephyr-Core-3.5.0/subsys/net/lib/lwm2m/
Ducifi_lpwan.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Mandatory resource: ID 6 - IEEE MAC address of the device (up to 64 bits) */
11 #define MAC_ADDRESS_SIZE 17 /* 16 hex digits, eg. "01a2b3c4d5e6f708\0" */
14 /* clang-format off */
30 #define UCIFI_LPWAN_MAX_REPEAT_TIME_RID 16
31 #define UCIFI_LPWAN_NUMBER_REPEATS_RID 17
39 /* clang-format on */
/Zephyr-Core-3.5.0/soc/x86/apollo_lake/
Dsoc_gpio.h2 * Copyright (c) 2018-2019, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
39 #define APL_GPIO_16 16
40 #define APL_GPIO_17 17
73 #define APL_GPIO_48 16
74 #define APL_GPIO_49 17
123 #define APL_GPIO_203 16
124 #define APL_GPIO_204 17
157 #define APL_GPIO_88 16
158 #define APL_GPIO_89 17
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/Zephyr-Core-3.5.0/dts/bindings/pinctrl/
Dite,it8xxx2-pinctrl-func.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
32 volt-sel:
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Dsifive,pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
12 - SIFIVE_PINMUX_IOF0
13 - SIFIVE_PINMUX_IOF1
15 For example, setting pins 16 and 17 both to IOF0 would look like this:
17 #include <dt-bindings/pinctrl/sifive-pinctrl.h>
21 pinmux = <16 SIFIVE_PINMUX_IOF0>;
24 pinmux = <17 SIFIVE_PINMUX_IOF0>;
36 child-binding:
/Zephyr-Core-3.5.0/drivers/ethernet/
Deth_dwmac_priv.h6 * SPDX-License-Identifier: Apache-2.0
10 * DesignWare Cores Ethernet Quality-of-Service Databook
76 #define REG_READ(r) sys_read32(p->base_addr + (r))
77 #define REG_WRITE(r, v) sys_write32((v), p->base_addr + (r))
107 #define MAC_CONF_JD BIT(17)
108 #define MAC_CONF_JE BIT(16)
133 #define MAC_EXT_CONF_SPEN BIT(17)
134 #define MAC_EXT_CONF_DCRCC BIT(16)
144 #define MAC_PKT_FILTER_VTFE BIT(16)
185 #define MAC_VLAN_TAG_CTRL_VTIM BIT(17)
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/Zephyr-Core-3.5.0/drivers/can/
Dcan_mcp251xfd.h5 * SPDX-License-Identifier: Apache-2.0
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
82 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
101 #define MCP251XFD_REG_CON_ESIGM BIT(17)
102 #define MCP251XFD_REG_CON_RTXAT BIT(16)
120 #define MCP251XFD_REG_NBTCFG_TSEG1_MASK GENMASK(23, 16)
126 #define MCP251XFD_REG_DBTCFG_TSEG1_MASK GENMASK(20, 16)
133 #define MCP251XFD_REG_TDC_TDCMOD_MASK GENMASK(17, 16)
139 #define MCP251XFD_REG_TDC_TDCO_MIN -64
146 #define MCP251XFD_REG_TSCON_TSEOF BIT(17)
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/Zephyr-Core-3.5.0/tests/drivers/rtc/shell/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
61 get_time_mock.rtc.tm_year = 2023 - 1900; /* rtc_time year offset */ in configure_get_time_mock()
62 get_time_mock.rtc.tm_mon = 12 - 1; /* rtc_time month offset */ in configure_get_time_mock()
79 zassert_equal(year, rtctime->tm_year + 1900, "Year mismatch"); in assert_set_time()
80 zassert_equal(mon, rtctime->tm_mon + 1, "Month mismatch"); in assert_set_time()
81 zassert_equal(mday, rtctime->tm_mday, "Day mismatch"); in assert_set_time()
82 zassert_equal(hour, rtctime->tm_hour, "Hour mismatch"); in assert_set_time()
83 zassert_equal(min, rtctime->tm_min, "Minute mismatch"); in assert_set_time()
84 zassert_equal(sec, rtctime->tm_sec, "Second mismatch"); in assert_set_time()
104 configure_get_time_mock(-ENODATA); in ZTEST()
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/Zephyr-Core-3.5.0/dts/bindings/sensor/
Dbosch,bmp388.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 200 - 200 - 5ms (default; chip reset value)
17 100 - 100 - 10ms
18 50 - 50 - 20ms
19 25 - 25 - 40ms
20 12.5 - 25/2 - 80ms
21 6.25 - 25/4 - 160ms
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/Zephyr-Core-3.5.0/dts/arm/microchip/
Dmec172xnsz.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
18 #include "mec172x/mec172x-vw-routing.dtsi"
22 #address-cells = <1>;
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/Zephyr-Core-3.5.0/boards/arm/actinius_icarus_som_dk/
Darduino_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpio0 15 0>, /* A0 */
14 <1 0 &gpio0 16 0>, /* A1 */
15 <2 0 &gpio0 17 0>, /* A2 */
29 <16 0 &gpio0 7 0>, /* D10 */
30 <17 0 &gpio0 13 0>, /* D11 */
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/Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
89 #define MIO_PIN_SPECIAL_MASK_SDIO0_CD GENMASK(21, 16)
90 #define MIO_PIN_SPECIAL_SHIFT_SDIO0_CD 16
99 #define MIO_PIN_SPECIAL_MASK_SDIO1_CD GENMASK(21, 16)
100 #define MIO_PIN_SPECIAL_SHIFT_SDIO1_CD 16
124 #define MIO16 16
125 #define MIO17 17
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
172 #define MIO_GROUP_SPI0_0_GRP_PINS 16, 17, 21
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/Zephyr-Core-3.5.0/samples/kernel/condition_variables/simple/
DREADME.rst24 .. zephyr-app-commands::
25 :zephyr-app: samples/kernel/condition_variables/simple
26 :host-os: unix
36 .. code-block:: console
54 [thread 16] working (0/5)
55 [thread 17] working (0/5)
74 [thread 16] working (1/5)
75 [thread 17] working (1/5)
95 [thread 16] working (2/5)
96 [thread 17] working (2/5)
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/Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/common/
DKconfig.soc2 # SPDX-License-Identifier: Apache-2.0
16 bool "Support for external, SPI-connected RAM"
66 bool "ESP-PSRAM16 or APS1604"
69 bool "ESP-PSRAM32 or IS25WP032"
72 bool "ESP-PSRAM64 or LY68L6400"
124 menu "PSRAM clock and cs IO for ESP32-DOWD"
129 default 17
132 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
137 default 16
140 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/
Dti-cc32xx-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole TI CC32XX pin configuration information is encoded in a 32-bit
13 * - 31..22: Reserved
14 * - 21..16: Pin.
15 * - 15..10: Reserved.
16 * - 9: Pull-down flag.
17 * - 8: Pull-up flag.
18 * - 7..5: Drive strength.
19 * - 4: Enable open-drain flag.
20 * - 3..0: Configuration mode
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/Zephyr-Core-3.5.0/dts/xtensa/espressif/esp32/
Desp32_wrover_e_n16r2.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 gpio-reserved-ranges = <6 11>,<16 17>, // flash&psram
16 gpio-reserved-ranges = <6>,<7>; // GPIO37-38 NC
19 /* 16MB flash */
21 reg = <0x0 DT_SIZE_M(16)>;
Desp32_wrover_e_n16r4.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 gpio-reserved-ranges = <6 11>,<16 17>, // flash&psram
16 gpio-reserved-ranges = <6>,<7>; // GPIO37-38 NC
19 /* 16MB flash */
21 reg = <0x0 DT_SIZE_M(16)>;
Desp32_wrover_e_n16r8.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 gpio-reserved-ranges = <6 11>,<16 17>, // flash&psram
16 gpio-reserved-ranges = <6>,<7>; // GPIO37-38 NC
19 /* 16MB flash */
21 reg = <0x0 DT_SIZE_M(16)>;
/Zephyr-Core-3.5.0/samples/boards/nrf/nrfx_prs/boards/
Dnrf9160dk_nrf9160.overlay4 psels = <NRF_PSEL(SPIM_SCK, 0, 16)>,
5 <NRF_PSEL(SPIM_MOSI, 0, 17)>;
9 bias-pull-down;
15 psels = <NRF_PSEL(SPIM_SCK, 0, 16)>,
16 <NRF_PSEL(SPIM_MOSI, 0, 17)>,
18 low-power-enable;
29 bias-pull-down;
45 compatible = "nordic,nrf-spim";
47 cs-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
48 pinctrl-0 = <&spi1_default_alt>;
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/Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/
Dsoc_pins.h4 * SPDX-License-Identifier: Apache-2.0
31 #define MCHP_GPIO_020 (16U)
32 #define MCHP_GPIO_021 (17U)
65 #define MCHP_GPIO_060 (16U)
66 #define MCHP_GPIO_061 (17U)
99 #define MCHP_GPIO_120 (16U)
100 #define MCHP_GPIO_121 (17U)
133 #define MCHP_GPIO_160 (16U)
134 #define MCHP_GPIO_161 (17U)
167 #define MCHP_GPIO_220 (16U)
[all …]
/Zephyr-Core-3.5.0/boards/arm/contextualelectronics_abc/
Dcontextualelectronics_abc-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
18 low-power-enable;
26 <NRF_PSEL(UART_RTS, 0, 17)>,
27 <NRF_PSEL(UART_CTS, 0, 16)>;
35 <NRF_PSEL(UART_RTS, 0, 17)>,
36 <NRF_PSEL(UART_CTS, 0, 16)>;
37 low-power-enable;
52 low-power-enable;
69 low-power-enable;
/Zephyr-Core-3.5.0/scripts/coredump/gdbstubs/arch/
Dx86_64.py5 # SPDX-License-Identifier: Apache-2.0
35 RIP = 16
36 EFLAGS = 17
66 IV_X87_FPU_FP_ERROR = 16
67 IV_ALIGNMENT_CHECK = 17
77 # Mapping is from GDB's gdb/i386-stubs.c
82 ExceptionVectors.IV_OVERFLOW: 16,
83 ExceptionVectors.IV_BOUND_RANGE: 16,
150 self.registers[RegNum.RBP] = tu[16]
153 self.registers[RegNum.RBX] = tu[17]
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