Home
last modified time | relevance | path

Searched +full:16 +full:- +full:17 (Results 1 – 25 of 680) sorted by relevance

12345678910>>...28

/Zephyr-Core-3.4.0/tests/lib/cmsis_dsp/filtering/src/
Dmisc_q15.c3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
52 DEFINE_CORRELATE_TEST(14, 16);
53 DEFINE_CORRELATE_TEST(14, 17);
57 DEFINE_CORRELATE_TEST(15, 16);
58 DEFINE_CORRELATE_TEST(15, 17);
61 DEFINE_CORRELATE_TEST(16, 15);
62 DEFINE_CORRELATE_TEST(16, 16);
63 DEFINE_CORRELATE_TEST(16, 17);
64 DEFINE_CORRELATE_TEST(16, 18);
[all …]
/Zephyr-Core-3.4.0/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a77951.h4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
45 #define PIN_A16 RCAR_GP_PIN(1, 16)
46 #define PIN_A17 RCAR_GP_PIN(1, 17)
105 #define PIN_SD3_DATA7 RCAR_GP_PIN(4, 16)
106 #define PIN_SD3_DS RCAR_GP_PIN(4, 17)
123 #define PIN_HRTS0 RCAR_GP_PIN(5, 16)
124 #define PIN_MSIOF0_SCK RCAR_GP_PIN(5, 17)
149 #define PIN_SSI_SDATA6 RCAR_GP_PIN(6, 16)
[all …]
/Zephyr-Core-3.4.0/tests/subsys/dsp/basicmath/src/
Dq15.c3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
19 #define ABS_ERROR_THRESH_Q63 ((q63_t)(1 << 17))
48 DEFINE_TEST_VARIANT4(basic_math_q15, zdsp_add_q15, 16, in_com1, in_com2, ref_add, 16);
51 17);
53 17);
84 DEFINE_TEST_VARIANT4(basic_math_q15, zdsp_add_q15_in_place, 16, in_com1, in_com2, ref_add, 16);
87 ref_add_possat, 17);
89 ref_add_negsat, 17);
120 DEFINE_TEST_VARIANT4(basic_math_q15, zdsp_sub_q15, 16, in_com1, in_com2, ref_sub, 16);
[all …]
/Zephyr-Core-3.4.0/samples/userspace/shared_mem/src/
Dmain.h4 * SPDX-License-Identifier: Apache-2.0
54 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25}
55 #define START_WHEEL2 {6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, \
56 17, 18, 19, 20, 21, 22, 23, 24, 25, 5, 0, 4, 1, 3, 2}
58 15, 14, 17, 16, 19, 18, 21, 20, 23, 22, 25, 24}
/Zephyr-Core-3.4.0/dts/bindings/pinctrl/
Dite,it8xxx2-pinctrl-func.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func4-gcr:
20 func4-en-mask:
23 volt-sel:
26 volt-sel-mask:
29 pp-od-mask:
32 KSI[7:0] does not support push-pull and open-drain mode.
[all …]
Dsifive,pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
12 - SIFIVE_PINMUX_IOF0
13 - SIFIVE_PINMUX_IOF1
15 For example, setting pins 16 and 17 both to IOF0 would look like this:
17 #include <dt-bindings/pinctrl/sifive-pinctrl.h>
21 pinmux = <16 SIFIVE_PINMUX_IOF0>;
24 pinmux = <17 SIFIVE_PINMUX_IOF0>;
36 child-binding:
/Zephyr-Core-3.4.0/soc/x86/apollo_lake/
Dsoc_gpio.h2 * Copyright (c) 2018-2019, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
39 #define APL_GPIO_16 16
40 #define APL_GPIO_17 17
73 #define APL_GPIO_48 16
74 #define APL_GPIO_49 17
123 #define APL_GPIO_203 16
124 #define APL_GPIO_204 17
157 #define APL_GPIO_88 16
158 #define APL_GPIO_89 17
[all …]
/Zephyr-Core-3.4.0/subsys/net/lib/lwm2m/
Ducifi_lpwan.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Mandatory resource: ID 6 - IEEE MAC address of the device (up to 64 bits) */
11 #define MAC_ADDRESS_SIZE 17 /* 16 hex digits, eg. "01a2b3c4d5e6f708\0" */
14 /* clang-format off */
30 #define UCIFI_LPWAN_MAX_REPEAT_TIME_RID 16
31 #define UCIFI_LPWAN_NUMBER_REPEATS_RID 17
39 /* clang-format on */
/Zephyr-Core-3.4.0/drivers/ethernet/
Deth_dwmac_priv.h6 * SPDX-License-Identifier: Apache-2.0
10 * DesignWare Cores Ethernet Quality-of-Service Databook
76 #define REG_READ(r) sys_read32(p->base_addr + (r))
77 #define REG_WRITE(r, v) sys_write32((v), p->base_addr + (r))
107 #define MAC_CONF_JD BIT(17)
108 #define MAC_CONF_JE BIT(16)
133 #define MAC_EXT_CONF_SPEN BIT(17)
134 #define MAC_EXT_CONF_DCRCC BIT(16)
144 #define MAC_PKT_FILTER_VTFE BIT(16)
185 #define MAC_VLAN_TAG_CTRL_VTIM BIT(17)
[all …]
/Zephyr-Core-3.4.0/dts/bindings/sensor/
Dbosch,bmp388.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 200 - 200 - 5ms (default; chip reset value)
17 100 - 100 - 10ms
18 50 - 50 - 20ms
19 25 - 25 - 40ms
20 12.5 - 25/2 - 80ms
21 6.25 - 25/4 - 160ms
[all …]
/Zephyr-Core-3.4.0/dts/arm/microchip/
Dmec172xnsz.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
18 #include "mec172x/mec172x-vw-routing.dtsi"
22 #address-cells = <1>;
[all …]
/Zephyr-Core-3.4.0/boards/arm/actinius_icarus_som_dk/
Darduino_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpio0 15 0>, /* A0 */
14 <1 0 &gpio0 16 0>, /* A1 */
15 <2 0 &gpio0 17 0>, /* A2 */
29 <16 0 &gpio0 7 0>, /* D10 */
30 <17 0 &gpio0 13 0>, /* D11 */
[all …]
/Zephyr-Core-3.4.0/soc/arm/xilinx_zynq7000/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
89 #define MIO_PIN_SPECIAL_MASK_SDIO0_CD GENMASK(21, 16)
90 #define MIO_PIN_SPECIAL_SHIFT_SDIO0_CD 16
99 #define MIO_PIN_SPECIAL_MASK_SDIO1_CD GENMASK(21, 16)
100 #define MIO_PIN_SPECIAL_SHIFT_SDIO1_CD 16
124 #define MIO16 16
125 #define MIO17 17
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
172 #define MIO_GROUP_SPI0_0_GRP_PINS 16, 17, 21
[all …]
/Zephyr-Core-3.4.0/samples/kernel/condition_variables/simple/
DREADME.rst24 .. zephyr-app-commands::
25 :zephyr-app: samples/kernel/condition_variables/simple
26 :host-os: unix
36 .. code-block:: console
54 [thread 16] working (0/5)
55 [thread 17] working (0/5)
74 [thread 16] working (1/5)
75 [thread 17] working (1/5)
95 [thread 16] working (2/5)
96 [thread 17] working (2/5)
[all …]
/Zephyr-Core-3.4.0/samples/boards/nrf/nrfx_prs/boards/
Dnrf9160dk_nrf9160.overlay4 psels = <NRF_PSEL(SPIM_SCK, 0, 16)>,
5 <NRF_PSEL(SPIM_MOSI, 0, 17)>;
9 bias-pull-down;
15 psels = <NRF_PSEL(SPIM_SCK, 0, 16)>,
16 <NRF_PSEL(SPIM_MOSI, 0, 17)>,
18 low-power-enable;
29 bias-pull-down;
45 compatible = "nordic,nrf-spim";
47 cs-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
48 pinctrl-0 = <&spi1_default_alt>;
[all …]
/Zephyr-Core-3.4.0/soc/arm/microchip_mec/common/
Dsoc_pins.h4 * SPDX-License-Identifier: Apache-2.0
31 #define MCHP_GPIO_020 (16U)
32 #define MCHP_GPIO_021 (17U)
65 #define MCHP_GPIO_060 (16U)
66 #define MCHP_GPIO_061 (17U)
99 #define MCHP_GPIO_120 (16U)
100 #define MCHP_GPIO_121 (17U)
133 #define MCHP_GPIO_160 (16U)
134 #define MCHP_GPIO_161 (17U)
167 #define MCHP_GPIO_220 (16U)
[all …]
/Zephyr-Core-3.4.0/boards/arm/contextualelectronics_abc/
Dcontextualelectronics_abc-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
18 low-power-enable;
26 <NRF_PSEL(UART_RTS, 0, 17)>,
27 <NRF_PSEL(UART_CTS, 0, 16)>;
35 <NRF_PSEL(UART_RTS, 0, 17)>,
36 <NRF_PSEL(UART_CTS, 0, 16)>;
37 low-power-enable;
52 low-power-enable;
69 low-power-enable;
/Zephyr-Core-3.4.0/scripts/coredump/gdbstubs/arch/
Dx86_64.py5 # SPDX-License-Identifier: Apache-2.0
35 RIP = 16
36 EFLAGS = 17
66 IV_X87_FPU_FP_ERROR = 16
67 IV_ALIGNMENT_CHECK = 17
77 # Mapping is from GDB's gdb/i386-stubs.c
82 ExceptionVectors.IV_OVERFLOW: 16,
83 ExceptionVectors.IV_BOUND_RANGE: 16,
150 self.registers[RegNum.RBP] = tu[16]
153 self.registers[RegNum.RBX] = tu[17]
[all …]
/Zephyr-Core-3.4.0/include/zephyr/dt-bindings/pinctrl/
Drpi-pico-rp2040-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
47 #define UART0_TX_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_UART)
48 #define UART0_RX_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_UART)
78 #define I2C0_SDA_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_I2C)
79 #define I2C0_SCL_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_I2C)
109 #define PWM_0A_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PWM)
110 #define PWM_0B_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PWM)
140 #define SPI0_RX_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_SPI)
141 #define SPI0_CSN_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_SPI)
176 #define PIO0_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PIO0)
[all …]
/Zephyr-Core-3.4.0/soc/arm/microchip_mec/mec172x/reg/
Dmec172x_ecia.h4 * SPDX-License-Identifier: Apache-2.0
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
60 * Each GIRQ is composed of 5 32-bit registers.
63 * +08h = Read-Only Result = Source AND Enable-Set
69 * 0x200: BLOCK_EN_SET bit == 1 connects bit-wise OR of all GIRQn result
72 * 0x204: BLOCK_EN_CLR bit == 1 disconnects bit-wise OR of GIRQn source
[all …]
/Zephyr-Core-3.4.0/boards/arm/wio_terminal/
Draspberrypi_40pins_connector.dtsi3 * SPDX-License-Identifier: Apache-2.0
8 compatible = "raspberrypi-40pins-header";
9 #gpio-cells = <2>;
10 gpio-map-mask = <0xffffffff 0xffffffc0>;
11 gpio-map-pass-thru = <0 0x3f>;
12 gpio-map = <0 0 &porta 17 0>, /* I2C1_SDA */
13 <1 0 &porta 16 0>, /* I2C1_SCL */
18 <6 0 &portb 16 0>, /* I2S_BLCK */
28 <16 0 &porta 5 0>, /* DAC1 */
29 <17 0 &porta 13 0>, /* I2C0_SDA */
/Zephyr-Core-3.4.0/soc/arm/renesas_rcar/gen3/
Dpfc_r8a77951.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77951.h>
17 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
28 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
39 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
50 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
61 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
72 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
83 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
94 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
[all …]
/Zephyr-Core-3.4.0/soc/riscv/riscv-ite/it8xxx2/
Dilm.c4 * SPDX-License-Identifier: Apache-2.0
20 * IT8xxx2 allows 4-kilobyte blocks of RAM be configured individually as either Instruction- or
32 * address range non-cacheable (which is appropriate because Flash has high latency but RAM is
42 BUILD_ASSERT((ILM_BLOCK_SIZE & (ILM_BLOCK_SIZE - 1)) == 0, "ILM_BLOCK_SIZE must be a power of two");
53 * SCAR registers contain 20-bit addresses in three registers, with one set
61 /* Bits 16..18 and 19 of address, plus the enable bit for the entire SCAR; SCARnH */
76 return ((uintptr_t)p & (ILM_BLOCK_SIZE - 1)) == 0; in is_block_aligned()
83 return -EFAULT; /* Not in RAM */ in it8xxx2_configure_ilm_block()
85 const int dirmap_index = ((uintptr_t)ram_addr - RAM_BASE) / ILM_BLOCK_SIZE; in it8xxx2_configure_ilm_block()
87 if (dirmap_index >= ARRAY_SIZE(config->scar_regs)) { in it8xxx2_configure_ilm_block()
[all …]
/Zephyr-Core-3.4.0/boards/arm/actinius_icarus/
Dfeather_connector.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "adafruit-feather-header";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpio0 14 0>, /* A1 */
15 <2 0 &gpio0 16 0>, /* A3 */
16 <3 0 &gpio0 17 0>, /* A4 */
29 <16 0 &gpio0 0 0>, /* 0 */
30 <17 0 &gpio0 1 0>, /* 1 */
/Zephyr-Core-3.4.0/samples/drivers/led_xec/
DREADME.rst9 This sample allows to test the Microchip led-xec driver which uses the
10 breathing-blinking LED (BBLED) controllers. The SoC design is fixed
24 - Turning on
25 - Turning off
26 - Blinking on: 0.1 sec, off: 0.1 sec
27 - Blinking on: 1 sec, off: 1 sec
34 Connect GPIO 0156 to board LED4 by placing a wire from JP71-11 to J47-3.
35 Make sure there are no jumpers on JP54 1-2 and JP21 4-5
38 Connect GPIO 0156 to board LED5 by placing a wire from JP71-12 to J48-3.
39 Make sure there are no jumpers on JP54 3-4 and JP21 16-17
[all …]

12345678910>>...28