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/Zephyr-Core-3.5.0/dts/bindings/pcie/host/
Dpci-host-ecam-generic.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "pci-host-ecam-generic"
8 include: pcie-controller.yaml
14 msi-parent:
21 As described in IEEE Std 1275-1994, but must provide at least a
22 definition of non-prefetchable memory. One or both of prefetchable Memory
25 interrupt-map-mask:
28 interrupt-map:
31 bus-range:
/Zephyr-Core-3.5.0/doc/build/dts/api/
Dapi.rst10 Some of these -- the ones beginning with ``DT_INST_`` -- require a special
19 .. _devicetree-generic-apis:
33 :ref:`devicetree-property-access` API.
45 .. doxygengroup:: devicetree-generic-id
47 .. _devicetree-property-access:
52 The following general-purpose macros can be used to access node properties.
53 There are special-purpose APIs for accessing the :ref:`devicetree-ranges-property`,
54 :ref:`devicetree-reg-property` and :ref:`devicetree-interrupts-property`.
59 .. doxygengroup:: devicetree-generic-prop
61 .. _devicetree-ranges-property:
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/Zephyr-Core-3.5.0/include/zephyr/drivers/pcie/
Dcontroller.h10 * SPDX-License-Identifier: Apache-2.0
34 * @brief Function called to read a 32-bit word from an endpoint's configuration space.
36 * Read a 32-bit word from an endpoint's configuration space with the PCI Express Controller
48 * @brief Function called to write a 32-bit word to an endpoint's configuration space.
50 * Write a 32-bit word to an endpoint's configuration space with the PCI Express Controller
75 * @param bar_bus_addr bus-centric address allocated to be written in the BAR register
94 * @param bar_base_addr bus-centric address allocation base
102 * @brief Function called to translate an endpoint Base Address Register bus-centric address
108 * The bus-centric address set in this BAR register is not necessarily accessible from the CPU,
116 * @param bar_bus_addr bus-centric address written in the BAR register
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/Zephyr-Core-3.5.0/drivers/pcie/host/
Dpcie_ecam.c4 * SPDX-License-Identifier: Apache-2.0
24 * - handle prefetchable regions
47 const struct pcie_ctrl_config *cfg = dev->config; in pcie_ecam_init()
48 struct pcie_ecam_data *data = dev->data; in pcie_ecam_init()
52 * Flags defined in the PCI Bus Binding to IEEE Std 1275-1994 : in pcie_ecam_init()
64 * t is 1 if the address is aliased (for non-relocatable I/O), below 1 MB (for Memory), in pcie_ecam_init()
69 * 10 denotes 32-bit-address Memory Space in pcie_ecam_init()
70 * 11 denotes 64-bit-address Memory Space in pcie_ecam_init()
71 * bbbbbbbb is the 8-bit Bus Number in pcie_ecam_init()
72 * ddddd is the 5-bit Device Number in pcie_ecam_init()
[all …]
/Zephyr-Core-3.5.0/include/zephyr/sys/
Dutil_internal_util_dec.h2 * Copyright (c) 2011-2014, Wind River Systems, Inc.
6 * SPDX-License-Identifier: Apache-2.0
1296 #define Z_UTIL_DEC_1276 1275
2015 #define Z_UTIL_DEC_1995 1994
Dutil_internal_util_inc.h2 * Copyright (c) 2011-2014, Wind River Systems, Inc.
6 * SPDX-License-Identifier: Apache-2.0
1294 #define Z_UTIL_INC_1274 1275
2013 #define Z_UTIL_INC_1993 1994
Dutil_listify.h5 * SPDX-License-Identifier: Apache-2.0
5118 F(1275, __VA_ARGS__)
7994 F(1994, __VA_ARGS__)