Searched +full:11898 +full:- +full:1 (Results 1 – 6 of 6) sorted by relevance
| /Zephyr-Core-3.5.0/dts/bindings/can/ |
| D | can-controller.yaml | 6 bus-speed:
11 sample-point:
17 (`sjw`, `prop-seg`, `phase-seg1`, and `phase-seg2`).
23 default: 1
25 Initial time quanta of resynchronization jump width (ISO 11898-1).
28 timing parameters. Default of 1 matches the default value previously used for all in-tree CAN
32 prop-seg:
36 Initial time quanta of propagation segment (ISO 11898-1). Deprecated in favor of setting
38 phase-seg1:
42 Initial time quanta of phase buffer 1 segment (ISO 11898-1). Deprecated in favor of setting
[all …]
|
| /Zephyr-Core-3.5.0/drivers/can/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
17 module-str = CAN
39 range 1 256
46 range 1 256
59 bool "CAN-FD"
61 Enable CAN-FD support. Not all CAN controllers support CAN-FD.
71 bool "Automatic recovery from bus-off"
74 This option enables the automatic bus-off recovery according to
75 ISO 11898-1 (recovery after 128 occurrences of 11 consecutive
85 the "-object can-host-socketcan" qemu command line option. The CAN interface must be
|
| /Zephyr-Core-3.5.0/doc/hardware/peripherals/canbus/ |
| D | controller.rst | 13 Controller Area Network is a two-wire serial bus specified by the
14 Bosch CAN Specification, Bosch CAN with Flexible Data-Rate specification and the
15 ISO 11898-1:2003 standard.
20 from the CAN controller to the bus-levels. The bus lines are called
24 These wires use the logic levels whereas the bus-level is interpreted
29 To write a dominant bit to the bus, open-drain transistors tie CAN H to Vdd
31 The first and last node use a 120-ohm resistor between CAN H and CAN L to
33 This structure is called a wired-AND.
48 The bit-timing as defined in ISO 11898-1:2003 looks as following:
63 The bit-rate is calculated from the time of a time quantum and the values
[all …]
|
| /Zephyr-Core-3.5.0/boards/shields/mcp2515/doc/ |
| D | index.rst | 7 Stand-Alone CAN Controller with SPI Interface.
13 --------
15 The DFRobot CAN BUS shield supports the Microchip MCP2515 stand-alone CAN
24 --------
26 - MCP2515
28 - Stand-Alone CAN 2.0B Controller
29 - Up to 1Mb/s baud rate
30 - Standard and extended data and remote frames
31 - 3x Tx Buffers
32 - 2x Rx Buffers
[all …]
|
| /Zephyr-Core-3.5.0/boards/xtensa/esp32s3_luatos_core/doc/ |
| D | index.rst | 3 ESP32S3-Luatos-Core
9 The ESP32S3-LUATOS-CORE development board is a compact board based on Espressif ESP32-S3.
10 The board comes equipped with a 2.4GHz antenna and supports both Wi-Fi and Bluetooth functionalitie…
11 For more information, check `ESP32S3-LUATOS-CORE`_ (chinese)
20 ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi
21 and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor
22 (Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband,
25 ESP32S3-LUATOS-CORE includes the following features:
27 - Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz
28 - Additional vector instructions support for AI acceleration
[all …]
|
| /Zephyr-Core-3.5.0/boards/xtensa/esp32s3_devkitm/doc/ |
| D | index.rst | 3 ESP32S3-DevKitM
9 The ESP32-S3-DevKitM is an entry-level development board equipped with either ESP32-S3-MINI-1
10 or ESP32-S3-MINI-1U, a module named for its small size. This board integrates complete Wi-Fi
11 and Bluetooth Low Energy functions. For more information, check `ESP32-S3 DevKitM`_
16 ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi
17 and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor
18 (Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband,
21 ESP32-S3 DevKitM includes the following features:
23 - Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz
24 - Additional vector instructions support for AI acceleration
[all …]
|
