Searched +full:108 +full:mhz (Results 1 – 15 of 15) sorted by relevance
| /Zephyr-Core-3.4.0/dts/bindings/timer/ |
| D | nuclei,systimer.yaml | 30 For example, the CPU clock frequency is 108MHz, and the system timer
31 uses 27MHz, which is the CPU clock divided by 4.
45 that CPU clock frequency divided by (2^2=)4, or 27MHz.
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| /Zephyr-Core-3.4.0/soc/riscv/riscv-privileged/gd32vf103/ |
| D | Kconfig.defconfig.gd32vf103 | 14 # The CPU frequency is set to the maximum value of 108MHz by default.
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| /Zephyr-Core-3.4.0/boards/riscv/gd32vf103c_starter/doc/ |
| D | index.rst | 13 to 108 MHz with flash accesses zero wait states, 128 KiB of Flash, 32 KiB of
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| /Zephyr-Core-3.4.0/boards/arm/gd32f350r_eval/doc/ |
| D | index.rst | 13 to 108-MHz with flash accesses zero wait states, 128kB of Flash, 16kB of
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| /Zephyr-Core-3.4.0/boards/arm/nucleo_l496zg/doc/ |
| D | index.rst | 42 - Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 uA/MHz run mode)
43 … |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhryst…
46 - 4 to 48 MHz crystal oscillator
48 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
50 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
172 as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
173 driven by 16MHz high speed internal oscillator.
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| /Zephyr-Core-3.4.0/boards/riscv/gd32vf103v_eval/doc/ |
| D | index.rst | 13 to 108 MHz with flash accesses zero wait states, 128 KiB of Flash, 32 KiB of
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| /Zephyr-Core-3.4.0/boards/arm/stm32l496g_disco/doc/ |
| D | index.rst | 55 - Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91
56 |micro| A/MHz run mode)
57 - Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz,
58 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1)
61 - 4 to 48 MHz crystal oscillator
63 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
65 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
67 - Internal 48 MHz with clock recovery
186 as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz,
187 driven by 16MHz high speed internal oscillator.
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| /Zephyr-Core-3.4.0/boards/arm/nucleo_wl55jc/doc/ |
| D | nucleo_wl55jc.rst | 15 (Arm® Cortex®-M4/M0+ at 48 MHz) in UFBGA73 package featuring:
18 - RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®,
25 - 32 MHz HSE on-board oscillator
62 - Frequency range: 150 MHz to 960 MHz
70 and the Japanese ARIB STD-T30, T-67, T-108
79 execution from Flash memory, frequency up to 48 MHz, MPU
81 - 1.25 DMIPS/MHz (Dhrystone 2.1)
85 - Frequency up to 48 MHz, MPU
86 - 0.95 DMIPS/MHz (Dhrystone 2.1)
113 - 32 MHz crystal oscillator
[all …]
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| /Zephyr-Core-3.4.0/boards/arm/nucleo_l4a6zg/doc/ |
| D | index.rst | 42 - Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 uA/MHz run mode)
43 … |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhryst…
46 - 4 to 48 MHz crystal oscillator
48 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
50 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
169 as well as main PLL clock. By default, system clock is driven by PLL at 80MHz, which is
170 driven by 16MHz high speed internal oscillator (HSI). High speed external oscillator
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| /Zephyr-Core-3.4.0/boards/arm/nucleo_l552ze_q/doc/ |
| D | nucleol552ze_q.rst | 44 They operate at a frequency of up to 110 MHz.
46 - Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 62 uA/MHz run mode)
50 - 1.5 DMPIS/MHz (Drystone 2.1)
51 - 442 CoreMark |reg| (4.02 CoreMark |reg| /MHZ)
68 - 4 to 48 MHz crystal oscillator
70 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
72 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
273 110MHz, driven by 4MHz medium speed internal oscillator.
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| /Zephyr-Core-3.4.0/boards/arm/stm32f746g_disco/ |
| D | stm32f746g_disco.dts | 235 * Note: SDRAM_CLK_MHZ = HCLK_MHZ / 2 (108 MHz)
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| /Zephyr-Core-3.4.0/boards/arm/stm32f7508_dk/ |
| D | stm32f7508_dk.dts | 232 * Note: SDRAM_CLK_MHZ = HCLK_MHZ / 2 (108 MHz)
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| /Zephyr-Core-3.4.0/boards/arm/stm32l562e_dk/doc/ |
| D | index.rst | 57 They operate at a frequency of up to 110 MHz.
59 - Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 62 uA/MHz run mode)
63 - 1.5 DMPIS/MHz (Drystone 2.1)
64 - 442 CoreMark |reg| (4.02 CoreMark |reg| /MHZ)
84 - 4 to 48 MHz crystal oscillator
86 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
88 - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
275 110MHz, driven by 4MHz medium speed internal oscillator.
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| /Zephyr-Core-3.4.0/drivers/audio/ |
| D | tlv320dac310x.c | 346 /* calculate MCLK divider to get ~1MHz */ in codec_configure_clocks()
442 107, 108, 110, 113, 116, 120, 125, 128, 132, 138, 144 in codec_set_output_volume()
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| /Zephyr-Core-3.4.0/dts/arm/nxp/ |
| D | nxp_rt10xx.dtsi | 102 interrupts = <108 0>;
919 * = (24MHz * (32 + 77 / 100)) / 1 = 786.48 MHz
927 /* The maximum input frequency into the SAI mclk input is 300MHz
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