| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | ti,boosterpack-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
10 20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
11 10 x 2 pin headers. Both variants are compatible and stackable.
13 The pins of the 20 pin variant and the outer row of the 40 pin variant are
14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
26 10 I2C SDA 30 31 GPIO 11 GPIO
32 compatible: "ti,boosterpack-header"
34 include: [gpio-nexus.yaml, base.yaml]
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| D | atmel-xplained-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained layout provide a standard 10 pin header. A board can have
12 every pin can be defined as general purpose GPIO.
29 https://www.microchip.com/development-tools/xplained-boards
30 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
32 This binding provides a nexus mapping for 10 pins where pins are disposed
36 Bind Pin Name Pin Pin Pin Name Bind
41 GND 9 10 VDD(+3.3V)
43 compatible: "atmel-xplained-header"
45 include: [gpio-nexus.yaml, base.yaml]
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| D | seeed-xiao-header.yaml | 4 # SPDX-License-Identifier: Apache-2.0
12 Proceeding counter-clockwise:
13 * A 7-pin Digital/Analog Input header. This has input signals
15 * An 7-pin header Power and Digital/Analog Input header. This
16 has three power pins, followed by four inputs labeled 10 at the
19 This binding provides a nexus mapping for 10 pins where parent pins 0
20 through 10 correspond to D0 through D10, as depicted below:
22 0 D0 5V -
23 1 D1 GND -
24 2 D2 3V3 -
[all …]
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| D | arduino-header-r3.yaml | 3 # SPDX-License-Identifier: Apache-2.0
11 Proceeding counter-clockwise:
12 * An 8-pin Power Supply header. No pins on this header are exposed
14 * A 6-pin Analog Input header. This has analog input signals
16 * An 8-pin header (opposite Analog Input). This has digital input
18 * A 10-pin header (opposite Power Supply). This has six additional
29 AREF -
30 GND -
31 - N/C D13 19
32 - IOREF D12 18
[all …]
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| D | atmel-xplained-pro-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained Pro layout provide a standard 20 pin header. A board can have
9 names EXTn where n ϵ [1…7], n is determined by which ID pin is connected
28 https://www.microchip.com/development-tools/xplained-boards
29 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
35 Bind Pin Name Pin Pin Pin Name Bind
37 0 ADC(+) 3 4 ADC(-) 1
39 4 PWM(+) 7 8 PWM(-) 5
40 6 IRQ/GPIO3 9 10 SPI(CS1)/GPIO4 7
42 10 UART(RX) 13 14 UART(TX) 11
[all …]
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| D | particle-gen3-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 "shields" but use a different orientation and pin numbering scheme.
11 * A 12-pin header on the right. 9 pins on this header are exposed
13 * A 16-pin header. 13 pins on this header are exposed by this
17 0 through 8 correspond to the pins on the 12-pin header, starting
19 16-pin header, skipping the bottom pin then assigning 9 through 19,
20 skipping over GND, and replacing the lower 3V3 with pin 20. The
24 - 3V3
26 - GND
27 19 ADC0 LiPo+ -
[all …]
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/renesas/ |
| D | pinctrl-rcar-common.h | 4 * SPDX-License-Identifier: Apache-2.0
21 * IPSR bank [ 10 : 13 ]
23 #define IPSR(bank, shift, func) (((bank) << 10U) | ((shift) << 4U) | (func))
25 /* Arbitrary number to encode non capable gpio pin */
29 * @brief Utility macro to encode a GPIO capable pin
32 * @param pin the pin within the GPIO bank (0..31)
34 #define RCAR_GP_PIN(bank, pin) (((bank) * 32U) + (pin)) argument
37 * @brief Utility macro to encode a non capable GPIO pin
39 * @param pin the encoded pin number
41 #define RCAR_NOGP_PIN(pin) (PIN_NOGPSR_START + pin) argument
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| /Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/common/ |
| D | Kconfig.soc | 2 # SPDX-License-Identifier: Apache-2.0
16 bool "Support for external, SPI-connected RAM"
66 bool "ESP-PSRAM16 or APS1604"
69 bool "ESP-PSRAM32 or IS25WP032"
72 bool "ESP-PSRAM64 or LY68L6400"
124 menu "PSRAM clock and cs IO for ESP32-DOWD"
132 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
140 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
142 endmenu # PSRAM clock and cs IO for ESP32-DOWD
144 menu "PSRAM clock and cs IO for ESP32-D2WD"
[all …]
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| /Zephyr-Core-3.5.0/soc/x86/ia32/ |
| D | soc.h | 2 * Copyright (c) 2010-2015, Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
11 * This header file is used to specify and describe board-level aspects for
38 * @brief Convert PCI interrupt PIN to IRQ
41 * INTx are mapped to IRQs 10 and 11 after being swizzled.
43 * @return IRQ number, -1 if the result is incorrect
47 static inline int pci_pin2irq(int bus, int dev, int pin) in pci_pin2irq() argument
51 if ((pin < PCI_INTA) || (pin > PCI_INTD)) { in pci_pin2irq()
52 return -1; in pci_pin2irq()
55 return 10 + (((pin + dev - 1) >> 1) & 1); in pci_pin2irq()
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| /Zephyr-Core-3.5.0/dts/bindings/sensor/ |
| D | st,ism330dhcx-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: sensor-device.yaml
7 drdy-gpios:
8 type: phandle-array
10 DRDY gpio pin
12 This pin defaults to active high when produced by the sensor.
16 int-pin:
20 Select DRDY pin number (1 or 2).
29 configuration at power-up.
31 - 1
[all …]
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| /Zephyr-Core-3.5.0/boards/shields/x_nucleo_eeprma2/ |
| D | x_nucleo_eeprma2.overlay | 4 * SPDX-License-Identifier: Apache-2.0
12 eeprom-0 = &eeprom0_x_nucleo_eeprma2;
13 eeprom-1 = &eeprom4_x_nucleo_eeprma2;
19 clock-frequency = <I2C_BITRATE_FAST>;
22 /* M24C02-FMC6TG aka U1 (2 kbit eeprom in DFN8 package) */
27 address-width = <8>;
30 /* if solder-bridge closed: arduino A1 pin on CN8 can wp */
31 /* wp-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; */
35 /* M24256-DFDW6TP aka U2 (256 kbit eeprom in TSSOP package) */
40 address-width = <16>;
[all …]
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| /Zephyr-Core-3.5.0/dts/bindings/display/ |
| D | solomon,ssd1306fb-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: display-controller.yaml
7 segment-offset:
10 description: 8-bit column start address for Page Addressing Mode
12 page-offset:
17 display-offset:
22 multiplex-ratio:
27 segment-remap:
31 com-invdir:
35 com-sequential:
[all …]
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| /Zephyr-Core-3.5.0/tests/kernel/timer/timer_behavior/ |
| D | Kconfig | 1 # SPDX-License-Identifier: Apache-2.0
26 default 10
41 default 10
43 A value of 10 means 10%.
48 Toggles a GPIO pin, on every period, that can be used by an external
59 connected to a GPIO pin is used to measure time behaviour.
66 connected to a GPIO pin is used to measure time behaviour.
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| /Zephyr-Core-3.5.0/dts/bindings/ethernet/ |
| D | wiznet,w5500.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: W5500 standalone 10/100BASE-T Ethernet controller with SPI interface
8 include: [spi-device.yaml, ethernet-controller.yaml]
11 int-gpios:
12 type: phandle-array
14 description: Interrupt pin.
16 The interrupt pin of W5500 is active low.
17 If connected directly the MCU pin should be configured
19 reset-gpios:
20 type: phandle-array
[all …]
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| D | adi,adin2111.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 ADIN2111 standalone 10BASE-T1L Ethernet controller with SPI interface.
12 spi-max-frequency = <25000000>;
13 int-gpios = <&gpioe 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
14 reset-gpios = <&gpioe 8 GPIO_ACTIVE_LOW>;
16 local-mac-address = [ CA 2F B7 10 23 63 ];
19 local-mac-address = [ 3C 82 D4 A2 29 8E ];
22 compatible = "adi,adin2111-mdio";
24 #address-cells = <1>;
25 #size-cells = <0>;
[all …]
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| D | microchip,enc28j60.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: ENC28J60 standalone 10BASE-T Ethernet controller with SPI interface
8 include: [spi-device.yaml, ethernet-controller.yaml]
11 int-gpios:
12 type: phandle-array
14 description: Interrupt pin.
16 The interrupt pin of ENC28J60 is active low.
17 If connected directly the MCU pin should be configured
20 full-duplex:
23 Optional feature flag - Enables full duplex reception and transmission.
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| /Zephyr-Core-3.5.0/tests/drivers/pinctrl/gd32/src/ |
| D | main_af.c | 3 * SPDX-License-Identifier: Apache-2.0
9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
19 zassert_equal(pcfg->state_cnt, 1U); in ZTEST()
21 scfg = &pcfg->states[0]; in ZTEST()
23 zassert_equal(scfg->id, PINCTRL_STATE_DEFAULT); in ZTEST()
24 zassert_equal(scfg->pin_cnt, 12U); in ZTEST()
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
[all …]
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| D | main_afio.c | 3 * SPDX-License-Identifier: Apache-2.0
9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
19 zassert_equal(pcfg->state_cnt, 1U); in ZTEST()
21 scfg = &pcfg->states[0]; in ZTEST()
23 zassert_equal(scfg->id, PINCTRL_STATE_DEFAULT); in ZTEST()
24 zassert_equal(scfg->pin_cnt, 14U); in ZTEST()
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
[all …]
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| /Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/common/ |
| D | pinctrl_soc.h | 4 * SPDX-License-Identifier: Apache-2.0
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
107 /* MIO pin numbers */
118 #define MIO10 10
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
169 #define MIO_GROUP_QSPI1_0_GRP_PINS 9, 10, 11, 12, 13
184 #define MIO_GROUP_SPI1_0_GRP_PINS 10, 11, 12
203 #define MIO_GROUP_SDIO1_0_GRP_PINS 10, 11, 12, 13, 14, 15
211 #define MIO_GROUP_SMC0_NOR_PINS 0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, \
[all …]
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| /Zephyr-Core-3.5.0/dts/bindings/spi/ |
| D | spi-controller.yaml | 1 # Copyright (c) 2018, I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
11 clock-frequency:
15 "#address-cells":
18 "#size-cells":
21 cs-gpios:
22 type: phandle-array
31 cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
32 <&gpio1 10 GPIO_ACTIVE_LOW>,
35 spi-device@0 {
[all …]
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| /Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/reg/ |
| D | mec172x_gpio.h | 4 * SPDX-License-Identifier: Apache-2.0
54 /* bit[8] output buffer type: push-pull or open-drain */
67 * bit[10] Alternate output disable. Default==0(alternate output enabled)
69 * Set bit[10]=1 if you wish to control pin output using the parallel
70 * GPIO output register bit for this pin.
72 #define MCHP_GPIO_CTRL_AOD_POS 10
80 /* bits[14:12] pin mux (function) */
103 /* bit[16]: Alternate output pin value. Enabled when bit[10]==0(default) */
116 * Each GPIO pin implements a second control register.
117 * GPIO Control 2 register selects pin drive strength and slew rate.
[all …]
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| /Zephyr-Core-3.5.0/tests/drivers/gpio/gpio_basic_api/boards/ |
| D | em_starterkit.overlay | 5 * SPDX-License-Identifier: Apache-2.0
10 compatible = "test-gpio-basic-api";
11 out-gpios = <&gpio0 18 0>; /* Pmod3 pin 9 */
12 in-gpios = <&gpio0 19 0>; /* Pmod3 pin 10 */
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| D | quick_feather.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "test-gpio-basic-api";
10 out-gpios = <&gpio 2 0>; /* Header J8 - pin 6 */
11 in-gpios = <&gpio 0 0>; /* Header J8 - pin 10 */
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| /Zephyr-Core-3.5.0/soc/x86/alder_lake/ |
| D | soc_gpio.h | 2 * Copyright (c) 2021-2023, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
18 #define GPIO_INTEL_NR_SUBDEVS 10
22 #define PAD_CFG0_PMODE_MASK (0x0F << 10)
44 #define GPIO_RAW_PIN(pin, pin_offset) pin argument
47 (cfg->group_index * 0x4)
50 (cfg->group_index * 0x4)
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| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | st,stm32f1-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32F1 Pin controller Node
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32f1-pinctrl"
20 swj-cfg:
24 - "full"
25 - "no-njtrst"
26 - "jtag-disable"
[all …]
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