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/hal_espressif-3.5.0/components/soc/esp32/include/soc/
Dslc_struct.h26 uint32_t slc0_tx_rst: 1;
27 uint32_t slc0_rx_rst: 1;
28 uint32_t ahbm_fifo_rst: 1;
29 uint32_t ahbm_rst: 1;
30 uint32_t slc0_tx_loop_test: 1;
31 uint32_t slc0_rx_loop_test: 1;
32 uint32_t slc0_rx_auto_wrback: 1;
33 uint32_t slc0_rx_no_restart_clr: 1;
34 uint32_t slc0_rxdscr_burst_en: 1;
35 uint32_t slc0_rxdata_burst_en: 1;
[all …]
Dhost_struct.h31 uint32_t func2_int: 1;
38 uint32_t func2_int_en: 1;
47 uint32_t func1_mdstat: 1;
75 uint32_t rx_pf_valid: 1;
86 uint32_t tohost_bit0: 1;
87 uint32_t tohost_bit1: 1;
88 uint32_t tohost_bit2: 1;
89 uint32_t tohost_bit3: 1;
90 uint32_t tohost_bit4: 1;
91 uint32_t tohost_bit5: 1;
[all …]
Di2s_struct.h28 uint32_t tx_reset: 1;
29 uint32_t rx_reset: 1;
30 uint32_t tx_fifo_reset: 1;
31 uint32_t rx_fifo_reset: 1;
32 uint32_t tx_start: 1;
33 uint32_t rx_start: 1;
34 uint32_t tx_slave_mod: 1;
35 uint32_t rx_slave_mod: 1;
36 uint32_t tx_right_first: 1;
37 uint32_t rx_right_first: 1;
[all …]
Drtc_cntl_struct.h26 …c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will st…
27 …c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will st…
28 uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/
29 uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/
30 uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/
31 uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/
32 uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/
33 uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/
34 uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/
35 uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/
[all …]
/hal_espressif-3.5.0/components/mdns/test_afl_fuzz_host/
Dsdkconfig.h6 #define CONFIG_IDF_CMAKE 1
8 #define CONFIG_IDF_TARGET_ESP32 1
11 #define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1
12 #define CONFIG_APP_BUILD_GENERATE_BINARIES 1
13 #define CONFIG_APP_BUILD_BOOTLOADER 1
14 #define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1
15 #define CONFIG_APP_COMPILE_TIME_DATE 1
17 #define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1
18 #define CONFIG_BOOTLOADER_LOG_LEVEL_INFO 1
20 #define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1
[all …]
/hal_espressif-3.5.0/components/soc/esp32s2/include/soc/
Dusbh_struct.h27 uint32_t sesreqscs: 1;
28 uint32_t sesreq: 1;
29 uint32_t vbvalidoven: 1;
30 uint32_t vbvalidovval: 1;
31 uint32_t avalidoven: 1;
32 uint32_t avalidovval: 1;
33 uint32_t bvalidoven: 1;
34 uint32_t bvalidovval: 1;
35 uint32_t hstnegscs: 1;
36 uint32_t hnpreq: 1;
[all …]
Duart_struct.h29 uint32_t rxfifo_full: 1;
30 uint32_t txfifo_empty: 1;
31 uint32_t parity_err: 1;
32 uint32_t frm_err: 1;
33 uint32_t rxfifo_ovf: 1;
34 uint32_t dsr_chg: 1;
35 uint32_t cts_chg: 1;
36 uint32_t brk_det: 1;
37 uint32_t rxfifo_tout: 1;
38 uint32_t sw_xon: 1;
[all …]
Duhci_struct.h23 uint32_t in_rst: 1;
24 uint32_t out_rst: 1;
25 uint32_t ahbm_fifo_rst: 1;
26 uint32_t ahbm_rst: 1;
27 uint32_t in_loop_test: 1;
28 uint32_t out_loop_test: 1;
29 uint32_t out_auto_wrback: 1;
30 uint32_t out_no_restart_clr: 1;
31 uint32_t out_eof_mode: 1;
32 uint32_t uart0_ce: 1;
[all …]
Drtc_cntl_struct.h25 …c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will sta…
26 …c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will sta…
27 uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/
28 uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/
29 uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/
30 uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/
31 uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/
32 uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/
33 uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/
34 uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/
[all …]
Dledc_struct.h26 …uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channe…
27 …uint32_t idle_lv: 1; /*This bit is used to control the output value when high spee…
28 …uint32_t low_speed_update: 1; /*This bit is only useful for low speed timer channels, reser…
30 uint32_t ovf_cnt_en: 1;
31 uint32_t ovf_cnt_rst: 1;
32 uint32_t ovf_cnt_rst_st: 1;
56 uint32_t duty_inc: 1;
57 uint32_t duty_start: 1;
69 } channel_group[1]; /* single channel group, low speed mode only */
76 uint32_t pause: 1;
[all …]
Di2c_struct.h30 uint32_t sda_force_out: 1;
31 uint32_t scl_force_out: 1;
32 uint32_t sample_scl_level: 1;
33 uint32_t rx_full_ack_level: 1;
34 uint32_t ms_mode: 1;
35 uint32_t trans_start: 1;
36 uint32_t tx_lsb_first: 1;
37 uint32_t rx_lsb_first: 1;
38 uint32_t clk_en: 1;
39 uint32_t arbitration_en: 1;
[all …]
/hal_espressif-3.5.0/components/soc/esp32s3/include/soc/
Dusbh_struct.h28 uint32_t sesreqscs: 1;
29 uint32_t sesreq: 1;
30 uint32_t vbvalidoven: 1;
31 uint32_t vbvalidovval: 1;
32 uint32_t avalidoven: 1;
33 uint32_t avalidovval: 1;
34 uint32_t bvalidoven: 1;
35 uint32_t bvalidovval: 1;
36 uint32_t hstnegscs: 1;
37 uint32_t hnpreq: 1;
[all …]
Drtc_cntl_struct.h19 … : 2; /*{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will sta…
20 … : 2; /*{reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will sta…
21 uint32_t sw_appcpu_rst : 1; /*APP CPU SW reset*/
22 uint32_t sw_procpu_rst : 1; /*PRO CPU SW reset*/
23 uint32_t bb_i2c_force_pd : 1; /*BB_I2C force power down*/
24 uint32_t bb_i2c_force_pu : 1; /*BB_I2C force power up*/
25 uint32_t bbpll_i2c_force_pd : 1; /*BB_PLL _I2C force power down*/
26 uint32_t bbpll_i2c_force_pu : 1; /*BB_PLL_I2C force power up*/
27 uint32_t bbpll_force_pd : 1; /*BB_PLL force power down*/
28 uint32_t bbpll_force_pu : 1; /*BB_PLL force power up*/
[all …]
Dhost_struct.h34 uint32_t func1_mdstat : 1;
62 uint32_t rx_pf_valid : 1;
73 uint32_t tohost_bit0 : 1;
74 uint32_t tohost_bit1 : 1;
75 uint32_t tohost_bit2 : 1;
76 uint32_t tohost_bit3 : 1;
77 uint32_t tohost_bit4 : 1;
78 uint32_t tohost_bit5 : 1;
79 uint32_t tohost_bit6 : 1;
80 uint32_t tohost_bit7 : 1;
[all …]
Dledc_struct.h29 uint32_t sig_out_en: 1;
30 uint32_t idle_lv: 1;
31 uint32_t low_speed_update: 1;
33 uint32_t ovf_cnt_en: 1;
34 uint32_t ovf_cnt_rst: 1;
35 uint32_t ovf_cnt_rst_st: 1;
59 uint32_t duty_inc: 1;
60 uint32_t duty_start: 1;
72 } channel_group[1];
79 uint32_t pause: 1;
[all …]
Dassist_debug_struct.h26 uint32_t core_0_area_dram0_0_rd : 1;
27 uint32_t core_0_area_dram0_0_wr : 1;
28 uint32_t core_0_area_dram0_1_rd : 1;
29 uint32_t core_0_area_dram0_1_wr : 1;
30 uint32_t core_0_area_pif_0_rd : 1;
31 uint32_t core_0_area_pif_0_wr : 1;
32 uint32_t core_0_area_pif_1_rd : 1;
33 uint32_t core_0_area_pif_1_wr : 1;
34 uint32_t core_0_sp_spill_min : 1;
35 uint32_t core_0_sp_spill_max : 1;
[all …]
Dsens_struct.h21 uint32_t sar1_clk_gated : 1;
23 uint32_t reserved27 : 1;
24 uint32_t sar1_data_inv : 1; /*Invert SAR ADC1 data*/
25 uint32_t sar1_int_en : 1; /*enable saradc1 to send out interrupt*/
44 uint32_t meas1_done_sar : 1; /*SAR ADC1 conversion done indication*/
45 … uint32_t meas1_start_sar : 1; /*SAR ADC1 controller (in RTC) starts conversion*/
46 …uint32_t meas1_start_force : 1; /*1: SAR ADC1 controller (in RTC) is started by SW…
48 …uint32_t sar1_en_pad_force : 1; /*1: SAR ADC1 pad enable bitmap is controlled by S…
55 … uint32_t sar1_dig_force : 1; /*1: SAR ADC1 controlled by DIG ADC1 CTRL*/
69 uint32_t sar1_dac_xpd_fsm_idle : 1;
[all …]
/hal_espressif-3.5.0/tools/test_apps/peripherals/i2c_wifi/
DREADME.md9 1. Switch on wifi softAP, and connect to your personal device, like your mobile phone.
14 1. Receive data from master board.
97 I (609) I2C-wifi test: wifi_init_softap finished. SSID:myssid password:mypassword channel:1
106 I (23609) I2C-wifi test: 6a 1b 05 1f 1f 08 01 20 19 03 27
107 I (23619) I2C-wifi test: 6a 1b 05 1f 1f 08 01 20 19 03 27
108 I (23629) I2C-wifi test: 6a 1b 05 1f 1f 08 01 20 19 03 27
109 I (23639) I2C-wifi test: 6a 1b 05 1f 1f 08 01 20 19 03 27
110 I (23649) I2C-wifi test: 6a 1b 05 1f 1f 08 01 20 19 03 27
111 I (23659) I2C-wifi test: 6a 1b 05 1f 1f 08 01 20 19 03 27
112 I (23669) I2C-wifi test: 6a 1b 05 1f 1f 08 01 20 19 03 27
[all …]
/hal_espressif-3.5.0/components/soc/esp32h2/include/soc/
Drtc_cntl_struct.h23 … 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will sta…
24 … 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will sta…
25 uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/
26 uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/
27 uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/
28 uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/
29 uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/
30 uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/
31 uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/
32 uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/
[all …]
Drmt_struct.h27 uint32_t tx_start: 1;
28 uint32_t mem_rd_rst: 1;
29 uint32_t mem_rst: 1;
30 uint32_t tx_conti_mode: 1;
31 uint32_t mem_tx_wrap_en: 1;
32 uint32_t idle_out_lv: 1;
33 uint32_t idle_out_en: 1;
34 uint32_t tx_stop: 1;
37 uint32_t reserved19: 1;
38 uint32_t carrier_eff_en: 1;
[all …]
Di2c_struct.h33 uint32_t sda_force_out : 1;
34 uint32_t scl_force_out : 1;
35 uint32_t sample_scl_level : 1;
36 uint32_t rx_full_ack_level : 1;
37 uint32_t ms_mode : 1;
38 uint32_t trans_start : 1;
39 uint32_t tx_lsb_first : 1;
40 uint32_t rx_lsb_first : 1;
41 uint32_t clk_en : 1;
42 uint32_t arbitration_en : 1;
[all …]
/hal_espressif-3.5.0/components/soc/esp32c3/include/soc/
Drtc_cntl_struct.h23 …: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will sta…
24 …: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will sta…
25 uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/
26 uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/
27 uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/
28 uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/
29 uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/
30 uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/
31 uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/
32 uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/
[all …]
Drmt_struct.h27 uint32_t tx_start: 1;
28 uint32_t mem_rd_rst: 1;
29 uint32_t mem_rst: 1;
30 uint32_t tx_conti_mode: 1;
31 uint32_t mem_tx_wrap_en: 1;
32 uint32_t idle_out_lv: 1;
33 uint32_t idle_out_en: 1;
34 uint32_t tx_stop: 1;
37 uint32_t reserved19: 1;
38 uint32_t carrier_eff_en: 1;
[all …]
Di2c_struct.h33 uint32_t sda_force_out : 1;
34 uint32_t scl_force_out : 1;
35 uint32_t sample_scl_level : 1;
36 uint32_t rx_full_ack_level : 1;
37 uint32_t ms_mode : 1;
38 uint32_t trans_start : 1;
39 uint32_t tx_lsb_first : 1;
40 uint32_t rx_lsb_first : 1;
41 uint32_t clk_en : 1;
42 uint32_t arbitration_en : 1;
[all …]
/hal_espressif-3.5.0/components/spi_flash/esp32s3/
Dmspi_timing_tuning_configs.h9 …MODULE_CLK_40M_DTR_MODE {{1, 0, 0}, {0, 0, 0}, {2, 1, 1}, {2, 0, 1}, {2, 2, 2}, {2, 1, 2},…
14 … {{0, 0, 0}, {4, 2, 2}, {2, 1, 2}, {4, 1, 2}, {1, 0, 1}, {4, 0, 2}, {0, 0, 1}, {4, 2, 3}, {2,…
16 #define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE 1
19 …, 0}, {4, 1, 2}, {1, 0, 1}, {4, 0, 2}, {0, 0, 1}, {4, 1, 3}, {1, 0, 2}, {4, 0, 3}, {0, 0, 2}, {4, …
21 #define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE 1
24 …MODULE_CLK_80M_STR_MODE {{1, 0, 0}, {0, 0, 0}, {2, 1, 1}, {2, 0, 1}, {2, 2, 2}, {2, 1, 2},…
29 …DE {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {1, 0, 1}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {1, 0, 2},…
34 …_STR_MODE {{1, 0, 0}, {0, 0, 0}, {1, 1, 1}, {2, 3, 2}, {1, 0, 1}, {0, 0, 1}, {1, 1, 2}, {2,…
39 …TR_MODE {{1, 0, 0}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 1}, {3, 0, 1}, {1, 0, 1}, {2,…
44 … {{0, 0, 0}, {4, 2, 2}, {2, 1, 2}, {4, 1, 2}, {1, 0, 1}, {4, 0, 2}, {0, 0, 1}, {4, 2, 3}, {2,…
[all …]

12345678910>>...159