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/cmsis-dsp-latest/Testing/Patterns/DSP/SVM/SVMF32/
DReference5_s32.txt3 // -1
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DReference2_s32.txt3 // 1
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DReference1_s32.txt3 // 1
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/cmsis-dsp-latest/Testing/Patterns/DSP/SVM/SVMF16/
DReference5_s32.txt3 // -1
5 // -1
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DReference4_s32.txt5 // 1
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/cmsis-dsp-latest/Testing/Patterns/DSP/FastMath/FastMathQ15/
DDivisionShift1_s16.txt3 // 1
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/cmsis-dsp-latest/Testing/Patterns/DSP/FastMath/FastMathQ31/
DDivisionShift1_s16.txt3 // 1
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/cmsis-dsp-latest/Examples/ARM/arm_class_marks_example/
Darm_class_marks_example.uvoptx31 <gFlags>1</gFlags>
32 <BeepAtEnd>1</BeepAtEnd>
34 <RunTarget>1</RunTarget>
38 <HexSelection>1</HexSelection>
51 <CreateCListing>1</CreateCListing>
52 <CreateAListing>1</CreateAListing>
53 <CreateLListing>1</CreateLListing>
55 <AsmCond>1</AsmCond>
56 <AsmSymb>1</AsmSymb>
58 <CCond>1</CCond>
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/cmsis-dsp-latest/Examples/ARM/arm_svm_example/
Darm_svm_example.uvoptx31 <gFlags>1</gFlags>
32 <BeepAtEnd>1</BeepAtEnd>
34 <RunTarget>1</RunTarget>
38 <HexSelection>1</HexSelection>
51 <CreateCListing>1</CreateCListing>
52 <CreateAListing>1</CreateAListing>
53 <CreateLListing>1</CreateLListing>
55 <AsmCond>1</AsmCond>
56 <AsmSymb>1</AsmSymb>
58 <CCond>1</CCond>
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/cmsis-dsp-latest/Examples/ARM/arm_fir_example/
Darm_fir_example.uvoptx31 <gFlags>1</gFlags>
32 <BeepAtEnd>1</BeepAtEnd>
34 <RunTarget>1</RunTarget>
38 <HexSelection>1</HexSelection>
51 <CreateCListing>1</CreateCListing>
52 <CreateAListing>1</CreateAListing>
53 <CreateLListing>1</CreateLListing>
55 <AsmCond>1</AsmCond>
56 <AsmSymb>1</AsmSymb>
58 <CCond>1</CCond>
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/cmsis-dsp-latest/Examples/ARM/arm_graphic_equalizer_example/
Darm_graphic_equalizer_example.uvoptx31 <gFlags>1</gFlags>
32 <BeepAtEnd>1</BeepAtEnd>
34 <RunTarget>1</RunTarget>
38 <HexSelection>1</HexSelection>
51 <CreateCListing>1</CreateCListing>
52 <CreateAListing>1</CreateAListing>
53 <CreateLListing>1</CreateLListing>
55 <AsmCond>1</AsmCond>
56 <AsmSymb>1</AsmSymb>
58 <CCond>1</CCond>
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/cmsis-dsp-latest/Examples/ARM/arm_linear_interp_example/
Darm_linear_interp_example.uvoptx31 <gFlags>1</gFlags>
32 <BeepAtEnd>1</BeepAtEnd>
34 <RunTarget>1</RunTarget>
38 <HexSelection>1</HexSelection>
51 <CreateCListing>1</CreateCListing>
52 <CreateAListing>1</CreateAListing>
53 <CreateLListing>1</CreateLListing>
55 <AsmCond>1</AsmCond>
56 <AsmSymb>1</AsmSymb>
58 <CCond>1</CCond>
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/cmsis-dsp-latest/Examples/ARM/arm_fft_bin_example/
Darm_fft_bin_example.uvoptx31 <gFlags>1</gFlags>
32 <BeepAtEnd>1</BeepAtEnd>
34 <RunTarget>1</RunTarget>
38 <HexSelection>1</HexSelection>
51 <CreateCListing>1</CreateCListing>
52 <CreateAListing>1</CreateAListing>
53 <CreateLListing>1</CreateLListing>
55 <AsmCond>1</AsmCond>
56 <AsmSymb>1</AsmSymb>
58 <CCond>1</CCond>
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/cmsis-dsp-latest/Examples/ARM/arm_matrix_example/
Darm_matrix_example.uvoptx31 <gFlags>1</gFlags>
32 <BeepAtEnd>1</BeepAtEnd>
34 <RunTarget>1</RunTarget>
38 <HexSelection>1</HexSelection>
51 <CreateCListing>1</CreateCListing>
52 <CreateAListing>1</CreateAListing>
53 <CreateLListing>1</CreateLListing>
55 <AsmCond>1</AsmCond>
56 <AsmSymb>1</AsmSymb>
58 <CCond>1</CCond>
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/cmsis-dsp-latest/Examples/ARM/arm_signal_converge_example/
Darm_signal_converge_example.uvoptx31 <gFlags>1</gFlags>
32 <BeepAtEnd>1</BeepAtEnd>
34 <RunTarget>1</RunTarget>
38 <HexSelection>1</HexSelection>
51 <CreateCListing>1</CreateCListing>
52 <CreateAListing>1</CreateAListing>
53 <CreateLListing>1</CreateLListing>
55 <AsmCond>1</AsmCond>
56 <AsmSymb>1</AsmSymb>
58 <CCond>1</CCond>
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/cmsis-dsp-latest/Examples/ARM/arm_dotproduct_example/
Darm_dotproduct_example.uvoptx31 <gFlags>1</gFlags>
32 <BeepAtEnd>1</BeepAtEnd>
34 <RunTarget>1</RunTarget>
38 <HexSelection>1</HexSelection>
51 <CreateCListing>1</CreateCListing>
52 <CreateAListing>1</CreateAListing>
53 <CreateLListing>1</CreateLListing>
55 <AsmCond>1</AsmCond>
56 <AsmSymb>1</AsmSymb>
58 <CCond>1</CCond>
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/cmsis-dsp-latest/Examples/ARM/arm_variance_example/
Darm_variance_example.uvoptx31 <gFlags>1</gFlags>
32 <BeepAtEnd>1</BeepAtEnd>
34 <RunTarget>1</RunTarget>
38 <HexSelection>1</HexSelection>
51 <CreateCListing>1</CreateCListing>
52 <CreateAListing>1</CreateAListing>
53 <CreateLListing>1</CreateLListing>
55 <AsmCond>1</AsmCond>
56 <AsmSymb>1</AsmSymb>
58 <CCond>1</CCond>
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/cmsis-dsp-latest/Examples/ARM/arm_sin_cos_example/
Darm_sin_cos_example.uvoptx31 <gFlags>1</gFlags>
32 <BeepAtEnd>1</BeepAtEnd>
34 <RunTarget>1</RunTarget>
38 <HexSelection>1</HexSelection>
51 <CreateCListing>1</CreateCListing>
52 <CreateAListing>1</CreateAListing>
53 <CreateLListing>1</CreateLListing>
55 <AsmCond>1</AsmCond>
56 <AsmSymb>1</AsmSymb>
58 <CCond>1</CCond>
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/cmsis-dsp-latest/Examples/ARM/arm_convolution_example/
Darm_convolution_example.uvoptx31 <gFlags>1</gFlags>
32 <BeepAtEnd>1</BeepAtEnd>
34 <RunTarget>1</RunTarget>
38 <HexSelection>1</HexSelection>
51 <CreateCListing>1</CreateCListing>
52 <CreateAListing>1</CreateAListing>
53 <CreateLListing>1</CreateLListing>
55 <AsmCond>1</AsmCond>
56 <AsmSymb>1</AsmSymb>
58 <CCond>1</CCond>
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/cmsis-dsp-latest/Examples/ARM/arm_bayes_example/
Darm_bayes_example.uvoptx31 <gFlags>1</gFlags>
32 <BeepAtEnd>1</BeepAtEnd>
34 <RunTarget>1</RunTarget>
38 <HexSelection>1</HexSelection>
51 <CreateCListing>1</CreateCListing>
52 <CreateAListing>1</CreateAListing>
53 <CreateLListing>1</CreateLListing>
55 <AsmCond>1</AsmCond>
56 <AsmSymb>1</AsmSymb>
58 <CCond>1</CCond>
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/cmsis-dsp-latest/Testing/Patterns/DSP/FastMath/FastMathF16/
DDivisionShift1_s16.txt5 // 1
7 // 1
9 // 1
11 // 1
13 // 1
15 // 1
17 // 1
19 // 1
21 // 1
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/cmsis-dsp-latest/Testing/Patterns/DSP/FastMath/FastMathF32/
DDivisionShift1_s16.txt5 // 1
7 // 1
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/cmsis-dsp-latest/Testing/Patterns/DSP/FastMath/FastMathF64/
DDivisionShift1_s16.txt5 // 1
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/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM55/
Dpartition_ARMCM55.h3 * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline
35 #define SAU_INIT_CTRL 1
41 #define SAU_INIT_CTRL_ENABLE 1
46 // <1=> All Memory is Non-Secure
48 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
69 #define SAU_INIT_REGION0 1
84 // <1=>Secure, Non-Secure Callable
86 #define SAU_INIT_NSC0 1
92 // <e>Initialize SAU Region 1
93 // <i> Setup SAU Region 1 memory attributes
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/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM33/
Dpartition_ARMCM33.h35 #define SAU_INIT_CTRL 1
41 #define SAU_INIT_CTRL_ENABLE 1
46 // <1=> All Memory is Non-Secure
48 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
69 #define SAU_INIT_REGION0 1
84 // <1=>Secure, Non-Secure Callable
86 #define SAU_INIT_NSC0 1
92 // <e>Initialize SAU Region 1
93 // <i> Setup SAU Region 1 memory attributes
95 #define SAU_INIT_REGION1 1
[all …]

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