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/Zephyr-Core-3.6.0/tests/subsys/dsp/basicmath/src/
Dq15.pat2 0x0EB1, 0xD7DA, 0xDFC2, 0x2DDA, 0xAEB8, 0x1A8C, 0x34D0, 0xC949,
3 0x19FF, 0x1AFC, 0xD67E, 0x2639, 0x1546, 0xF32D, 0x2A82, 0xB79E,
4 0x1317, 0xEAF2, 0xCBD9, 0xC454, 0x42FD, 0xBB89, 0x9B4F, 0xCE5C,
5 0x09A1, 0xDFC2, 0xD780, 0x2B2C, 0x0FDB, 0xC69C, 0x5D9B, 0xBC82,
6 0x2794, 0xC287, 0x152B, 0xDA69, 0x2BE1, 0xE9BB, 0xD5EE, 0xC7C4,
7 0xBCDA, 0xC828, 0x19B1, 0x5F41, 0x5146, 0x00F0, 0xDEF6, 0x2A44,
8 0xCD0A, 0xE918, 0xF4D0, 0xD863, 0x241F, 0xE030, 0x26F3, 0x1ACB,
9 0x245C, 0x047C, 0x9433, 0x2BF5, 0x2F0F, 0x40E5, 0xC00D, 0x849C,
10 0x215D, 0xDE1B, 0x264A, 0x311D, 0x0C88, 0x1028, 0x2D8F, 0xCE0E,
11 0x1B43, 0x5529, 0x2914, 0xE215, 0x0C95, 0xF727, 0xDF21, 0xD12E,
[all …]
/Zephyr-Core-3.6.0/boards/arm/raytac_mdbt53_db_40_nrf5340/
Draytac_mdbt53_db_40_nrf5340_cpunet_common.dts40 boot_partition: partition@0 {
42 reg = <0x00000000 0xc000>;
45 label = "image-0";
46 reg = <0x0000C000 0x17000>;
50 reg = <0x00023000 0x17000>;
54 reg = <0x0003a000 0x6000>;
/Zephyr-Core-3.6.0/boards/arm/raytac_mdbt53v_db_40_nrf5340/
Draytac_mdbt53v_db_40_nrf5340_cpunet_common.dts40 boot_partition: partition@0 {
42 reg = <0x00000000 0xc000>;
45 label = "image-0";
46 reg = <0x0000C000 0x17000>;
50 reg = <0x00023000 0x17000>;
54 reg = <0x0003a000 0x6000>;
/Zephyr-Core-3.6.0/samples/subsys/usb/dfu/
DREADME.rst33 to be loaded at the offset of SLOT-0.
47 the USB DFU sample at the offset of SLOT-0.
65 Use the following command to backup the SLOT-0 image:
69 dfu-util --alt 0 --upload slot0_backup.bin
84 I: Primary image: magic=good, swap_type=0x3, copy_done=0x1, image_ok=0x1
85 I: Secondary image: magic=good, swap_type=0x2, copy_done=0x3, image_ok=0x3
88 I: Bootloader chainload address offset: 0xc000
101 I: Primary image: magic=good, swap_type=0x2, copy_done=0x1, image_ok=0x3
102 I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
105 I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
[all …]
/Zephyr-Core-3.6.0/tests/lib/cmsis_dsp/fastmath/src/
Dq15.pat2 0x0000, 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x6000, 0x7FFF,
3 0xF000, 0xE000, 0xD000, 0xC000, 0xB000, 0xA000, 0x8000, 0x0000,
4 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x6000, 0x7FFF
8 0xCCCD, 0x0000, 0x0CCD, 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF
12 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD,
13 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD,
14 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD,
15 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD,
16 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD,
17 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD,
[all …]
/Zephyr-Core-3.6.0/drivers/sensor/vl53l1x/
Dvl53l1_platform_user_config.h25 #define VL53L1_TUNINGPARM_PUBLIC_PAGE_BASE_ADDRESS 0x8000
26 #define VL53L1_TUNINGPARM_PRIVATE_PAGE_BASE_ADDRESS 0xC000
28 #define VL53L1_GAIN_FACTOR__STANDARD_DEFAULT 0x0800
30 * 1.11 format. 1.0 = 0x0800, 0.980 = 0x07D7
33 #define VL53L1_OFFSET_CAL_MIN_EFFECTIVE_SPADS 0x0500
35 * calibration Format 8.8 0x0500 -> 5.0 effective SPADs
38 #define VL53L1_OFFSET_CAL_MAX_PRE_PEAK_RATE_MCPS 0x1900
40 * calibration Format 9.7 0x1900 -> 50.0 Mcps.
44 #define VL53L1_OFFSET_CAL_MAX_SIGMA_MM 0x0040
47 * Format 14.2 0x0040 -> 16.0mm.
/Zephyr-Core-3.6.0/boards/arm/bl5340_dvk/
Dbl5340_dvk_cpunet_common.dtsi44 boot_partition: partition@0 {
46 reg = <0x00000000 0xc000>;
50 label = "image-0";
51 reg = <0x0000C000 0x16000>;
56 reg = <0x00022000 0x16000>;
61 reg = <0x00038000 0x8000>;
/Zephyr-Core-3.6.0/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/
DREADME.rst48 States of Servers are bounded as per Bluetooth SIG Mesh Model Specification v1.0
76 to publish to group 0xC000 and LED1 to subscribe to that group.
78 to publish to group 0xC000 and LED3 to subscribe to that group.
87 bind 0 1 1000
88 bind 0 1 1001
89 bind 0 1 1002
90 bind 0 1 1003
93 pub-set 0100 c000 1 0 5 1001
94 pub-set 0100 c000 1 0 5 1003
104 network 0x0.
[all …]
/Zephyr-Core-3.6.0/boards/arm/pan1781_evb/
Dpan1781_evb.dts43 pwms = <&sw_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
64 gpio-map-mask = <0xffffffff 0xffffffc0>;
65 gpio-map-pass-thru = <0 0x3f>;
66 gpio-map = <0 0 &gpio0 2 0>, /* A0 */
67 <1 0 &gpio0 3 0>, /* A1 */
68 <2 0 &gpio0 4 0>, /* A2 */
69 <3 0 &gpio0 5 0>, /* A3 */
70 <6 0 &gpio0 6 0>, /* D0 */
71 <7 0 &gpio0 8 0>, /* D1 */
72 <8 0 &gpio0 14 0>, /* D2 */
[all …]
/Zephyr-Core-3.6.0/boards/arm/nrf5340_audio_dk_nrf5340/
Dnrf5340_audio_dk_nrf5340_cpunet.dts44 pinctrl-0 = <&uart0_default>;
56 boot_partition: partition@0 {
58 reg = <0x00000000 0xc000>;
61 label = "image-0";
62 reg = <0x0000C000 0x12000>;
66 reg = <0x0001E000 0x12000>;
70 reg = <0x0003a000 0x6000>;
/Zephyr-Core-3.6.0/boards/arm/raytac_mdbt50q_db_33_nrf52833/
Draytac_mdbt50q_db_33_nrf52833.dts32 label = "Green LED 0";
47 pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
55 label = "Push button switch 0";
116 pinctrl-0 = <&uart0_default>;
125 pinctrl-0 = <&uart1_default>;
133 pinctrl-0 = <&i2c0_default>;
142 pinctrl-0 = <&i2c1_default>;
149 pinctrl-0 = <&pwm0_default>;
158 pinctrl-0 = <&spi0_default>;
166 pinctrl-0 = <&spi1_default>;
[all …]
/Zephyr-Core-3.6.0/boards/arm/acn52832/
Dacn52832.dts64 pinctrl-0 = <&uart0_default>;
75 boot_partition: partition@0 {
77 reg = <0x00000000 0xc000>;
80 label = "image-0";
81 reg = <0x0000c000 0x37000>;
85 reg = <0x00043000 0x37000>;
89 reg = <0x0007a000 0x00006000>;
/Zephyr-Core-3.6.0/subsys/net/l2/ppp/
Dnetwork.c21 if (ctx->network_protos_up == 0) { in ppp_network_up()
27 NET_DBG("[%p] Proto %s (0x%04x) %s (%d)", ctx, ppp_proto2str(proto), in ppp_network_up()
35 if (ctx->network_protos_up <= 0) { in ppp_network_down()
36 ctx->network_protos_up = 0; in ppp_network_down()
40 NET_DBG("[%p] Proto %s (0x%04x) %s (%d)", ctx, ppp_proto2str(proto), in ppp_network_down()
47 if (ctx->network_protos_up <= 0) { in ppp_network_done()
63 if (proto->protocol < 0xC000 && proto->close) { in ppp_network_all_down()
69 if (ctx->network_protos_open > 0) { in ppp_network_all_down()
74 ctx->network_protos_open = 0; in ppp_network_all_down()
Dlink.c51 proto->protocol >= 0xC000) { in do_network()
61 if (ctx->network_protos_open == 0) { in do_network()
72 uint16_t auth_proto = 0; in do_auth()
/Zephyr-Core-3.6.0/samples/application_development/sysbuild/with_mcuboot/
DREADME.rst47 Address of sample 0xc000
/Zephyr-Core-3.6.0/boards/arm/nrf52_sparkfun/
Dnrf52_sparkfun.dts69 pinctrl-0 = <&uart0_default>;
81 boot_partition: partition@0 {
83 reg = <0x00000000 0xc000>;
86 label = "image-0";
87 reg = <0x0000c000 0x32000>;
91 reg = <0x0003e000 0x32000>;
95 reg = <0x00070000 0xa000>;
99 reg = <0x0007a000 0x00006000>;
/Zephyr-Core-3.6.0/dts/bindings/mtd/
Dfixed-partitions.yaml13 boot_partition: partition@0 {
15 reg = <0x00000000 0x0000C000>;
18 label = "image-0";
19 reg = <0x0000C000 0x00076000>;
23 reg = <0x00082000 0x00076000>;
27 * The flash starting at 0x000f8000 and ending at
28 * 0x000fffff is reserved for use by the application.
37 reg = <0x000f8000 0x00008000>;
48 Above, slot0_partition's register address 0xc000 means that
80 reg = <0xSTART_OFFSET 0xSIZE>;
/Zephyr-Core-3.6.0/soc/arm/arm/beetle/
Dsoc.h33 #define _BEETLE_GPIO0 (1 << 0)
39 #define _BEETLE_TIMER0 (1 << 0)
57 #define _BEETLE_APB_BASE 0x40000000
58 #define _BEETLE_APB_PER_SIZE 0x1000
59 #define _BEETLE_APB_FULL_SIZE 0x10000
60 #define _BEETLE_AHB_BASE 0x40010000
61 #define _BEETLE_AHB_PER_SIZE 0x1000
62 #define _BEETLE_AHB_FULL_SIZE 0x10000
65 #define _BEETLE_GPIO0_BASE (_BEETLE_AHB_BASE + 0x0000)
66 #define _BEETLE_GPIO1_BASE (_BEETLE_AHB_BASE + 0x1000)
[all …]
/Zephyr-Core-3.6.0/boards/arm/nrf52_adafruit_feather/
Dnrf52_adafruit_feather.dts44 gpios = <&gpio0 17 0>;
48 gpios = <&gpio0 19 0>;
56 pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
89 pinctrl-0 = <&uart0_default>;
96 pinctrl-0 = <&i2c0_default>;
108 boot_partition: partition@0 {
110 reg = <0x00000000 0xc000>;
113 label = "image-0";
114 reg = <0x0000C000 0x32000>;
118 reg = <0x0003E000 0x32000>;
[all …]
/Zephyr-Core-3.6.0/boards/arm/we_ophelia1ev_nrf52805/
Dwe_ophelia1ev_nrf52805.dts30 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
31 label = "LED 0";
79 pinctrl-0 = <&i2c0_default>;
87 pinctrl-0 = <&spi0_default>;
96 pinctrl-0 = <&uart0_default>;
107 boot_partition: partition@0 {
109 reg = <0x00000000 0xc000>;
112 label = "image-0";
113 reg = <0x0000C000 0xd000>;
117 reg = <0x00019000 0xd000>;
[all …]
/Zephyr-Core-3.6.0/boards/arm/we_proteus2ev_nrf52832/
Dwe_proteus2ev_nrf52832.dts27 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
28 label = "LED 0";
75 pinctrl-0 = <&uart0_default>;
84 pinctrl-0 = <&i2c0_default>;
93 pinctrl-0 = <&spi0_default>;
104 boot_partition: partition@0 {
106 reg = <0x00000000 0xc000>;
109 label = "image-0";
110 reg = <0x0000C000 0x32000>;
114 reg = <0x0003E000 0x32000>;
[all …]
/Zephyr-Core-3.6.0/boards/arm/ebyte_e73_tbb_nrf52832/
Debyte_e73_tbb_nrf52832.dts44 pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
94 pinctrl-0 = <&uart0_default>;
101 pinctrl-0 = <&pwm0_default>;
113 boot_partition: partition@0 {
115 reg = <0x00000000 0xc000>;
118 label = "image-0";
119 reg = <0x0000C000 0x32000>;
123 reg = <0x0003E000 0x32000>;
127 reg = <0x00070000 0xa000>;
131 reg = <0x0007a000 0x00006000>;
/Zephyr-Core-3.6.0/subsys/fs/ext2/
Dext2.h11 #define EXT2_MAGIC_NUMBER 0xEF53
17 #define EXT2_FEATURE_INCOMPAT_COMPRESSION 0x0001 /* Disk/File compression is used */
18 #define EXT2_FEATURE_INCOMPAT_FILETYPE 0x0002 /* Directory entries record the file type */
19 #define EXT3_FEATURE_INCOMPAT_RECOVER 0x0004 /* Filesystem needs recovery */
20 #define EXT3_FEATURE_INCOMPAT_JOURNAL_DEV 0x0008 /* Filesystem has a separate journal device */
21 #define EXT2_FEATURE_INCOMPAT_META_BG 0x0010 /* Meta block groups */
25 #define EXT2_FEATURE_RO_COMPAT_SPARSE_SUPER 0x0001 /* Sparse Superblock */
26 #define EXT2_FEATURE_RO_COMPAT_LARGE_FILE 0x0002 /* Large file support, 64-bit file size */
27 #define EXT2_FEATURE_RO_COMPAT_BTREE_DIR 0x0004 /* Binary tree sorted directory files */
29 #define EXT2_FEATURE_RO_COMPAT_SUPPORTED (0)
[all …]
/Zephyr-Core-3.6.0/boards/arm/blueclover_plt_demo_v2_nrf52832/
Dblueclover_plt_demo_v2_nrf52832.dts31 label = "Push button switch 0";
67 pinctrl-0 = <&uart0_default>;
76 pinctrl-0 = <&i2c0_default>;
81 reg = <0x44>;
86 reg = <0x68>;
93 pinctrl-0 = <&pwm0_default>;
102 pinctrl-0 = <&spi1_default>;
105 apa102@0 {
107 reg = <0>;
118 boot_partition: partition@0 {
[all …]
/Zephyr-Core-3.6.0/boards/arm/ruuvi_ruuvitag/
Druuvi_ruuvitag.dts40 label = "Red LED 0";
52 label = "Push button switch 0";
74 pinctrl-0 = <&uart0_default>;
84 pinctrl-0 = <&spi0_default>;
87 bme280@0 {
89 reg = <0>;
109 boot_partition: partition@0 {
111 reg = <0x00000000 0xc000>;
114 label = "image-0";
115 reg = <0x0000C000 0x32000>;
[all …]

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