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/Zephyr-Core-3.5.0/boards/riscv/rv32m1_vega/support/
Dopenocd_rv32m1_vega_ri5cy.cfg4 set _WORKAREASIZE 0x2000
11 set _WORKAREASIZE 0x1000
18 set _CPUTAPID 0x249511C3
38 # Select core 0
39 core_select 0
41 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
46 flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
47 flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1
52 mwb 0x40023000 0x70
53 mww 0x40023004 0x49000000
[all …]
Dopenocd_rv32m1_vega_zero_riscy.cfg4 set _WORKAREASIZE 0x2000
11 set _WORKAREASIZE 0x1000
18 set _CPUTAPID 0x249511C3
41 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
46 flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
47 flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1
52 mwb 0x40023000 0x70
53 mww 0x40023004 0x49000000
54 mwb 0x40023000 0x80
58 mwb 0x40023000 0x70
[all …]
/Zephyr-Core-3.5.0/tests/net/lib/dns_packet/src/
Dmain.c27 * Transaction ID: 0xda0f
30 static uint8_t query_ipv4[] = { 0xda, 0x0f, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00,
31 0x00, 0x00, 0x00, 0x00, 0x03, 0x77, 0x77, 0x77,
32 0x0d, 0x7a, 0x65, 0x70, 0x68, 0x79, 0x72, 0x70,
33 0x72, 0x6f, 0x6a, 0x65, 0x63, 0x74, 0x03, 0x6f,
34 0x72, 0x67, 0x00, 0x00, 0x01, 0x00, 0x01 };
43 0xda, 0x0f, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00,
44 0x00, 0x00, 0x00, 0x00, 0x06, 0x7a, 0x65, 0x70,
45 0x68, 0x79, 0x72, 0x05, 0x6c, 0x6f, 0x63, 0x61,
46 0x6c, 0x00, 0x00, 0x01, 0x00, 0x01,
[all …]
/Zephyr-Core-3.5.0/drivers/led/
Dncp5623.c25 #define NCP5623_LED_CURRENT 0x20
26 #define NCP5623_LED_PWM0 0x40
27 #define NCP5623_LED_PWM1 0x60
28 #define NCP5623_LED_PWM2 0x80
33 #define NCP5623_MIN_BRIGHTNESS 0
34 #define NCP5623_MAX_BRIGHTNESS 0x1f
64 return 0; in ncp5623_get_info()
72 uint8_t buf[6] = {0x70, NCP5623_LED_PWM0, 0x70, NCP5623_LED_PWM1, 0x70, NCP5623_LED_PWM2}; in ncp5623_set_color()
85 buf[1] = buf[1] | color[0] / 8; in ncp5623_set_color()
97 int ret = 0; in ncp5623_set_brightness()
[all …]
/Zephyr-Core-3.5.0/tests/subsys/mgmt/mcumgr/os_mgmt_echo/src/
Dmain.c17 0x02, 0x00, 0x00, 0x2e, 0x00, 0x00, 0x01, 0x00,
18 0xbf, 0x61, 0x64, 0x78, 0x28, 0x73, 0x68, 0x6f,
19 0x72, 0x74, 0x20, 0x4d, 0x43, 0x55, 0x4d, 0x47,
20 0x52, 0x20, 0x74, 0x65, 0x73, 0x74, 0x20, 0x61,
21 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69,
22 0x6f, 0x6e, 0x20, 0x6d, 0x65, 0x73, 0x73, 0x61,
23 0x67, 0x65, 0x2e, 0x2e, 0x2e, 0xff,
28 0x03, 0x00, 0x00, 0x2e, 0x00, 0x00, 0x01, 0x00,
29 0xbf, 0x61, 0x72, 0x78, 0x28, 0x73, 0x68, 0x6f,
30 0x72, 0x74, 0x20, 0x4d, 0x43, 0x55, 0x4d, 0x47,
[all …]
/Zephyr-Core-3.5.0/subsys/fb/
Dcfb_fonts.c20 0x00, 0x00,
21 0x00, 0x00,
22 0x00, 0x00,
23 0x00, 0x00,
24 0x00, 0x00,
25 0x00, 0x00,
26 0x00, 0x00,
27 0x00, 0x00,
28 0x00, 0x00,
29 0x00, 0x00,
[all …]
/Zephyr-Core-3.5.0/dts/arm/nxp/
Dnxp_rt1010.dtsi14 reg = <0x00000000 DT_SIZE_K(32)>;
18 reg = <0x20000000 DT_SIZE_K(32)>;
22 reg = <0x20200000 DT_SIZE_K(64)>;
34 interrupts = <70 0>, <71 0>;
38 interrupts = <73 0>;
42 interrupts = <30 0>;
46 interrupts = <31 0>;
69 reg = <0x42000000 0x4000>;
70 interrupts = <72 0>;
99 reg = <0x400a0000 0x4000>;
[all …]
Dnxp_rt10xx.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
36 reg = <0xe000ed90 0x40>;
42 reg = <0xe0000000 0x1000>;
66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #clock-cells = <0>;
85 #clock-cells = <0>;
91 reg = <0x400b0000 0x4000>;
[all …]
/Zephyr-Core-3.5.0/samples/boards/mec172xevb_assy6906/rom_api/src/
Dmain.c27 0x45, 0x73, 0x66, 0x72, 0x44, 0x36, 0x70, 0x73,
28 0x47, 0x7a, 0x66, 0x70, 0x78, 0x56, 0x78, 0x6b,
29 0x70, 0x65, 0x4a, 0x56, 0x55, 0x4a, 0x58, 0x62,
30 0x41, 0x61, 0x53, 0x33, 0x6e, 0x55, 0x78, 0x41,
31 0x46, 0x6d, 0x34, 0x77, 0x42,
34 0xe4, 0x70, 0xa9, 0x89, 0xc5, 0x37, 0xda, 0x0d,
35 0x9f, 0x55, 0x9a, 0x4e, 0x9d, 0xed, 0xaa, 0x75,
36 0xf8, 0xe0, 0x58, 0x0f, 0xc4, 0x2e, 0x0d, 0x23,
37 0x03, 0x7c, 0x0f, 0x18,
40 0xe2, 0x82, 0x23, 0xfb, 0x3f, 0x6a, 0x49, 0x17,
[all …]
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/reset/
Dstm32wba_reset.h13 #define STM32_RESET_BUS_AHB1 0x60
14 #define STM32_RESET_BUS_AHB2 0x64
15 #define STM32_RESET_BUS_AHB4 0x6C
16 #define STM32_RESET_BUS_AHB5 0x70
17 #define STM32_RESET_BUS_APB1L 0x74
18 #define STM32_RESET_BUS_APB1H 0x78
19 #define STM32_RESET_BUS_APB2 0x7C
20 #define STM32_RESET_BUS_APB7 0x80
/Zephyr-Core-3.5.0/tests/kernel/fpu_sharing/generic/src/
Dfloat_regs_sparc.h16 "ldd [%0 + 0x00], %%f0\n" in _load_all_float_registers()
17 "ldd [%0 + 0x08], %%f2\n" in _load_all_float_registers()
18 "ldd [%0 + 0x10], %%f4\n" in _load_all_float_registers()
19 "ldd [%0 + 0x18], %%f6\n" in _load_all_float_registers()
20 "ldd [%0 + 0x20], %%f8\n" in _load_all_float_registers()
21 "ldd [%0 + 0x28], %%f10\n" in _load_all_float_registers()
22 "ldd [%0 + 0x30], %%f12\n" in _load_all_float_registers()
23 "ldd [%0 + 0x38], %%f14\n" in _load_all_float_registers()
24 "ldd [%0 + 0x40], %%f16\n" in _load_all_float_registers()
25 "ldd [%0 + 0x48], %%f18\n" in _load_all_float_registers()
[all …]
/Zephyr-Core-3.5.0/samples/drivers/led_ws2812/
Dnrf52-bindings.h17 #define ZERO_FRAME 0x40
18 #define ONE_FRAME 0x70
/Zephyr-Core-3.5.0/samples/drivers/ht16k33/boards/
Dnrf52840dk_nrf52840.overlay12 reg = <0x70>;
/Zephyr-Core-3.5.0/samples/drivers/led_ws2812/boards/
Dnucleo_g071rb.overlay10 led_strip: ws2812@0 {
14 reg = <0>; /* ignored, but necessary for SPI bindings */
20 spi-one-frame = <0x70>;
21 spi-zero-frame = <0x40>;
Dnucleo_h743zi.overlay10 led_strip: ws2812@0 {
14 reg = <0>; /* ignored, but necessary for SPI bindings */
20 spi-one-frame = <0x70>;
21 spi-zero-frame = <0x40>;
Dnucleo_l476rg.overlay10 led_strip: ws2812@0 {
14 reg = <0>; /* ignored, but necessary for SPI bindings */
20 spi-one-frame = <0x70>;
21 spi-zero-frame = <0x40>;
/Zephyr-Core-3.5.0/tests/net/lib/dns_sd/src/
Dmain.c21 0 \
22 | ((a & 0xff) << 24) \
23 | ((b & 0xff) << 16) \
24 | ((c & 0xff) << 8) \
25 | ((d & 0xff) << 0) \
91 uint16_t offs = 0; in create_query()
95 uint16_t expected_req_buf_size = 0 in create_query()
101 (struct dns_header *)&create_query_buf[0]; in create_query()
103 hdr->id = htons(0); in create_query()
122 create_query_buf[offs++] = '\0'; in create_query()
[all …]
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/sensor/
Dit8xxx2_vcmp.h14 #define VCMP_CHANNEL_0 0
29 #define IT8XXX2_VCMP_SCAN_PERIOD_100US 0x10
30 #define IT8XXX2_VCMP_SCAN_PERIOD_200US 0x20
31 #define IT8XXX2_VCMP_SCAN_PERIOD_400US 0x30
32 #define IT8XXX2_VCMP_SCAN_PERIOD_600US 0x40
33 #define IT8XXX2_VCMP_SCAN_PERIOD_800US 0x50
34 #define IT8XXX2_VCMP_SCAN_PERIOD_1MS 0x60
35 #define IT8XXX2_VCMP_SCAN_PERIOD_1_5MS 0x70
36 #define IT8XXX2_VCMP_SCAN_PERIOD_2MS 0x80
37 #define IT8XXX2_VCMP_SCAN_PERIOD_2_5MS 0x90
[all …]
/Zephyr-Core-3.5.0/boards/arc/nsim/support/
Dnsim_hs6x.props1 maxlastpc=0
2 trace_enabled=0
4 nsim_isa_core=0
5 arcver=0x70
7 nsim_isa_uarch_rev_major=0
8 nsim_isa_uarch_rev_minor=0
12 nsim_isa_big_endian=0
18 nsim_isa_shift_option=0
20 nsim_isa_timer_0_int_level=0
22 nsim_isa_timer_1_int_level=0
[all …]
/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_dw_registers.h15 #define SWPORTA_DR 0x00
16 #define SWPORTA_DDR 0x04
17 #define SWPORTA_CTL 0x08
18 #define SWPORTB_DR 0x0c
19 #define SWPORTB_DDR 0x10
20 #define SWPORTB_CTL 0x14
21 #define SWPORTC_DR 0x18
22 #define SWPORTC_DDR 0x1c
23 #define SWPORTC_CTL 0x20
24 #define SWPORTD_DR 0x24
[all …]
/Zephyr-Core-3.5.0/drivers/flash/
Dflash_cadence_qspi_nor_ll.h17 #define CAD_QSPI_ADDR_FASTREAD 0
20 #define CAT_QSPI_ADDR_SINGLE_IO 0
27 #define CAD_QSPI_COMMAND_TIMEOUT 0x10000000
29 #define CAD_QSPI_CFG 0x0
30 #define CAD_QSPI_CFG_BAUDDIV_MSK 0xff87ffff
31 #define CAD_QSPI_CFG_BAUDDIV(x) FIELD_PREP(0x780000, x)
32 #define CAD_QSPI_CFG_CS_MSK ~0x3c00
34 #define CAD_QSPI_CFG_ENABLE (BIT(0))
35 #define CAD_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff
37 #define CAD_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb
[all …]
/Zephyr-Core-3.5.0/soc/arm64/intel_socfpga/common/
Dsocfpga_system_manager.h11 #define SOCFPGA_SYSMGR_REG_BASE 0xffd12000
13 #define SOCFPGA_SYSMGR_SDMMC 0x28
15 #define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6c
17 #define SOCFPGA_SYSMGR_EMAC_0 0x44
18 #define SOCFPGA_SYSMGR_EMAC_1 0x48
19 #define SOCFPGA_SYSMGR_EMAC_2 0x4c
20 #define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70
22 #define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0
23 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4
24 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8
[all …]
/Zephyr-Core-3.5.0/tests/subsys/canbus/isotp/conformance/src/
Drandom_data.h8 0xdc, 0x70, 0xfa, 0x96, 0xbb, 0x71, 0x49, 0x06, 0x18, 0x75, 0x84, 0xaf,
9 0xe3, 0xd4, 0x60, 0x11, 0xf8, 0xf8, 0xfa, 0xc7, 0x67, 0xae, 0xa4, 0x36,
10 0x08, 0xe5, 0x76, 0xa6, 0x50, 0x98, 0x2e, 0xc1, 0x4f, 0x91, 0x90, 0x92,
11 0xbf, 0xfa, 0x5a, 0xce, 0x6d, 0xeb, 0x2e, 0x5c, 0x77, 0x6b, 0x90, 0xfc,
12 0x50, 0xd7, 0x69, 0x04, 0x4b, 0x1d, 0xb3, 0x54, 0x55, 0xba, 0x0f, 0x75,
13 0xf5, 0x3b, 0x0c, 0x76, 0xc8, 0x31, 0x7d, 0x9a, 0xb5, 0xcd, 0x4f, 0x70,
14 0x47, 0xa0, 0xe3, 0xe5, 0x68, 0x59, 0xfb, 0x1e, 0x20, 0x4a, 0x9c, 0x90,
15 0xb6, 0xe7, 0x45, 0x83, 0x8d, 0x71, 0xd7, 0x27, 0xac, 0xef, 0xa3, 0xb9,
16 0x39, 0xda, 0x30, 0xac, 0xc3, 0x3a, 0x1c, 0x7c, 0x29, 0x2f, 0xc6, 0xa0,
17 0xbc, 0xe1, 0x1d, 0xab, 0x0f, 0x16, 0x30, 0xa4, 0x3c, 0x5d, 0x10, 0x45,
[all …]
/Zephyr-Core-3.5.0/tests/bluetooth/bt_crypto/src/
Dtest_bt_crypto.c17 static const uint8_t key[] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, in ZTEST()
18 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c}; in ZTEST()
20 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, in ZTEST()
21 0x93, 0x17, 0x2a, 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, 0x9e, 0xb7, in ZTEST()
22 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51, 0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, in ZTEST()
23 0x11, 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef, 0xf6, 0x9f, 0x24, 0x45, in ZTEST()
24 0xdf, 0x4f, 0x9b, 0x17, 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10}; in ZTEST()
26 uint8_t exp_mac1[] = {0xbb, 0x1d, 0x69, 0x29, 0xe9, 0x59, 0x37, 0x28, in ZTEST()
27 0x7f, 0xa3, 0x7d, 0x12, 0x9b, 0x75, 0x67, 0x46}; in ZTEST()
28 uint8_t exp_mac2[] = {0x07, 0x0a, 0x16, 0xb4, 0x6b, 0x4d, 0x41, 0x44, in ZTEST()
[all …]
/Zephyr-Core-3.5.0/samples/drivers/ht16k33/
DREADME.rst18 3. reduce the brightness gradually from 100% to 0%
27 connect an HT16K33 LED driver at address 0x70 on the I2C-0 bus.

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