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/Zephyr-latest/tests/lib/cmsis_dsp/filtering/src/
Dmisc_q7.pat2 0xF3, 0xAE, 0x42, 0x21, 0x19, 0xE2, 0x32, 0x15,
3 0xF9, 0xC4, 0xB6, 0xE3, 0xE1, 0x49, 0x2F, 0x1A,
4 0xF9, 0xE0, 0x28, 0xEA, 0xF1, 0x41, 0x7F, 0x32,
5 0xD5, 0x04, 0xBF, 0x0B, 0xD0, 0xBC, 0x16, 0x20,
6 0xBD, 0x08, 0xD8, 0xF4, 0x2E, 0x13, 0xFB, 0xC4,
7 0x26, 0xF2, 0x05, 0x0E, 0xA9, 0x09, 0xDE, 0x42,
8 0x30, 0xFC, 0x16, 0xDB, 0x17, 0xD8, 0x02, 0x2C,
9 0xFD, 0x05, 0xEF, 0x02, 0x13, 0xDA, 0x03, 0x2D,
10 0x24, 0x0D, 0x0D, 0xE8, 0xF4, 0xB5, 0xF6, 0xB6,
11 0x1C, 0xDE, 0x09, 0x03, 0xF0, 0xCD, 0x0B, 0xB0,
[all …]
/Zephyr-latest/boards/shields/p3t1755dp_ard_i3c/
Dp3t1755dp_ard_i3c.overlay17 reg = <0x48 0x0236 0x152a0090>;
/Zephyr-latest/tests/kernel/fpu_sharing/generic/src/
Dfloat_regs_sparc.h16 "ldd [%0 + 0x00], %%f0\n" in _load_all_float_registers()
17 "ldd [%0 + 0x08], %%f2\n" in _load_all_float_registers()
18 "ldd [%0 + 0x10], %%f4\n" in _load_all_float_registers()
19 "ldd [%0 + 0x18], %%f6\n" in _load_all_float_registers()
20 "ldd [%0 + 0x20], %%f8\n" in _load_all_float_registers()
21 "ldd [%0 + 0x28], %%f10\n" in _load_all_float_registers()
22 "ldd [%0 + 0x30], %%f12\n" in _load_all_float_registers()
23 "ldd [%0 + 0x38], %%f14\n" in _load_all_float_registers()
24 "ldd [%0 + 0x40], %%f16\n" in _load_all_float_registers()
25 "ldd [%0 + 0x48], %%f18\n" in _load_all_float_registers()
[all …]
/Zephyr-latest/drivers/sensor/asahi_kasei/ak8975/
Dak8975.h12 #define AK8975_REG_CHIP_ID 0x00
13 #define AK8975_CHIP_ID 0x48
15 #define AK8975_REG_DATA_START 0x03
17 #define AK8975_REG_CNTL 0x0A
18 #define AK8975_MODE_MEASURE 0x01
19 #define AK8975_MODE_FUSE_ACCESS 0x0F
21 #define AK8975_REG_ADJ_DATA_START 0x10
/Zephyr-latest/samples/sensor/adt7420/boards/
Dfrdm_k64f.overlay12 reg = <0x48>;
Dnrf52dk_nrf52832.overlay12 reg = <0x48>;
/Zephyr-latest/boards/shields/p3t1755dp_ard_i2c/
Dp3t1755dp_ard_i2c.overlay17 reg = <0x48>;
/Zephyr-latest/samples/sensor/thermometer/boards/
Dfrdm_mcxn947_mcxn947_cpu0.overlay24 reg = <0x48 0x0236 0x152a0090>;
Dfrdm_mcxn947_mcxn947_cpu0_qspi.overlay24 reg = <0x48 0x0236 0x152a0090>;
Dfrdm_k22f.overlay19 reg = <0x48>;
Dnucleo_h7a3zi_q.overlay18 pinctrl-0 = <&i2c1_sda_pb7 &i2c1_scl_pb6>;
25 reg = <0x48>;
/Zephyr-latest/boards/shields/dvp_fpc24_mt9m114/
Ddvp_fpc24_mt9m114.overlay16 reg = <0x48>;
/Zephyr-latest/samples/net/mqtt_publisher/src/
Dtest_certs.h31 0x30, 0x82, 0x02, 0xfb, 0x30, 0x82, 0x01, 0xe3,
32 0xa0, 0x03, 0x02, 0x01, 0x02, 0x02, 0x09, 0x00,
33 0xee, 0x10, 0x1f, 0xc1, 0xf2, 0x30, 0xe9, 0x11,
34 0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86,
35 0xf7, 0x0d, 0x01, 0x01, 0x0b, 0x05, 0x00, 0x30,
36 0x14, 0x31, 0x12, 0x30, 0x10, 0x06, 0x03, 0x55,
37 0x04, 0x03, 0x0c, 0x09, 0x6c, 0x6f, 0x63, 0x61,
38 0x6c, 0x68, 0x6f, 0x73, 0x74, 0x30, 0x1e, 0x17,
39 0x0d, 0x31, 0x37, 0x30, 0x36, 0x32, 0x36, 0x31,
40 0x30, 0x35, 0x36, 0x31, 0x30, 0x5a, 0x17, 0x0d,
[all …]
/Zephyr-latest/soc/renesas/ra/ra2a1/
Dsections.ld22 . = __OPTION_SETTING_OFS_Start + 0x04;
24 . = __OPTION_SETTING_OFS_Start + 0x10;
27 } GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
38 } GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
48 . = __OPTION_SETTING_NS_Start + 0x04;
50 . = __OPTION_SETTING_NS_Start + 0x10;
52 . = __OPTION_SETTING_NS_Start + 0x40;
54 . = __OPTION_SETTING_NS_Start + 0x44;
56 . = __OPTION_SETTING_NS_Start + 0x48;
58 . = __OPTION_SETTING_NS_Start + 0x4C;
[all …]
/Zephyr-latest/soc/renesas/ra/ra4m1/
Dsections.ld22 . = __OPTION_SETTING_OFS_Start + 0x04;
24 . = __OPTION_SETTING_OFS_Start + 0x10;
27 } GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
38 } GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
48 . = __OPTION_SETTING_NS_Start + 0x04;
50 . = __OPTION_SETTING_NS_Start + 0x10;
52 . = __OPTION_SETTING_NS_Start + 0x40;
54 . = __OPTION_SETTING_NS_Start + 0x44;
56 . = __OPTION_SETTING_NS_Start + 0x48;
58 . = __OPTION_SETTING_NS_Start + 0x4C;
[all …]
/Zephyr-latest/tests/subsys/canbus/isotp/conformance/src/
Drandom_data.h8 0xdc, 0x70, 0xfa, 0x96, 0xbb, 0x71, 0x49, 0x06, 0x18, 0x75, 0x84, 0xaf,
9 0xe3, 0xd4, 0x60, 0x11, 0xf8, 0xf8, 0xfa, 0xc7, 0x67, 0xae, 0xa4, 0x36,
10 0x08, 0xe5, 0x76, 0xa6, 0x50, 0x98, 0x2e, 0xc1, 0x4f, 0x91, 0x90, 0x92,
11 0xbf, 0xfa, 0x5a, 0xce, 0x6d, 0xeb, 0x2e, 0x5c, 0x77, 0x6b, 0x90, 0xfc,
12 0x50, 0xd7, 0x69, 0x04, 0x4b, 0x1d, 0xb3, 0x54, 0x55, 0xba, 0x0f, 0x75,
13 0xf5, 0x3b, 0x0c, 0x76, 0xc8, 0x31, 0x7d, 0x9a, 0xb5, 0xcd, 0x4f, 0x70,
14 0x47, 0xa0, 0xe3, 0xe5, 0x68, 0x59, 0xfb, 0x1e, 0x20, 0x4a, 0x9c, 0x90,
15 0xb6, 0xe7, 0x45, 0x83, 0x8d, 0x71, 0xd7, 0x27, 0xac, 0xef, 0xa3, 0xb9,
16 0x39, 0xda, 0x30, 0xac, 0xc3, 0x3a, 0x1c, 0x7c, 0x29, 0x2f, 0xc6, 0xa0,
17 0xbc, 0xe1, 0x1d, 0xab, 0x0f, 0x16, 0x30, 0xa4, 0x3c, 0x5d, 0x10, 0x45,
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_dw_registers.h15 #define SWPORTA_DR 0x00
16 #define SWPORTA_DDR 0x04
17 #define SWPORTA_CTL 0x08
18 #define SWPORTB_DR 0x0c
19 #define SWPORTB_DDR 0x10
20 #define SWPORTB_CTL 0x14
21 #define SWPORTC_DR 0x18
22 #define SWPORTC_DDR 0x1c
23 #define SWPORTC_CTL 0x20
24 #define SWPORTD_DR 0x24
[all …]
/Zephyr-latest/drivers/sensor/asahi_kasei/akm09918c/
Dakm09918c_reg.h11 #define AKM09918C_REG_WIA1 0x00
12 #define AKM09918C_REG_WIA2 0x01
13 #define AKM09918C_REG_RSV1 0x02
14 #define AKM09918C_REG_RSV2 0x03
15 #define AKM09918C_REG_ST1 0x10
16 #define AKM09918C_REG_HXL 0x11
17 #define AKM09918C_REG_HXH 0x12
18 #define AKM09918C_REG_HYL 0x13
19 #define AKM09918C_REG_HYH 0x14
20 #define AKM09918C_REG_HZL 0x15
[all …]
/Zephyr-latest/soc/intel/intel_socfpga/common/
Dsocfpga_system_manager.h13 #define SOCFPGA_SYSMGR_SDMMC 0x28
15 #define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6c
17 #define SOCFPGA_SYSMGR_EMAC_0 0x44
18 #define SOCFPGA_SYSMGR_EMAC_1 0x48
19 #define SOCFPGA_SYSMGR_EMAC_2 0x4c
20 #define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70
22 #define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0
23 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4
24 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8
25 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xcc
[all …]
/Zephyr-latest/dts/bindings/display/
Dilitek,ili9488.yaml13 default: [0xb0, 0x11]
19 default: [0x02, 0x02, 0x3b]
22 default SS bit value (0) may interfere with display rotation.
26 default: [0x0e, 0x0e]
32 default: [0x43]
38 default: [0x00, 0x40, 0x00, 0x40]
45 0x0f,
46 0x1f,
47 0x1c,
48 0x0b,
[all …]
/Zephyr-latest/drivers/sensor/meas/ms5837/
Dms5837.h14 #define MS5837_CMD_RESET 0x1E
16 #define MS5837_CMD_CONV_P_256 0x40
17 #define MS5837_CMD_CONV_P_512 0x42
18 #define MS5837_CMD_CONV_P_1024 0x44
19 #define MS5837_CMD_CONV_P_2048 0x46
20 #define MS5837_CMD_CONV_P_4096 0x48
21 #define MS5837_CMD_CONV_P_8192 0x4A
23 #define MS5837_CMD_CONV_T_256 0x50
24 #define MS5837_CMD_CONV_T_512 0x52
25 #define MS5837_CMD_CONV_T_1024 0x54
[all …]
/Zephyr-latest/arch/sparc/core/
Dstack_offsets.h16 #define STACK_FRAME_L0_OFFSET 0x00
17 #define STACK_FRAME_L1_OFFSET 0x04
18 #define STACK_FRAME_L2_OFFSET 0x08
19 #define STACK_FRAME_L3_OFFSET 0x0c
20 #define STACK_FRAME_L4_OFFSET 0x10
21 #define STACK_FRAME_L5_OFFSET 0x14
22 #define STACK_FRAME_L6_OFFSET 0x18
23 #define STACK_FRAME_L7_OFFSET 0x1c
24 #define STACK_FRAME_I0_OFFSET 0x20
25 #define STACK_FRAME_I1_OFFSET 0x24
[all …]
/Zephyr-latest/tests/crypto/crypto_hash/src/
Dmain.c23 uint8_t test2[] = {0xbd};
24 uint8_t test3[] = {0x5f, 0xd4};
25 uint8_t test4[] = {0xb0, 0xbd, 0x69};
26 uint8_t test5[] = {0xc9, 0x8c, 0x8e, 0x55};
27 uint8_t test6[] = {0x81, 0xa7, 0x23, 0xd9, 0x66};
29 0x83, 0x90, 0xcf, 0x0b, 0xe0, 0x76, 0x61, 0xcc, 0x76, 0x69, 0xaa, 0xc5,
30 0x4c, 0xe0, 0x9a, 0x37, 0x73, 0x3a, 0x62, 0x9d, 0x45, 0xf5, 0xd9, 0x83,
31 0xef, 0x20, 0x1f, 0x9b, 0x2d, 0x13, 0x80, 0x0e, 0x55, 0x5d, 0x9b, 0x10,
32 0x97, 0xfe, 0xc3, 0xb7, 0x83, 0xd7, 0xa5, 0x0d, 0xcb, 0x5e, 0x2b, 0x64,
33 0x4b, 0x96, 0xa1, 0xe9, 0x46, 0x3f, 0x17, 0x7c, 0xf3, 0x49, 0x06, 0xbf,
[all …]
/Zephyr-latest/drivers/spi/
Dspi_dw_regs.h17 #define DW_SPI_REG_CTRLR0 (0x00)
18 #define DW_SPI_REG_CTRLR1 (0x04)
19 #define DW_SPI_REG_SSIENR (0x08)
20 #define DW_SPI_REG_MWCR (0x0c)
21 #define DW_SPI_REG_SER (0x10)
22 #define DW_SPI_REG_BAUDR (0x14)
23 #define DW_SPI_REG_TXFTLR (0x18)
24 #define DW_SPI_REG_RXFTLR (0x1c)
25 #define DW_SPI_REG_TXFLR (0x20)
26 #define DW_SPI_REG_RXFLR (0x24)
[all …]
/Zephyr-latest/samples/modules/tflite-micro/magic_wand/src/
Dmagic_wand_model_data.cpp26 0x1c, 0x00, 0x00, 0x00, 0x54, 0x46, 0x4c, 0x33, 0x00, 0x00, 0x12, 0x00,
27 0x1c, 0x00, 0x04, 0x00, 0x08, 0x00, 0x0c, 0x00, 0x10, 0x00, 0x14, 0x00,
28 0x00, 0x00, 0x18, 0x00, 0x12, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
29 0x24, 0x4c, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00,
30 0x2c, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
31 0x14, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xdc, 0x00, 0x00, 0x00,
32 0x0f, 0x00, 0x00, 0x00, 0x54, 0x4f, 0x43, 0x4f, 0x20, 0x43, 0x6f, 0x6e,
33 0x76, 0x65, 0x72, 0x74, 0x65, 0x64, 0x2e, 0x00, 0x12, 0x00, 0x00, 0x00,
34 0xb0, 0x00, 0x00, 0x00, 0xa4, 0x00, 0x00, 0x00, 0x98, 0x00, 0x00, 0x00,
35 0x8c, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x74, 0x00, 0x00, 0x00,
[all …]

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