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/Zephyr-latest/tests/lib/cmsis_dsp/filtering/src/
Dmisc_q7.pat2 0xF3, 0xAE, 0x42, 0x21, 0x19, 0xE2, 0x32, 0x15,
3 0xF9, 0xC4, 0xB6, 0xE3, 0xE1, 0x49, 0x2F, 0x1A,
4 0xF9, 0xE0, 0x28, 0xEA, 0xF1, 0x41, 0x7F, 0x32,
5 0xD5, 0x04, 0xBF, 0x0B, 0xD0, 0xBC, 0x16, 0x20,
6 0xBD, 0x08, 0xD8, 0xF4, 0x2E, 0x13, 0xFB, 0xC4,
7 0x26, 0xF2, 0x05, 0x0E, 0xA9, 0x09, 0xDE, 0x42,
8 0x30, 0xFC, 0x16, 0xDB, 0x17, 0xD8, 0x02, 0x2C,
9 0xFD, 0x05, 0xEF, 0x02, 0x13, 0xDA, 0x03, 0x2D,
10 0x24, 0x0D, 0x0D, 0xE8, 0xF4, 0xB5, 0xF6, 0xB6,
11 0x1C, 0xDE, 0x09, 0x03, 0xF0, 0xCD, 0x0B, 0xB0,
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dstm32u0_reset.h13 #define STM32_RESET_BUS_IOP 0x2C
14 #define STM32_RESET_BUS_AHB1 0x28
15 #define STM32_RESET_BUS_APB1L 0x38
16 #define STM32_RESET_BUS_APB1H 0x40
Dstm32g0_reset.h13 #define STM32_RESET_BUS_IOP 0x24
14 #define STM32_RESET_BUS_AHB1 0x28
15 #define STM32_RESET_BUS_APB1L 0x2C
16 #define STM32_RESET_BUS_APB1H 0x30
Dstm32g4_l4_5_reset.h13 #define STM32_RESET_BUS_AHB1 0x28
14 #define STM32_RESET_BUS_AHB2 0x2C
15 #define STM32_RESET_BUS_AHB3 0x30
16 #define STM32_RESET_BUS_APB1L 0x38
17 #define STM32_RESET_BUS_APB1H 0x3C
18 #define STM32_RESET_BUS_APB2 0x40
Dstm32wb_l_reset.h13 #define STM32_RESET_BUS_AHB1 0x28
14 #define STM32_RESET_BUS_AHB2 0x2C
15 #define STM32_RESET_BUS_AHB3 0x30
16 #define STM32_RESET_BUS_APB1L 0x38
17 #define STM32_RESET_BUS_APB1H 0x3C
18 #define STM32_RESET_BUS_APB2 0x40
19 #define STM32_RESET_BUS_APB3 0x44
Dstm32c0_reset.h14 #define STM32_RESET_BUS_IOP 0x24
15 #define STM32_RESET_BUS_AHB1 0x28
16 #define STM32_RESET_BUS_APB1L 0x2C
17 #define STM32_RESET_BUS_APB1H 0x30
/Zephyr-latest/drivers/display/
Ddisplay_ist3931.h9 #define IST3931_CMD_NOP 0xe3
10 #define IST3931_CMD_IST_COMMAND_ENTRY 0x88
11 #define IST3931_CMD_EXIT_ENTRY 0xe3
12 #define IST3931_CMD_IST_COM_MAPPING 0x60
13 #define IST3931_CMD_POWER_CONTROL 0x2c
14 #define IST3931_CMD_BIAS 0x30
15 #define IST3931_CMD_CT 0xb1
16 #define IST3931_CMD_FRAME_CONTROL 0xb2
17 #define IST3931_CMD_SET_AX_ADD 0xc0
18 #define IST3931_CMD_SET_AY_ADD_LSB 0x00
[all …]
Ddisplay_st7789v.h11 #define ST7789V_CMD_NOP 0x00
12 #define ST7789V_CMD_SW_RESET 0x01
14 #define ST7789V_CMD_SLEEP_IN 0x10
15 #define ST7789V_CMD_SLEEP_OUT 0x11
16 #define ST7789V_CMD_INV_OFF 0x20
17 #define ST7789V_CMD_INV_ON 0x21
18 #define ST7789V_CMD_GAMSET 0x26
19 #define ST7789V_CMD_DISP_OFF 0x28
20 #define ST7789V_CMD_DISP_ON 0x29
22 #define ST7789V_CMD_CASET 0x2a
[all …]
Ddisplay_st7735r.h11 #define ST7735R_CMD_SW_RESET 0x01
12 #define ST7735R_CMD_RDDID 0x04
13 #define ST7735R_CMD_RDDST 0x09
14 #define ST7735R_CMD_RDDPM 0x0A
15 #define ST7735R_CMD_RDD_MADCTL 0x0B
16 #define ST7735R_CMD_RDD_COLMOD 0x0C
17 #define ST7735R_CMD_RDDIM 0x0D
18 #define ST7735R_CMD_RDDSM 0x0E
20 #define ST7735R_CMD_SLEEP_IN 0x10
21 #define ST7735R_CMD_SLEEP_OUT 0x11
[all …]
Ddisplay_st7796s.h10 #define ST7796S_CMD_SLPIN 0x10 /* Sleep in */
11 #define ST7796S_CMD_SLPOUT 0x11 /* Sleep out */
12 #define ST7796S_CMD_INVOFF 0x20 /* Display inversion off */
13 #define ST7796S_CMD_INVON 0x21 /* Display inversion on */
14 #define ST7796S_CMD_CASET 0x2A /* Column address set */
15 #define ST7796S_CMD_RASET 0x2B /* Row address set */
16 #define ST7796S_CMD_RAMWR 0x2C /* Memory write */
17 #define ST7796S_CMD_DISPOFF 0x28 /* Display off */
18 #define ST7796S_CMD_DISPON 0x29 /* Display on */
19 #define ST7796S_CMD_TEON 0x35 /* Tearing effect on */
[all …]
/Zephyr-latest/include/zephyr/drivers/mfd/
Daw9523b.h13 #define AW9523B_REG_INPUT0 0x00
14 #define AW9523B_REG_INPUT1 0x01
15 #define AW9523B_REG_OUTPUT0 0x02
16 #define AW9523B_REG_OUTPUT1 0x03
17 #define AW9523B_REG_CONFIG0 0x04
18 #define AW9523B_REG_CONFIG1 0x05
19 #define AW9523B_REG_INT0 0x06
20 #define AW9523B_REG_INT1 0x07
21 #define AW9523B_REG_ID 0x10
22 #define AW9523B_REG_CTL 0x11
[all …]
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dclock_agilex_ll.h13 #define CLKMGR_OFFSET 0xffd10000
15 #define CLKMGR_CTRL 0x0
16 #define CLKMGR_STAT 0x4
17 #define CLKMGR_INTRCLR 0x14
20 #define CLKMGR_MAINPLL 0xffd10024
21 #define CLKMGR_MAINPLL_EN 0x0
22 #define CLKMGR_MAINPLL_BYPASS 0xc
23 #define CLKMGR_MAINPLL_MPUCLK 0x18
24 #define CLKMGR_MAINPLL_NOCCLK 0x1c
25 #define CLKMGR_MAINPLL_NOCDIV 0x20
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_dw_registers.h15 #define SWPORTA_DR 0x00
16 #define SWPORTA_DDR 0x04
17 #define SWPORTA_CTL 0x08
18 #define SWPORTB_DR 0x0c
19 #define SWPORTB_DDR 0x10
20 #define SWPORTB_CTL 0x14
21 #define SWPORTC_DR 0x18
22 #define SWPORTC_DDR 0x1c
23 #define SWPORTC_CTL 0x20
24 #define SWPORTD_DR 0x24
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dst,lsm6dsv16x-common.yaml12 lsm6dsv16x: lsm6dsv16x@0 {
58 default: 0
62 - 0 # LSM6DSV16X_DT_FS_2G (0.061 mg/LSB)
67 enum: [0, 1, 2, 3]
71 default: 0x0
79 - 0x00 # LSM6DSV16X_DT_ODR_OFF
80 - 0x01 # LSM6DSV16X_DT_ODR_AT_1Hz875
81 - 0x02 # LSM6DSV16X_DT_ODR_AT_7Hz5
82 - 0x03 # LSM6DSV16X_DT_ODR_AT_15Hz
83 - 0x04 # LSM6DSV16X_DT_ODR_AT_30Hz
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_agilex5_ll.h19 #define CLKCTRL_OFFSET 0x00
20 #define CLKCTRL_CTRL 0x00
21 #define CLKCTRL_STAT 0x04
22 #define CLKCTRL_TESTIOCTRL 0x08
23 #define CLKCTRL_INTRGEN 0x0C
24 #define CLKCTRL_INTRMSK 0x10
25 #define CLKCTRL_INTRCLR 0x14
26 #define CLKCTRL_INTRSTS 0x18
27 #define CLKCTRL_INTRSTK 0x1C
28 #define CLKCTRL_INTRRAW 0x20
[all …]
/Zephyr-latest/dts/arm/nuvoton/
Dnpcx9mfp.dtsi16 reg = <0x10058000 DT_SIZE_K(416)>;
20 reg = <0x64000000 DT_SIZE_K(1024)>;
25 reg = <0x200C0000 DT_SIZE_K(92)>;
31 reg = <0x200D7000 DT_SIZE_K(4)>;
37 reg = <0x110 0x2c 0x15c 0x04>;
44 device-id = <0x2b>;
49 int_flash: w25q80@0 {
52 reg = <0>;
57 mapped-addr = <0x64000000>;
58 pinctrl-0 = <&int_flash_sl>;
/Zephyr-latest/tests/net/icmpv6/src/
Dmain.c46 "\x20\x21\x22\x23\x24\x25\x26\x27\x28\x29\x2a\x2b\x2c\x2d\x2e\x2f" \
55 "\x20\x21\x22\x23\x24\x25\x26\x27\x28\x29\x2a\x2b\x2c\x2d\x2e\x2f" \
64 "\x20\x21\x22\x23\x24\x25\x26\x27\x28\x29\x2a\x2b\x2c\x2d\x2e\x2f" \
80 return 0; in net_icmpv6_dev_init()
87 if (context->mac_addr[2] == 0x00) { in net_icmpv6_get_mac()
89 context->mac_addr[0] = 0x00; in net_icmpv6_get_mac()
90 context->mac_addr[1] = 0x00; in net_icmpv6_get_mac()
91 context->mac_addr[2] = 0x5E; in net_icmpv6_get_mac()
92 context->mac_addr[3] = 0x00; in net_icmpv6_get_mac()
93 context->mac_addr[4] = 0x53; in net_icmpv6_get_mac()
[all …]
/Zephyr-latest/arch/sparc/core/
Dstack_offsets.h16 #define STACK_FRAME_L0_OFFSET 0x00
17 #define STACK_FRAME_L1_OFFSET 0x04
18 #define STACK_FRAME_L2_OFFSET 0x08
19 #define STACK_FRAME_L3_OFFSET 0x0c
20 #define STACK_FRAME_L4_OFFSET 0x10
21 #define STACK_FRAME_L5_OFFSET 0x14
22 #define STACK_FRAME_L6_OFFSET 0x18
23 #define STACK_FRAME_L7_OFFSET 0x1c
24 #define STACK_FRAME_I0_OFFSET 0x20
25 #define STACK_FRAME_I1_OFFSET 0x24
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/dma/
Drpi-pico-dma-rp2350.h12 #define RPI_PICO_DMA_SLOT_PIO2_TX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x10)
13 #define RPI_PICO_DMA_SLOT_PIO2_TX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x11)
14 #define RPI_PICO_DMA_SLOT_PIO2_TX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x12)
15 #define RPI_PICO_DMA_SLOT_PIO2_TX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x13)
16 #define RPI_PICO_DMA_SLOT_PIO2_RX0 RPI_PICO_DMA_DREQ_TO_SLOT(0x14)
17 #define RPI_PICO_DMA_SLOT_PIO2_RX1 RPI_PICO_DMA_DREQ_TO_SLOT(0x15)
18 #define RPI_PICO_DMA_SLOT_PIO2_RX2 RPI_PICO_DMA_DREQ_TO_SLOT(0x16)
19 #define RPI_PICO_DMA_SLOT_PIO2_RX3 RPI_PICO_DMA_DREQ_TO_SLOT(0x17)
20 #define RPI_PICO_DMA_SLOT_SPI0_TX RPI_PICO_DMA_DREQ_TO_SLOT(0x18)
21 #define RPI_PICO_DMA_SLOT_SPI0_RX RPI_PICO_DMA_DREQ_TO_SLOT(0x19)
[all …]
/Zephyr-latest/include/zephyr/drivers/mm/
Drat.h18 #define RAT_CTRL(base_addr, i) (base_addr + 0x20 + 0x10 * (i))
19 #define RAT_BASE(base_addr, i) (base_addr + 0x24 + 0x10 * (i))
20 #define RAT_TRANS_L(base_addr, i) (base_addr + 0x28 + 0x10 * (i))
21 #define RAT_TRANS_H(base_addr, i) (base_addr + 0x2C + 0x10 * (i))
22 #define RAT_CTRL_W(enable, size) (((enable & 0x1) << 31u) | (size & 0x3F))
28 address_trans_region_size_1 = 0x0,
/Zephyr-latest/tests/lib/cmsis_dsp/statistics/src/
Dq7.pat2 0xD0, 0xCE, 0x16, 0x9B, 0x19, 0xE4, 0x10, 0x06,
3 0x1E, 0x07, 0x12, 0xD5, 0xDA, 0x0D, 0xF4, 0xF4,
4 0xE5, 0xDE, 0x23, 0xD6, 0xC9, 0x27, 0x22, 0x08,
5 0x1D, 0x13, 0x80, 0xF4, 0x1A, 0x38, 0x15, 0x22,
6 0x57, 0x38, 0xEF, 0x26, 0x11, 0xD8, 0x04, 0x0E,
7 0xF5, 0xE7, 0xF7, 0x18, 0x12, 0x2C, 0x0B, 0xBD,
8 0xFA, 0x05, 0xC1, 0xED, 0x25, 0xD1, 0xFA, 0x1D,
9 0xFF, 0x10, 0x1B, 0x46, 0x4E, 0x93, 0xDF, 0x30,
10 0x05, 0xF0, 0xF7, 0x02, 0xF3, 0x1A, 0x0B, 0x0A,
11 0xCB, 0x17, 0xE7, 0xD5, 0xF9, 0xC8, 0x0B, 0xF9,
[all …]
/Zephyr-latest/include/zephyr/bluetooth/mesh/
Dhealth_faults.h21 #define BT_MESH_HEALTH_FAULT_NO_FAULT 0x00
23 #define BT_MESH_HEALTH_FAULT_BATTERY_LOW_WARNING 0x01
24 #define BT_MESH_HEALTH_FAULT_BATTERY_LOW_ERROR 0x02
25 #define BT_MESH_HEALTH_FAULT_SUPPLY_VOLTAGE_TOO_LOW_WARNING 0x03
26 #define BT_MESH_HEALTH_FAULT_SUPPLY_VOLTAGE_TOO_LOW_ERROR 0x04
27 #define BT_MESH_HEALTH_FAULT_SUPPLY_VOLTAGE_TOO_HIGH_WARNING 0x05
28 #define BT_MESH_HEALTH_FAULT_SUPPLY_VOLTAGE_TOO_HIGH_ERROR 0x06
29 #define BT_MESH_HEALTH_FAULT_POWER_SUPPLY_INTERRUPTED_WARNING 0x07
30 #define BT_MESH_HEALTH_FAULT_POWER_SUPPLY_INTERRUPTED_ERROR 0x08
31 #define BT_MESH_HEALTH_FAULT_NO_LOAD_WARNING 0x09
[all …]
/Zephyr-latest/boards/shields/st7789v_generic/
Dst7789v_waveshare_240x240.overlay22 #size-cells = <0>;
24 st7789v_st7789v_waveshare_240x240: st7789v@0 {
27 reg = <0>;
30 x-offset = <0>;
31 y-offset = <0>;
32 vcom = <0x19>;
33 gctrl = <0x35>;
34 vrhs = <0x12>;
35 vdvs = <0x20>;
36 mdac = <0x00>;
[all …]
Dst7789v_tl019fqv01.overlay20 #size-cells = <0>;
22 st7789v_st7789v_tl019fqv01: st7789v@0 {
25 reg = <0>;
28 x-offset = <0>;
30 vcom = <0x2b>;
31 gctrl = <0x35>;
32 vrhs = <0x0f>;
33 vdvs = <0x20>;
34 mdac = <0x60>;
35 gamma = <0x01>;
[all …]
/Zephyr-latest/dts/arm/silabs/
Defr32xg13p.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
23 reg = <0>;
34 reg = <0x400e0000 0x104>;
35 interrupts = <25 0>;
40 flash0: flash@0 {
49 reg = <0x40010000 0x400>;
50 interrupts = <12 0>, <13 0>;
52 peripheral-id = <0>;
58 reg = <0x40010400 0x400>;
[all …]

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