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/Zephyr-latest/tests/kernel/mem_protect/mem_map/boards/
Dup_squared.overlay7 /* there is a memory hole from address 0x10000000-0x12150fff
9 * this range, so limit the memory range below 0x10000000.
12 reg = <0x0 0x10000000>;
/Zephyr-latest/samples/boards/st/ccm/
DREADME.rst21 should be initialized to 0. Like the normal bss section they
58 The total used CCM area : [0x10000000, 0x10000021)
59 Zero initialized BSS area : [0x10000000, 0x10000007)
60 Uninitialized NOINIT area : [0x10000008, 0x10000013)
61 Initialised DATA area : [0x10000014, 0x10000021)
62 Start of DATA in FLASH : 0x08003940
67 ccm_data_var_8 addr: 0x10000014 value: 0x12
68 ccm_data_var_16 addr: 0x10000016 value: 0x3456
69 ccm_data_var_32 addr: 0x10000018 value: 0x789abcde
70 ccm_data_array addr: 0x1000001c size: 5 value:
[all …]
/Zephyr-latest/dts/bindings/flash_controller/
Dnordic,nrf-qspi.yaml13 reg = <0x2b000 0x1000>, <0x10000000 0x10000000>;
18 Above, the register block with base address 0x2b000 and name
20 base address 0x10000000 and name "qspi_mm" is the XIP area.
35 const: 0
40 pinctrl-0:
/Zephyr-latest/dts/arm/nxp/
Dnxp_rt5xx.dtsi12 ranges = <0x20000000 0x30000000 0x500000
13 0x0 0x10000000 0x500000>;
17 ranges = <0x0 0x50000000 0x10000000>;
Dnxp_rt6xx.dtsi12 ranges = <0x20000000 0x30000000 0x500000
13 0x0 0x10000000 0x500000>;
17 ranges = <0x0 0x50000000 0x10000000>;
Dnxp_rw6xx.dtsi13 ranges = <0x20000000 0x30000000 0x130000
14 0x00000000 0x10000000 0x130000>;
18 ranges = <0x0 0x50000000 0x10000000>;
Dnxp_mcxn23x.dtsi13 ranges = <0x4000000 0x14000000 0x20000000>;
17 ranges = <0x0 0x50000000 0x10000000>;
20 ranges = <0x0 0x10000000 0x4000000>;
Dnxp_mcxn94x.dtsi13 ranges = <0x4000000 0x14000000 0x20000000>;
17 ranges = <0x0 0x50000000 0x10000000>;
20 ranges = <0x0 0x10000000 0x4000000>;
25 reg = <0x500c8000 0x1000>, <0x90000000 DT_SIZE_M(8)>;
Dnxp_lpc55S2x.dtsi15 ranges = <0x4000000 0x4000000 0x20000000>;
19 ranges = <0x0 0x40000000 0x10000000>;
22 ranges = <0x0 0x10000000 0x3020000>;
Dnxp_lpc55S6x.dtsi15 ranges = <0x4000000 0x14000000 0x20000000>;
19 ranges = <0x0 0x50000000 0x10000000>;
22 ranges = <0x0 0x10000000 0x3020000>;
Dnxp_mcxn23x_ns.dtsi10 ranges = <0x4000000 0x4000000 0x20000000>;
14 ranges = <0x0 0x40000000 0x10000000>;
Dnxp_lpc55S6x_ns.dtsi10 ranges = <0x4000000 0x4000000 0x20000000>;
14 ranges = <0x0 0x40000000 0x10000000>;
/Zephyr-latest/samples/drivers/mbox/remote/boards/
Dadp_xc7k_ae350.overlay19 reg = <0x10000000 0x10000000>;
/Zephyr-latest/tests/subsys/mem_mgmt/mem_attr/src/
Dmain.c22 for (size_t idx = 0; idx < num_regions; idx++) { in ZTEST()
23 if (region[idx].dt_size == 0x1000) { in ZTEST()
24 zassert_equal(region[idx].dt_addr, 0x10000000, "Wrong region address"); in ZTEST()
25 zassert_equal(region[idx].dt_size, 0x1000, "Wrong region size"); in ZTEST()
32 zassert_equal(region[idx].dt_addr, 0x20000000, "Wrong region address"); in ZTEST()
33 zassert_equal(region[idx].dt_size, 0x2000, "Wrong region size"); in ZTEST()
44 zassert_equal(mem_attr_check_buf((void *) 0x10000000, 0x0, DT_MEM_NON_VOLATILE), in ZTEST()
50 zassert_equal(mem_attr_check_buf((void *) 0x10000100, 0x100, in ZTEST()
52 0, "Unexpected return value"); in ZTEST()
53 zassert_equal(mem_attr_check_buf((void *) 0x20000000, 0x2000, DT_MEM_ARM_MPU_RAM_NOCACHE), in ZTEST()
[all …]
/Zephyr-latest/tests/lib/cmsis_dsp/fastmath/src/
Dq31.pat2 0x00000000, 0x10000000, 0x20000000, 0x30000000,
3 0x40000000, 0x50000000, 0x60000000, 0x7FFFFEAA,
4 0xF0000000, 0xE0000000, 0xD0000000, 0xC0000000,
5 0xB0000000, 0xA0000000, 0x80000000, 0x00000000,
6 0x10000000, 0x20000000, 0x30000000, 0x40000000,
7 0x50000000, 0x60000000, 0x7FFFFEAA
11 0xCCCCCCCD, 0x00000000, 0x0CCCCCCD, 0x7FFFFFFF,
12 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFFF
16 0x7FFFFFFF, 0x5A82799A, 0x00000000, 0xA57D8666,
17 0x80000000, 0xA57D8666, 0x00000000, 0x7FFFFFFF,
[all …]
/Zephyr-latest/boards/arm/mps3/
Dmps3_corstone300_an547.dts30 #size-cells = <0>;
32 cpu@0 {
35 reg = <0>;
41 reg = <0xe000ed90 0x40>;
48 #size-cells = <0>;
53 reg = <0x48102000>;
61 /* We utilize the secure addresses, if you subtract 0x10000000
64 itcm: itcm@10000000 { /* alias @ 0x0 */
66 reg = <0x10000000 DT_SIZE_K(512)>;
70 sram: sram@11000000 { /* alias @ 0x01000000 */
[all …]
Dmps3_corstone300_an552.dts29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
40 reg = <0xe000ed90 0x40>;
47 #size-cells = <0>;
52 reg = <0x48102000>;
60 /* We utilize the secure addresses, if you subtract 0x10000000
63 itcm: itcm@10000000 { /* alias @ 0x0 */
65 reg = <0x10000000 DT_SIZE_K(512)>;
69 sram: sram@11000000 { /* alias @ 0x01000000 */
[all …]
Dmps3_corstone300_fvp.dts29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
40 reg = <0xe000ed90 0x40>;
47 #size-cells = <0>;
52 reg = <0x48102000>;
60 /* We utilize the secure addresses, if you subtract 0x10000000
63 itcm: itcm@10000000 { /* alias @ 0x0 */
65 reg = <0x10000000 DT_SIZE_K(512)>;
69 sram: sram@11000000 { /* alias @ 0x01000000 */
[all …]
Dmps3_corstone310_an555.dts29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
40 reg = <0xe000ed90 0x40>;
47 #size-cells = <0>;
52 reg = <0x50004000>;
60 /* We utilize the secure addresses, if you subtract 0x10000000
63 itcm: itcm@10000000 { /* alias @ 0x0 */
65 reg = <0x10000000 DT_SIZE_K(32)>;
69 sram: sram@11000000 { /* alias @ 0x01000000 */
[all …]
Dmps3_corstone310_fvp.dts29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
40 reg = <0xe000ed90 0x40>;
47 #size-cells = <0>;
52 reg = <0x50004000>;
60 /* We utilize the secure addresses, if you subtract 0x10000000
63 itcm: itcm@10000000 { /* alias @ 0x0 */
65 reg = <0x10000000 DT_SIZE_K(32)>;
69 sram: sram@11000000 { /* alias @ 0x01000000 */
[all …]
/Zephyr-latest/boards/qemu/x86/
DKconfig.defconfig30 default 0x10000000 if ACPI
53 default 0x10000000 if ACPI
61 default 0x400000
83 default 0x400000
111 default 6 if NEWLIB_LIBC || (COMMON_LIBC_MALLOC && COMMON_LIBC_MALLOC_ARENA_SIZE != 0)
/Zephyr-latest/dts/arm64/qemu/
Dqemu-virt-a53.dtsi27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0>;
58 #clock-cells = <0>;
70 reg = <0x00 0x8000000 0x00 0x010000>,
71 <0x00 0x80a0000 0x00 0xf60000>;
75 #size-cells = <0x02>;
76 #address-cells = <0x02>;
80 reg = <0x00 0x8080000 0x00 0x20000>;
87 reg = <0x00 0x9000000 0x00 0x1000>;
[all …]
Dqemu-virt-arm64.dtsi27 #size-cells = <0>;
29 cpu@0 {
32 reg = <0>;
58 #clock-cells = <0>;
70 reg = <0x00 0x8000000 0x00 0x010000>,
71 <0x00 0x80a0000 0x00 0xf60000>;
75 #size-cells = <0x02>;
76 #address-cells = <0x02>;
80 reg = <0x00 0x8080000 0x00 0x20000>;
87 reg = <0x00 0x9000000 0x00 0x1000>;
[all …]
/Zephyr-latest/samples/drivers/ethernet/eth_ivshmem/boards/
Dqemu_cortex_a53.overlay13 reg = <0x0 0x70000000 0x0 DT_SIZE_M(128)>;
21 reg = <0x00 0x08e00000 0x00 0x100000>;
22 #size-cells = <0x02>;
23 #address-cells = <0x03>;
24 ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
25 #interrupt-cells = <0x01>;
26 interrupt-map-mask = <0x00 0x00 0x00 0x07>;
28 0x00 0x00 0x00 1 &gic 0 0 GIC_SPI 108 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
29 0x00 0x00 0x00 2 &gic 0 0 GIC_SPI 109 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
30 0x00 0x00 0x00 3 &gic 0 0 GIC_SPI 110 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
[all …]
/Zephyr-latest/boards/snps/nsim/arc_v/
Drmx100.dtsi6 reg = <0x80000000 0x10000000>; /* 256 MB */

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