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/Zephyr-latest/boards/silabs/radio_boards/slwrb4104a/
Dslwrb4104a.dts27 boot_partition: partition@0 {
29 reg = <0x0 0x00008000>;
33 /* Reserve 220 kB for the application in slot 0 */
35 label = "image-0";
36 reg = <0x00008000 0x00037000>;
42 reg = <0x0003f000 0x00037000>;
48 reg = <0x00076000 0x00008000>;
54 reg = <0x0007e000 0x00002000>;
/Zephyr-latest/boards/silabs/radio_boards/slwrb4170a/
Dslwrb4170a.dts27 boot_partition: partition@0 {
29 reg = <0x0 0x00008000>;
33 /* Reserve 220 kB for the application in slot 0 */
35 label = "image-0";
36 reg = <0x00008000 0x00037000>;
42 reg = <0x0003f000 0x00037000>;
48 reg = <0x00076000 0x00008000>;
54 reg = <0x0007e000 0x00002000>;
/Zephyr-latest/boards/silabs/radio_boards/slwrb4255a/
Dslwrb4255a.dts29 boot_partition: partition@0 {
31 reg = <0x0 0x00008000>;
35 /* Reserve 220 kB for the application in slot 0 */
37 label = "image-0";
38 reg = <0x00008000 0x00037000>;
44 reg = <0x0003f000 0x00037000>;
50 reg = <0x00076000 0x00008000>;
56 reg = <0x0007e000 0x00002000>;
64 pinctrl-0 = <&usart0_default>;
/Zephyr-latest/boards/nuvoton/numaker_m2l31ki/
Dnumaker_m2l31ki.dts48 boot_partition: partition@0 {
50 reg = <0x00000000 0x00008000>;
53 label = "image-0";
54 reg = <0x00008000 0x00038000>;
58 reg = <0x00040000 0x00038000>;
62 reg = <0x00078000 0x00008000>;
68 reg = <0x20000000 DT_SIZE_K(168)>;
73 pinctrl-0 = <&uart0_default>;
80 pinctrl-0 = <&usbd_default>;
/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dioapic.h21 #define IOAPIC_INT_MASK 0x00010000
22 #define IOAPIC_TRIGGER_MASK 0x00008000
23 #define IOAPIC_LEVEL 0x00008000
24 #define IOAPIC_EDGE 0x00000000
25 #define IOAPIC_REMOTE 0x00004000
26 #define IOAPIC_POLARITY_MASK 0x00002000
27 #define IOAPIC_LOW 0x00002000
28 #define IOAPIC_HIGH 0x00000000
29 #define IOAPIC_LOGICAL 0x00000800
30 #define IOAPIC_PHYSICAL 0x00000000
[all …]
/Zephyr-latest/boards/silabs/radio_boards/slwrb4161a/
Dslwrb4161a.dts27 boot_partition: partition@0 {
29 reg = <0x0 0x00008000>;
33 /* Reserve 220 kB for the application in slot 0 */
35 label = "image-0";
36 reg = <0x00008000 0x00037000>;
42 reg = <0x0003f000 0x00037000>;
48 reg = <0x00076000 0x00008000>;
54 reg = <0x0007e000 0x00002000>;
74 #size-cells = <0>;
75 pinctrl-0 = <&usart2_default>;
[all …]
/Zephyr-latest/boards/silabs/radio_boards/slwrb4250b/
Dslwrb4250b.dts20 pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
50 boot_partition: partition@0 {
52 reg = <0x0 0x00008000>;
56 /* Reserve 94 kB for the application in slot 0 */
58 label = "image-0";
59 reg = <0x00008000 0x00017800>;
65 reg = <0x0001f800 0x00017800>;
71 reg = <0x00037000 0x00007800>;
77 reg = <0x0003e800 0x00001800>;
85 pinctrl-0 = <&usart0_default>;
/Zephyr-latest/drivers/ethernet/
Deth_lan9250_priv.h23 #define LAN9250_SPI_INSTR_WRITE 0x02
24 #define LAN9250_SPI_INSTR_READ 0x03
27 #define LAN9250_TX_CMD_A_INT_ON_COMP 0x80000000
28 #define LAN9250_TX_CMD_A_BUFFER_ALIGN_4B 0x00000000
29 #define LAN9250_TX_CMD_A_START_OFFSET_0B 0x00000000
30 #define LAN9250_TX_CMD_A_FIRST_SEG 0x00002000
31 #define LAN9250_TX_CMD_A_LAST_SEG 0x00001000
34 #define LAN9250_TX_CMD_B_PACKET_TAG 0xFFFF0000
37 #define LAN9250_RX_STS_PACKET_LEN 0x3FFF0000
40 #define LAN9250_RX_DATA_FIFO 0x0000
[all …]
/Zephyr-latest/boards/ti/common/
Dlaunchxl-flash-p7.dtsi9 /* 40 KiB (0xa000) for MCUboot */
10 boot_partition: partition@0 {
12 reg = <0x00000000 0x0000a000>;
15 /* 136 KiB (0x22000) per slot for application */
17 label = "image-0";
18 reg = <0x0000a000 0x0004e000>;
23 reg = <0x00058000 0x0004e000>;
26 /* 32 KiB (0x8000) for storage */
29 reg = <0x000a6000 0x00008000>;
33 * flash sector (0x2000/8 KiB @ 0xae000), keep it unused.
Dlaunchxl-flash.dtsi9 /* 40 KiB (0xa000) for MCUboot */
10 boot_partition: partition@0 {
12 reg = <0x00000000 0x0000a000>;
15 /* 136 KiB (0x22000) per slot for application */
17 label = "image-0";
18 reg = <0x0000a000 0x00022000>;
23 reg = <0x0002c000 0x00022000>;
26 /* 32 KiB (0x8000) for storage */
29 reg = <0x0004e000 0x00008000>;
33 * flash sector (0x2000/8 KiB @ 0x56000), keep it unused.
/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Dintel-ioapic.h9 #define IRQ_TYPE_LEVEL 0x00008000
10 #define IRQ_TYPE_EDGE 0x00000000
11 #define IRQ_TYPE_LOW 0x00002000
12 #define IRQ_TYPE_HIGH 0x00000000
13 #define IRQ_DELIVERY_LOWEST 0x00000100
14 #define IRQ_DELIVERY_FIXED 0x00000000
/Zephyr-latest/boards/ezurio/bl654_sensor_board/
Dbl654_sensor_board.dts84 pinctrl-0 = <&uart0_default>;
93 pinctrl-0 = <&i2c0_default>;
99 reg = <0x76>;
105 pinctrl-0 = <&pwm0_default>;
120 boot_partition: partition@0 {
122 reg = <0x00000000 0x00010000>;
125 label = "image-0";
126 reg = <0x00010000 0x00070000>;
130 reg = <0x00080000 0x00070000>;
134 reg = <0x000f0000 0x00008000>;
[all …]
/Zephyr-latest/boards/seco/stm32f3_seco_d23/
Dstm32f3_seco_d23.dts71 standby-gpios = <&gpiod 0 GPIO_ACTIVE_HIGH>;
73 #phy-cells = <0>;
109 pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
117 pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6
125 pinctrl-0 = <&usart3_tx_pc10 &usart3_rx_pc11
132 pinctrl-0 = <&uart5_tx_pc12 &uart5_rx_pd2>;
138 pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
146 pinctrl-0 = <&i2c2_scl_pa9 &i2c2_sda_pa10>;
152 pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pb3
159 pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13
[all …]
/Zephyr-latest/dts/common/nordic/
Dnrf52840_partition.dtsi21 boot_partition: partition@0 {
23 reg = <0x00000000 0x0000C000>;
26 label = "image-0";
27 reg = <0x0000C000 0x00077000>;
31 reg = <0x00083000 0x00075000>;
35 * The flash starting at 0x000f8000 and ending at
36 * 0x000fffff is reserved for use by the application.
45 reg = <0x000f8000 0x00008000>;
Dnrf52840_partition_uf2_sdv7.dtsi20 * 0x00000000 SoftDevice s140 v7 (156 kB)
21 * 0x00027000 Application partition (788 kB)
22 * 0x000ec000 Storage partition (32 kB)
23 * 0x000f4000 UF2 boot partition (48 kB)
31 reserved_partition_0: partition@0 {
34 reg = <0x00000000 0x00027000>;
38 reg = <0x00027000 0x000C5000>;
43 reg = <0x000ec000 0x00008000>;
49 reg = <0x000f4000 0x0000c000>;
Dnrf52840_partition_uf2_sdv6.dtsi20 * 0x00000000 SoftDevice s140 v6 (152 kB)
21 * 0x00026000 Application partition (792 kB)
22 * 0x000ec000 Storage partition (32 kB)
23 * 0x000f4000 UF2 boot partition (48 kB)
33 reserved_partition_0: partition@0 {
36 reg = <0x00000000 0x00026000>;
40 reg = <0x00026000 0x000C6000>;
45 reg = <0x000ec000 0x00008000>;
51 reg = <0x000f4000 0x0000c000>;
/Zephyr-latest/boards/weact/blackpill_f401cc/
Dblackpill_f401cc.dts13 model = "WeAct Studio Black Pill V3.0 Board";
35 gpios = <&gpioa 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
55 boot_partition: partition@0 {
57 reg = <0x00000000 0x00008000>;
62 * The flash starting at offset 0x00008000 and ending at
63 * offset 0x0001ffff (sectors 2 through 4) is reserved for
68 label = "image-0";
69 reg = <0x00020000 0x00020000>;
73 reg = <0x00040000 0x00020000>;
77 reg = <0x00060000 0x00020000>;
[all …]
/Zephyr-latest/boards/st/nucleo_f410rb/
Dnucleo_f410rb.dts76 pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
83 pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
90 pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
97 pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb3>;
104 pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5
111 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
118 pinctrl-0 = <&dac_out1_pa5>;
129 boot_partition: partition@0 {
131 reg = <0x00000000 DT_SIZE_K(32)>;
136 * The flash sectors 2&3 at 0x00008000 and ending at
[all …]
/Zephyr-latest/boards/atmarktechno/degu_evk/
Ddegu_evk.dts46 gpios = <&gpio1 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
117 pinctrl-0 = <&uart0_default>;
125 pinctrl-0 = <&i2c0_default>;
133 pinctrl-0 = <&i2c1_default>;
148 boot_partition: partition@0 {
150 reg = <0x00000000 0x00014000>;
153 label = "image-0";
154 reg = <0x00014000 0x0006e000>;
158 reg = <0x00082000 0x0006e000>;
162 reg = <0x000f0000 0x00008000>;
[all …]
/Zephyr-latest/dts/bindings/mbox/
Dnordic,nrf-vevif-event-rx.yaml16 cpuflpr_vevif_event_rx: mailbox@0 {
18 reg = <0x0 0x1000>;
22 nordic,events-mask = <0x00008000>;
Dnordic,nrf-vevif-event-tx.yaml20 nordic,events-mask = <0x00008000>;
/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dboard.cmake12 board_runner_args(linkserver "--override=/device/memory/1/location=0x10000000")
15 board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x30000000\",\
16 \"size\":\"0x00060000\",\"type\":\"RAM\"\}")
17 board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x30060000\",\
18 \"size\":\"0x00008000\",\"type\":\"RAM\"\}")
20 board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x50000000\",\
21 \"size\":\"0x00140000\",\"type\":\"RAM\"\}")
26 # Pyocd support added with the NXP.MCXN947_DFP.17.0.0.pack CMSIS Pack
/Zephyr-latest/boards/qemu/cortex_m0/
Dqemu_cortex_m0.dts42 pinctrl-0 = <&uart0_default>;
54 boot_partition: partition@0 {
56 reg = <0x00000000 0x8000>;
59 label = "image-0";
60 reg = <0x00008000 0x1a000>;
64 reg = <0x00022000 0x1a000>;
68 reg = <0x0003c000 0x2000>;
72 reg = <0x0003e000 0x00002000>;
/Zephyr-latest/drivers/interrupt_controller/
Dintc_ioapic_priv.h15 #define IOAPIC_IND 0x00 /* Index Register */
16 #define IOAPIC_DATA 0x10 /* IO window (data) - pc.h */
17 #define IOAPIC_IRQPA 0x20 /* IRQ Pin Assertion Register */
18 #define IOAPIC_EOI 0x40 /* EOI Register */
22 #define IOAPIC_ID 0x00 /* IOAPIC ID */
23 #define IOAPIC_VERS 0x01 /* IOAPIC Version */
24 #define IOAPIC_ARB 0x02 /* IOAPIC Arbitration ID */
25 #define IOAPIC_BOOT 0x03 /* IOAPIC Boot Configuration */
26 #define IOAPIC_REDTBL 0x10 /* Redirection Table (24 * 64bit) */
30 #define IOAPIC_DT_APIC 0x0 /* APIC serial bus */
[all …]
/Zephyr-latest/drivers/fpga/
Dfpga_eos_s3.h13 /* Fabric Configuration Control Register, offset: 0x000 */
15 /* Maximum Bit Length Count, offset: 0x004 */
17 /* Maximum Word Length Count, offset: 0x008 */
20 /* Configuration Data, offset: 0xFFC */
26 #define FB_CFG_ENABLE ((uint32_t)(0x00000200))
27 #define FB_CFG_DISABLE ((uint32_t)(0x00000000))
29 #define CFG_CTL_APB_CFG_WR ((uint32_t)(0x00008000))
30 #define CFG_CTL_APB_CFG_RD ((uint32_t)(0x00004000))
31 #define CFG_CTL_APB_WL_DIN ((uint32_t)(0x00003C00))
32 #define CFG_CTL_APB_PARTIAL_LOAD ((uint32_t)(0x00000200))
[all …]

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