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/Zephyr-Core-3.6.0/samples/drivers/fpga/fpga_controller/src/
Dredled.h9 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
10 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
11 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
12 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
13 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
14 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
15 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
16 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
17 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
18 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
[all …]
/Zephyr-Core-3.6.0/subsys/bluetooth/host/
Dhfp_internal.h15 #define BT_HFP_AG_FEATURE_3WAY_CALL 0x00000001 /* Three-way calling */
16 #define BT_HFP_AG_FEATURE_ECNR 0x00000002 /* EC and/or NR function */
17 #define BT_HFP_AG_FEATURE_VOICE_RECG 0x00000004 /* Voice recognition */
18 #define BT_HFP_AG_INBAND_RING_TONE 0x00000008 /* In-band ring capability */
19 #define BT_HFP_AG_VOICE_TAG 0x00000010 /* Attach no. to voice tag */
20 #define BT_HFP_AG_FEATURE_REJECT_CALL 0x00000020 /* Ability to reject call */
21 #define BT_HFP_AG_FEATURE_ECS 0x00000040 /* Enhanced call status */
22 #define BT_HFP_AG_FEATURE_ECC 0x00000080 /* Enhanced call control */
23 #define BT_HFP_AG_FEATURE_EXT_ERR 0x00000100 /* Extended error codes */
24 #define BT_HFP_AG_FEATURE_CODEC_NEG 0x00000200 /* Codec negotiation */
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/f0/
Dstm32f030Xc.dtsi12 reg = <0x20000000 DT_SIZE_K(32)>;
19 reg = <0x08000000 DT_SIZE_K(256)>;
31 reg = <0x40004800 0x400>;
32 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
34 interrupts = <29 0>;
40 reg = <0x40004c00 0x400>;
41 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
43 interrupts = <29 0>;
49 reg = <0x40005000 0x400>;
50 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
[all …]
Dstm32f071.dtsi21 #clock-cells = <0>;
33 reg = <0x48001000 0x400>;
34 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
46 reg = <0x40004800 0x400>;
47 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
49 interrupts = <29 0>;
55 reg = <0x40004c00 0x400>;
56 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
58 interrupts = <29 0>;
64 reg = <0x40001400 0x400>;
[all …]
Dstm32f091.dtsi21 reg = <0x40005000 0x400>;
22 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
24 interrupts = <29 0>;
30 reg = <0x40011400 0x400>;
31 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
33 interrupts = <29 0>;
39 reg = <0x40011800 0x400>;
40 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
42 interrupts = <29 0>;
48 reg = <0x40011C00 0x400>;
[all …]
Dstm32f070Xb.dtsi11 reg = <0x20000000 DT_SIZE_K(16)>;
18 reg = <0x08000000 DT_SIZE_K(128)>;
30 reg = <0x40004800 0x400>;
31 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
33 interrupts = <29 0>;
39 reg = <0x40004c00 0x400>;
40 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
42 interrupts = <29 0>;
50 #size-cells = <0>;
51 reg = <0x40005800 0x400>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/l0/
Dstm32l031.dtsi15 reg = <0x40011400 0x400>;
16 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
18 interrupts = <22 0>;
20 st,prescaler = <0>;
31 reg = <0x08080000 DT_SIZE_K(1)>;
Dstm32l010Xb.dtsi12 reg = <0x20000000 DT_SIZE_K(20)>;
17 reg = <0x08080000 512>;
22 reg = <0x08000000 DT_SIZE_K(128)>;
28 reg = <0x40011400 0x400>;
29 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
31 interrupts = <22 0>;
Dstm32l071.dtsi18 reg = <0x50001000 0x400>;
19 clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000010>;
27 #size-cells = <0>;
28 reg = <0x40005800 0x400>;
29 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
30 interrupts = <24 0>;
39 #size-cells = <0>;
40 reg = <0x40007800 0x400>;
41 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
42 interrupts = <21 0>;
[all …]
Dstm32l051.dtsi17 #size-cells = <0>;
18 reg = <0x40005800 0x400>;
19 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
20 interrupts = <24 0>;
28 #size-cells = <0>;
29 reg = <0x40003800 0x400>;
30 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
37 reg = <0x40013800 0x400>;
38 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
40 interrupts = <27 0>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/g0/
Dstm32g050.dtsi15 reg = <0x40001000 0x400>;
16 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
18 interrupts = <17 0>;
20 st,prescaler = <0>;
26 reg = <0x40001400 0x400>;
27 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
29 interrupts = <18 0>;
31 st,prescaler = <0>;
36 interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
Dstm32g051.dtsi15 reg = <0x40001000 0x400>;
16 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
18 interrupts = <17 0>;
30 reg = <0x40001400 0x400>;
31 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
33 interrupts = <18 0>;
35 st,prescaler = <0>;
46 reg = <0x40014000 0x400>;
47 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00010000>;
49 interrupts = <20 0>;
[all …]
/Zephyr-Core-3.6.0/dts/bindings/clock/
Dst,stm32wba-rcc.yaml34 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
47 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>,
Dst,stm32-rcc.yaml33 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
49 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>,
/Zephyr-Core-3.6.0/drivers/sensor/vl53l1x/
Dvl53l1_platform_log.h64 #define VL53L1_TRACE_LEVEL_NONE 0x00000000
65 #define VL53L1_TRACE_LEVEL_ERRORS 0x00000001
66 #define VL53L1_TRACE_LEVEL_WARNING 0x00000002
67 #define VL53L1_TRACE_LEVEL_INFO 0x00000004
68 #define VL53L1_TRACE_LEVEL_DEBUG 0x00000008
69 #define VL53L1_TRACE_LEVEL_ALL 0x00000010
70 #define VL53L1_TRACE_LEVEL_IGNORE 0x00000020
72 #define VL53L1_TRACE_FUNCTION_NONE 0x00000000
73 #define VL53L1_TRACE_FUNCTION_I2C 0x00000001
74 #define VL53L1_TRACE_FUNCTION_ALL 0x7fffffff
[all …]
/Zephyr-Core-3.6.0/drivers/fpga/
Dfpga_eos_s3.h13 /* Fabric Configuration Control Register, offset: 0x000 */
15 /* Maximum Bit Length Count, offset: 0x004 */
17 /* Maximum Word Length Count, offset: 0x008 */
20 /* Configuration Data, offset: 0xFFC */
26 #define FB_CFG_ENABLE ((uint32_t)(0x00000200))
27 #define FB_CFG_DISABLE ((uint32_t)(0x00000000))
29 #define CFG_CTL_APB_CFG_WR ((uint32_t)(0x00008000))
30 #define CFG_CTL_APB_CFG_RD ((uint32_t)(0x00004000))
31 #define CFG_CTL_APB_WL_DIN ((uint32_t)(0x00003C00))
32 #define CFG_CTL_APB_PARTIAL_LOAD ((uint32_t)(0x00000200))
[all …]
/Zephyr-Core-3.6.0/include/zephyr/arch/riscv/
Dcsr.h12 #define MSTATUS_UIE 0x00000001
13 #define MSTATUS_SIE 0x00000002
14 #define MSTATUS_HIE 0x00000004
15 #define MSTATUS_MIE 0x00000008
16 #define MSTATUS_UPIE 0x00000010
17 #define MSTATUS_SPIE 0x00000020
18 #define MSTATUS_HPIE 0x00000040
19 #define MSTATUS_MPIE 0x00000080
20 #define MSTATUS_SPP 0x00000100
21 #define MSTATUS_HPP 0x00000600
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/l4/
Dstm32l432.dtsi15 #clock-cells = <0>;
23 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
24 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
30 #size-cells = <0>;
31 reg = <0x40003c00 0x400>;
32 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
39 reg = <0x40001400 0x400>;
40 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
42 interrupts = <55 0>;
44 st,prescaler = <0>;
[all …]
Dstm32l471.dtsi19 reg = <0x48000c00 0x400>;
20 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
27 reg = <0x48001000 0x400>;
28 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
35 reg = <0x48001400 0x400>;
36 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
43 reg = <0x48001800 0x400>;
44 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
50 reg = <0x40004800 0x400>;
51 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/f4/
Dstm32f412.dtsi15 #clock-cells = <0>;
25 reg = <0x40020000 0x1c00>;
31 reg = <0x40021400 0x400>;
32 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
39 reg = <0x40021800 0x400>;
40 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
46 reg = <0x40004800 0x400>;
47 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
49 interrupts = <39 0>;
56 #size-cells = <0>;
[all …]
Dstm32f405.dtsi19 reg = <0x40020000 0x2400>;
25 reg = <0x40021400 0x400>;
26 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
33 reg = <0x40021800 0x400>;
34 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
41 reg = <0x40022000 0x400>;
42 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
48 reg = <0x40004800 0x400>;
49 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
51 interrupts = <39 0>;
[all …]
/Zephyr-Core-3.6.0/drivers/ethernet/
Deth_xlnx_gem_priv.h30 * [31 .. 02] Mask for effective buffer address -> excludes [1..0]
34 #define ETH_XLNX_GEM_RXBD_WRAP_BIT 0x00000002
35 #define ETH_XLNX_GEM_RXBD_USED_BIT 0x00000001
36 #define ETH_XLNX_GEM_RXBD_BUFFER_ADDR_MASK 0xFFFFFFFC
49 * [21] VLAN tag (type ID 0x8100) detected
50 * [20] Priority tag: VLAN tag (type ID 0x8100) and null VLAN identifier
59 #define ETH_XLNX_GEM_RXBD_BCAST_BIT 0x80000000
60 #define ETH_XLNX_GEM_RXBD_MCAST_HASH_MATCH_BIT 0x40000000
61 #define ETH_XLNX_GEM_RXBD_UCAST_HASH_MATCH_BIT 0x20000000
62 #define ETH_XLNX_GEM_RXBD_SPEC_ADDR_MATCH_BIT 0x08000000
[all …]
/Zephyr-Core-3.6.0/include/zephyr/dt-bindings/pinctrl/
Dcc13xx_cc26xx-pinctrl.h13 #define IOC_PORT_GPIO 0x00000000 /* Default general purpose IO usage */
14 #define IOC_PORT_AON_CLK32K 0x00000007 /* AON External 32kHz clock */
15 #define IOC_PORT_AUX_IO 0x00000008 /* AUX IO Pin */
16 #define IOC_PORT_MCU_SSI0_RX 0x00000009 /* MCU SSI0 Receive Pin */
17 #define IOC_PORT_MCU_SSI0_TX 0x0000000A /* MCU SSI0 Transmit Pin */
18 #define IOC_PORT_MCU_SSI0_FSS 0x0000000B /* MCU SSI0 FSS Pin */
19 #define IOC_PORT_MCU_SSI0_CLK 0x0000000C /* MCU SSI0 Clock Pin */
20 #define IOC_PORT_MCU_I2C_MSSDA 0x0000000D /* MCU I2C Data Pin */
21 #define IOC_PORT_MCU_I2C_MSSCL 0x0000000E /* MCU I2C Clock Pin */
22 #define IOC_PORT_MCU_UART0_RX 0x0000000F /* MCU UART0 Receive Pin */
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/h7/
Dstm32h7.dtsi32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0>;
43 reg = <0xe000ed90 0x40>;
50 reg = <0x90000000 DT_SIZE_M(256)>;
57 #size-cells = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
73 #clock-cells = <0>;
80 #clock-cells = <0>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/wba/
Dstm32wba.dtsi30 #size-cells = <0>;
32 cpu0: cpu@0 {
35 reg = <0>;
42 reg = <0xe000ed90 0x40>;
76 reg = <0x48028000 DT_SIZE_K(16)>;
84 #clock-cells = <0>;
91 #clock-cells = <0>;
98 #clock-cells = <0>;
106 #clock-cells = <0>;
113 #clock-cells = <0>;
[all …]

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