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/Zephyr-latest/tests/lib/cmsis_dsp/transform/src/
Dcf64.pat2 0xbfa58a3e7ce8c268, 0x0,
3 0x3fdf7503d421b8a3, 0x0,
4 0x3fe7298971b2f05d, 0x0,
5 0x3fe27d5ab48bbded, 0x0,
6 0x3f8e957bf3faf458, 0x0,
7 0xbfda690069668b72, 0x0,
8 0xbfe71fc287a1a803, 0x0,
9 0xbfddfb560e6e15ae, 0x0,
10 0x3f98de5d5c60cb98, 0x0,
11 0x3fdf04b94d0d4acb, 0x0,
[all …]
Dcf16.pat2 0xa963, 0x0, 0x37dd, 0x0, 0x39ca, 0x0, 0x389f, 0x0,
3 0x23a5, 0x0, 0xb69a, 0x0, 0xb9c8, 0x0, 0xb77f, 0x0,
4 0x2638, 0x0, 0x37c1, 0x0, 0x3956, 0x0, 0x3800, 0x0,
5 0x9f32, 0x0, 0xb7f4, 0x0, 0xb9c0, 0x0, 0xb803, 0x0
9 0x2f3e, 0x0, 0xaa72, 0xb333, 0xb07c, 0xc59d, 0xaf3d, 0x20c9,
10 0x2943, 0x294b, 0xaebf, 0x293d, 0x2daf, 0x2a77, 0x1b0a, 0xaec2,
11 0xb384, 0x0, 0x1b0a, 0x2ec2, 0x2daf, 0xaa77, 0xaebf, 0xa93d,
12 0x2943, 0xa94b, 0xaf3d, 0xa0c9, 0xb07c, 0x459d, 0xaa72, 0x3333
16 0x2f3e, 0x0, 0xaa72, 0xb333, 0xb07c, 0xc59d, 0xaf3d, 0x20c9,
17 0x2943, 0x294b, 0xaebf, 0x293d, 0x2daf, 0x2a77, 0x1b0a, 0xaec2,
[all …]
Dcf32.pat2 0xbd2c51f4, 0x0, 0x3efba81f, 0x0,
3 0x3f394c4c, 0x0, 0x3f13ead6, 0x0,
4 0x3c74abe0, 0x0, 0xbed34803, 0x0,
5 0xbf38fe14, 0x0, 0xbeefdab0, 0x0,
6 0x3cc6f2eb, 0x0, 0x3ef825ca, 0x0,
7 0x3f2ab374, 0x0, 0x3effffb1, 0x0,
8 0xbbe63a4a, 0x0, 0xbefe8ffa, 0x0,
9 0xbf380fc4, 0x0, 0xbf006c31, 0x0
13 0x3de7b5a7, 0x0, 0xbd4e4efb, 0xbe666912,
14 0xbe0f8695, 0xc0b3a58e, 0xbde7a450, 0x3c191943,
[all …]
Drf16.pat2 0x2a24, 0x3771, 0x3a25, 0x378e, 0xabf0, 0xb7ba, 0xb987, 0xb7c1,
3 0xad2b, 0x389f, 0x39ce, 0x3828, 0xaed5, 0xb77d, 0xb9b5, 0xb826,
4 0x2941, 0x372e, 0x3994, 0x3757, 0xad1f, 0xb81b, 0xb9e2, 0xb6c2,
5 0x29f3, 0x385c, 0x3979, 0x3766, 0x28c3, 0xb745, 0xb89e, 0xb80b
9 0x2e71, 0xae39, 0x3551, 0x2f86, 0xa837, 0x3479, 0x2c4a, 0x2218,
10 0x3585, 0xc98d, 0xb475, 0x3362, 0xb10f, 0x2548, 0xa0cb, 0xb53f,
11 0xb50c, 0xb05c, 0xb042, 0x32d6, 0x3046, 0x2aca, 0xadc3, 0xa80e,
12 0x3202, 0x2cdf, 0xb021, 0xae43, 0x3868, 0x25a2, 0x34bd, 0xb297,
13 0x0
17 0x2e71, 0xae39, 0x3551, 0x2f86, 0xa837, 0x3479, 0x2c4a, 0x2218,
[all …]
Drf32.pat2 0x3d4488bd, 0x3eee16f4, 0x3f44a9f9, 0x3ef1b2dc,
3 0xbd7df235, 0xbef74e08, 0xbf30d013, 0xbef828a4,
4 0xbda55c29, 0x3f13dc88, 0x3f39b271, 0x3f04f489,
5 0xbddaa990, 0xbeef9469, 0xbf36936d, 0xbf04c5e0,
6 0x3d282c59, 0x3ee5cc2f, 0x3f327521, 0x3eead49b,
7 0xbda3eef9, 0xbf036c38, 0xbf3c329c, 0xbed84f0b,
8 0x3d3e582d, 0x3f0b7949, 0x3f2f1147, 0x3eecc652,
9 0x3d185c7c, 0xbee8a2da, 0xbf13b4a3, 0xbf015ee5
13 0x3dce2251, 0xbdc712ec, 0x3eaa1a3e, 0x3df0bf58,
14 0xbd06e1c5, 0x3e8f19ba, 0x3d894baf, 0x3c42f1aa,
[all …]
Drf64.pat2 0x3fa89117984a9562, 0x3fddc2de7434712d,
3 0x3fe8953f1cd52833, 0x3fde365b89867849,
4 0xbfafbe46aab40401, 0xbfdee9c10a4d1b7a,
5 0xbfe61a026041333c, 0xbfdf0514866bb5c2,
6 0xbfb4ab8518e22a6c, 0x3fe27b90f4351232,
7 0x3fe7364e272ce422, 0x3fe09e911971446b,
8 0xbfbb5531fa2e1aa9, 0xbfddf28d1b1c50ef,
9 0xbfe6d26da0d26eca, 0xbfe098bc0fcec34a,
10 0x3fa5058b1de3a42a, 0x3fdcb985e7b42496,
11 0x3fe64ea42cf02730, 0x3fdd5a9357e2dbe8,
[all …]
/Zephyr-latest/tests/lib/cmsis_dsp/matrix/src/
Dunary_f64.pat2 0x3fd7ba2f51a73bdc, 0x3fdc1f062f146f99,
3 0x3fcb4f3a611d8495, 0x3fb685d5f044a336,
4 0x3fcdf3d31d5b3612, 0xbfcfdbce4fe538b2,
5 0xbfc341650513a720, 0xbfc0711fd80e2710,
6 0x3fa25544691b26bc, 0x3fd7c683cd79b220,
7 0xbfcc45ca64ea972f, 0x3fd3c993dd1fe79b,
8 0x3fb10e0ac270edde, 0x3fb8bcad734ed1c3,
9 0xbfc006a92355eeff, 0x3fd96e5adb679277,
10 0xbfdd67ea98c77e51, 0x3fb1d6f2e4d0cc06,
11 0x3fb5e6ff6c3795e3, 0x3fd764ccbdf3c880,
[all …]
Dunary_f32.pat2 0xbc2a6b72, 0xbe5302a4, 0xbe851f28, 0xbde85867,
3 0x3e060969, 0x3dd11a7e, 0xbe26a669, 0xbe18f3a1,
4 0xbe933111, 0xbeebb5ca, 0x3e20f2dd, 0xbe547c76,
5 0xbeb0f580, 0xbe9e95cb, 0xbed62921, 0xbe6e19ee,
6 0xbda9575d, 0xbe7e58ce, 0xbe728c31, 0x3ee6b5c8,
7 0x3ee66649, 0x3e099e87, 0x3e008e8b, 0xbce5533c,
8 0x3cbdf6a4, 0xbcb896e4, 0x3dff7685, 0xbcb4ee27,
9 0x3dcd3f72, 0xbe94cbe3, 0x3dc968ff, 0xbee309ae,
10 0xbd197a4d, 0x3eeb9f21, 0xbe4b4f45, 0xbe6156ce,
11 0x3df013c9, 0x3d8d01b9, 0xbd1a3282, 0xbd8b3c3b,
[all …]
Dunary_f16.pat2 0x1fc8, 0xb0a5, 0xaca3, 0xb043, 0x301e, 0x3831, 0x2ffc, 0xb7d2,
3 0xb41e, 0xb836, 0xa713, 0x3505, 0x3239, 0x30a9, 0xb61d, 0xb56d,
4 0xb7f3, 0x2d1d, 0x3590, 0x2f3e, 0x1ad2, 0xb113, 0x3688, 0xacfd,
5 0xb25b, 0xb124, 0x3512, 0x2890, 0xadd0, 0x328c, 0xb16c, 0xb0f6,
6 0xb46a, 0xae1e, 0x38b2, 0xaf43, 0x3142, 0xbaf5, 0xb052, 0x2b74,
7 0xb275, 0x395e, 0x35fd, 0xb6fb, 0xb0fd, 0x267c, 0x2853, 0xaefb,
8 0xaa93, 0xb610, 0xb37f, 0xb4d6, 0x301a, 0xa1ef, 0x37ed, 0x318c,
9 0xae09, 0x3015, 0xb808, 0x2579, 0xb476, 0x3602, 0xb6e3, 0xb111,
10 0x2846, 0xb075, 0xa077, 0x387a, 0x334d, 0x296d, 0x32b1, 0x34c7,
11 0x340d, 0x320d, 0x3455, 0xaeeb, 0xa804, 0xb05c, 0xb19b, 0xa41f,
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/silabs/
Dxg22-pinctrl.h16 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 2)
19 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 4, 0, 0, 1)
21 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 15, 1, 0, 1)
25 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 20, 1, 0, 1)
28 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 24, 1, 0, 1)
31 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 28, 1, 0, 1)
34 #define SILABS_DBUS_EUART0_RTS(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 2)
36 #define SILABS_DBUS_EUART0_CTS(port, pin) SILABS_DBUS(port, pin, 32, 0, 0, 1)
37 #define SILABS_DBUS_EUART0_RX(port, pin) SILABS_DBUS(port, pin, 32, 0, 0, 3)
39 #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 38, 1, 0, 1)
[all …]
Dxg23-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 16, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 22, 0, 0, 1)
25 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 33, 1, 0, 1)
30 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 33, 0, 0, 2)
32 #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 41, 1, 0, 1)
37 #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 41, 0, 0, 2)
39 #define SILABS_DBUS_EUSART2_CS(port, pin) SILABS_DBUS(port, pin, 49, 1, 0, 1)
44 #define SILABS_DBUS_EUSART2_CTS(port, pin) SILABS_DBUS(port, pin, 49, 0, 0, 2)
[all …]
Dxg21-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1)
25 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 17, 1, 0, 1)
29 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 1)
32 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 26, 1, 0, 1)
35 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 30, 1, 0, 1)
38 #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 34, 1, 0, 1)
42 #define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 34, 0, 0, 4)
[all …]
Dxg27-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 2)
21 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 7, 0, 0, 1)
23 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
28 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 19, 0, 0, 2)
30 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 27, 1, 0, 1)
34 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 1)
37 #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 36, 1, 0, 1)
40 #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 40, 1, 0, 1)
43 #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 44, 1, 0, 1)
[all …]
Dxg24-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1)
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2)
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1)
25 #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 21, 1, 0, 1)
30 #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 21, 0, 0, 2)
32 #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 29, 1, 0, 1)
37 #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 29, 0, 0, 2)
39 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 37, 1, 0, 1)
43 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 42, 1, 0, 1)
[all …]
/Zephyr-latest/tests/lib/cmsis_dsp/filtering/src/
Dmisc_f16.pat2 0x3573, 0xb347, 0xb820, 0x3b24, 0xb212, 0x3b86, 0x3961, 0xb72d,
3 0xb4b9, 0xb027, 0x3949, 0xa086, 0x9f90, 0x3497, 0xb5f5, 0x38f8,
4 0xaf6c, 0x3461, 0x36c8, 0x38d0, 0xabaa, 0xb6a1, 0x33bc, 0xb9b2,
5 0x251b, 0xb14d, 0xaf8e, 0xb522, 0xaf61, 0xb6f6, 0xb1d7, 0xb03f,
6 0xb216, 0x9f6b, 0xa909, 0x2798, 0x283b, 0x2c52, 0xb127, 0x2148,
7 0xb832, 0x39cb, 0x2b98, 0x3a2e, 0x29a8, 0xb438, 0xb123, 0xaa85,
8 0x32b8, 0xacff, 0x38d1, 0x254e, 0xb320, 0xa31d, 0x3534, 0xb40f,
9 0xb8a7, 0xb48f, 0xaf99, 0x3965, 0x3644, 0x2433, 0x394d, 0xb008,
10 0x366e, 0xb5a7, 0x395c, 0xb137, 0xb81d, 0xac69, 0x38d7, 0x2987,
11 0xbc00, 0x35ac, 0x39a6, 0xb2ee, 0x3056, 0xb8b3, 0x32d4, 0xace4,
[all …]
Dmisc_f32.pat2 0x3f5fb92f, 0x3ea747ed, 0xbf03d245, 0xbe217751,
3 0x3f0d52ec, 0xbe5d25c8, 0x3e8b5b01, 0x3deb1ad1,
4 0xbe26468f, 0x3f15f863, 0xbef779eb, 0x3e9e4168,
5 0x3e3b9a00, 0x3e651db9, 0xbefcfff2, 0xbe9ba0c7,
6 0x3e85d0e3, 0xbea6c8db, 0xbec376bb, 0x3ee9701e,
7 0x3e5b7279, 0xbef8254f, 0x3f0f914c, 0x3f5af068,
8 0xbf37d326, 0xbe6a8921, 0xbe985a21, 0x3e920446,
9 0x3da5e8e3, 0xbe5c5643, 0x3e9f09d6, 0x3f10e0da,
10 0xbe252b96, 0xbe01794a, 0xbdd2684b, 0xbe8b0ec0,
11 0xbf02c5b3, 0xbeacf299, 0xbecd7401, 0xbd5f6d6b,
[all …]
/Zephyr-latest/soc/xlnx/zynq7000/common/
Dpinctrl_soc.h43 #define MIO_PIN_TRI_ENABLE_MASK BIT(0)
53 #define MIO_PIN_FUNCTION_ETHERNET0 MIO_PIN_LX_SEL(0x0, 0x0, 0x0, 0x1)
54 #define MIO_PIN_FUNCTION_ETHERNET1 MIO_PIN_LX_SEL(0x0, 0x0, 0x0, 0x1)
55 #define MIO_PIN_FUNCTION_MDIO0 MIO_PIN_LX_SEL(0x4, 0x0, 0x0, 0x0)
56 #define MIO_PIN_FUNCTION_MDIO1 MIO_PIN_LX_SEL(0x5, 0x0, 0x0, 0x0)
57 #define MIO_PIN_FUNCTION_QSPI0 MIO_PIN_LX_SEL(0x0, 0x0, 0x0, 0x1)
58 #define MIO_PIN_FUNCTION_QSPI1 MIO_PIN_LX_SEL(0x0, 0x0, 0x0, 0x1)
59 #define MIO_PIN_FUNCTION_QSPI_FBCLK MIO_PIN_LX_SEL(0x0, 0x0, 0x0, 0x1)
60 #define MIO_PIN_FUNCTION_QSPI_CS1 MIO_PIN_LX_SEL(0x0, 0x0, 0x0, 0x1)
61 #define MIO_PIN_FUNCTION_SPI0 MIO_PIN_LX_SEL(0x5, 0x0, 0x0, 0x0)
[all …]
/Zephyr-latest/tests/kernel/device/boards/
Dhifive_unmatched_fu740_s7.overlay19 reg = <0x0 0xE0000000 0x0 0x2000>;
24 reg = <0x0 0xE1000000 0x0 0x2000>;
29 reg = <0x0 0xE2000000 0x0 0x2000>;
34 reg = <0x0 0xE3000000 0x0 0x2000>;
39 reg = <0x0 0xE4000000 0x0 0x2000>;
45 reg = <0x0 0xE5000000 0x0 0x1000>,
46 <0x0 0xE6000000 0x0 0x1000>;
54 reg = <0x0 0xE7000000 0x0 0x2000>;
61 reg = <0x0 0xE8000000 0x0 0x2000>;
69 #power-domain-cells = <0>;
[all …]
Dhifive_unmatched_fu740_u74.overlay19 reg = <0x0 0xE0000000 0x0 0x2000>;
24 reg = <0x0 0xE1000000 0x0 0x2000>;
29 reg = <0x0 0xE2000000 0x0 0x2000>;
34 reg = <0x0 0xE3000000 0x0 0x2000>;
39 reg = <0x0 0xE4000000 0x0 0x2000>;
45 reg = <0x0 0xE5000000 0x0 0x1000>,
46 <0x0 0xE6000000 0x0 0x1000>;
54 reg = <0x0 0xE7000000 0x0 0x2000>;
61 reg = <0x0 0xE8000000 0x0 0x2000>;
69 #power-domain-cells = <0>;
[all …]
/Zephyr-latest/dts/riscv/sifive/
Driscv64-fu740.dtsi18 #clock-cells = <0>;
24 #clock-cells = <0>;
32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0>;
43 #address-cells = <0>;
52 reg = <0x1>;
57 #address-cells = <0>;
66 reg = <0x2>;
71 #address-cells = <0>;
[all …]
/Zephyr-latest/dts/common/broadcom/
Dviper-common.dtsi11 reg = <0x00400000 0x80000>;
16 reg = <0x40020000 0x400>;
24 reg = <0x48100000 0x400>;
32 reg = <0x48300000 0x2000>,
33 <0x482f005c 0x20>;
36 microcode = <0x63b00000 0x1000>;
48 reg = <0x0 0x4e100000 0x0 0x2100>,
49 <0x0 0x50000000 0x0 0x8000000>,
50 <0x4 0x0 0x0 0x8000000>;
53 dmas = <&pl330 0>, <&pl330 1>;
[all …]
/Zephyr-latest/arch/arm64/core/
Dfpu.S16 stp q0, q1, [x0, #(16 * 0)]
17 stp q2, q3, [x0, #(16 * 2)]
18 stp q4, q5, [x0, #(16 * 4)]
19 stp q6, q7, [x0, #(16 * 6)]
20 stp q8, q9, [x0, #(16 * 8)]
21 stp q10, q11, [x0, #(16 * 10)]
22 stp q12, q13, [x0, #(16 * 12)]
23 stp q14, q15, [x0, #(16 * 14)]
24 stp q16, q17, [x0, #(16 * 16)]
25 stp q18, q19, [x0, #(16 * 18)]
[all …]
Duserspace.S28 mov x3, x0
29 mov x0, #0
30 mov x4, #0
34 cmp x0, x1
38 ldrb w5, [x3, x0]
42 add x0, x0, #1
47 mov x0, #0
60 add x1, x1, x0
66 at S1E0R, x0
68 1: at S1E0W, x0
[all …]
/Zephyr-latest/tests/lib/shared_multi_heap/boards/
Dqemu_cortex_a53.overlay14 reg = <0x0 0x42000000 0x0 0x1000>;
21 reg = <0x0 0x43000000 0x0 0x2000>;
28 reg = <0x0 0x45000000 0x0 0x1000>;
34 reg = <0x0 0x44000000 0x0 0x3000>;
/Zephyr-latest/dts/riscv/starfive/
Dstarfive_jh7100_beagle_v.dtsi18 #size-cells = <0>;
20 cpu@0 {
21 clock-frequency = <0>;
36 reg = <0>;
43 #address-cells = <0>;
50 clock-frequency = <0>;
72 #address-cells = <0>;
81 reg = <0x0 0x80000000 0x2 0x0>;
101 reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
107 reg = <0x0 0x1808000 0x0 0x8000>;
[all …]

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