Home
last modified time | relevance | path

Searched +full:0 +full:b11 (Results 1 – 21 of 21) sorted by relevance

/Zephyr-latest/dts/bindings/sensor/
Djedec,jc-42.4-temp.yaml28 Sensor resolution. Default is 0.0625C (0b11),
30 0 = 0.5°C
35 - 0 # 0.5C
/Zephyr-latest/subsys/sd/
Dmmc.c19 * [31:26] : Set to 0
23 * [7:3] : Set to 0
24 * [2:0] : Cmd Set
27 (0xFC000000 & (0U << 26)) + (0x03000000 & (0b11 << 24)) + (0x00FF0000 & (183U << 16)) + \
28 (0x0000FF00 & (6U << 8)) + (0x000000F7 & (0U << 3)) + (0x00000000 & (3U << 0))
30 (0xFC000000 & (0U << 26)) + (0x03000000 & (0b11 << 24)) + (0x00FF0000 & (183U << 16)) + \
31 (0x0000FF00 & (2U << 8)) + (0x000000F7 & (0U << 3)) + (0x00000000 & (3U << 0))
33 (0xFC000000 & (0U << 26)) + (0x03000000 & (0b11 << 24)) + (0x00FF0000 & (183U << 16)) + \
34 (0x0000FF00 & (1U << 8)) + (0x000000F7 & (0U << 3)) + (0x00000000 & (3U << 0))
36 (0xFC000000 & (0U << 26)) + (0x03000000 & (0b11 << 24)) + (0x00FF0000 & (185U << 16)) + \
[all …]
/Zephyr-latest/include/zephyr/drivers/sensor/
Dveml7700.h43 VEML7700_ALS_GAIN_1 = 0x00, /* 0b00 */
44 VEML7700_ALS_GAIN_2 = 0x01, /* 0b01 */
45 VEML7700_ALS_GAIN_1_8 = 0x02, /* 0b10 */
46 VEML7700_ALS_GAIN_1_4 = 0x03, /* 0b11 */
65 VEML7700_INT_DISABLED = 0xFF,
66 VEML7700_ALS_PERS_1 = 0x00, /* 0b00 */
67 VEML7700_ALS_PERS_2 = 0x01, /* 0b01 */
68 VEML7700_ALS_PERS_4 = 0x02, /* 0b10 */
69 VEML7700_ALS_PERS_8 = 0x03, /* 0b11 */
/Zephyr-latest/subsys/bluetooth/host/classic/
Davctp_internal.h12 #define BT_L2CAP_PSM_AVCTP 0x0017
15 BT_AVCTP_IPID_NONE = 0b0,
16 BT_AVCTP_IPID_INVALID = 0b1,
20 BT_AVCTP_CMD = 0b0,
21 BT_AVCTP_RESPONSE = 0b1,
25 BT_AVCTP_PKT_TYPE_SINGLE = 0b00,
26 BT_AVCTP_PKT_TYPE_START = 0b01,
27 BT_AVCTP_PKT_TYPE_CONTINUE = 0b10,
28 BT_AVCTP_PKT_TYPE_END = 0b11,
32 uint8_t byte0; /** [7:4]: Transaction label, [3:2]: Packet_type, [1]: C/R, [0]: IPID */
[all …]
/Zephyr-latest/drivers/dma/
Ddma_si32.c31 BUILD_ASSERT((uintptr_t)SI32_DMACTRL_0 == (uintptr_t)DT_INST_REG_ADDR(0),
34 #define CHANNEL_COUNT DT_INST_PROP(0, dma_channels) /* number of used/enabled DMA channels */
73 __ASSERT(channel_descriptor->CONFIG.TMD == 0, "Result of success: TMD set to zero"); in dma_si32_isr_handler()
74 __ASSERT(channel_descriptor->CONFIG.NCOUNT == 0, in dma_si32_isr_handler()
77 __ASSERT((SI32_DMACTRL_0->CHENSET.U32 & BIT(channel)) == 0, in dma_si32_isr_handler()
85 cb(DEVICE_DT_INST_GET(0), user_data, channel, result); in dma_si32_isr_handler()
90 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, channel, irq), \
91 DT_INST_IRQ_BY_IDX(0, channel, priority), dma_si32_isr_handler, \
92 channel, 0); \
115 SI32_DMACTRL_A_write_chalt(SI32_DMACTRL_0, 0); in dma_si32_init()
[all …]
/Zephyr-latest/drivers/audio/
Dwm8904.h14 #define WM8904_REG_RESET (0x00)
15 #define WM8904_REG_ANALOG_ADC_0 (0x0A)
16 #define WM8904_REG_POWER_MGMT_0 (0x0C)
17 #define WM8904_REG_POWER_MGMT_2 (0x0E)
18 #define WM8904_REG_POWER_MGMT_3 (0x0F)
19 #define WM8904_REG_POWER_MGMT_6 (0x12)
20 #define WM8904_REG_CLK_RATES_0 (0x14)
21 #define WM8904_REG_CLK_RATES_1 (0x15)
22 #define WM8904_REG_CLK_RATES_2 (0x16)
23 #define WM8904_REG_AUDIO_IF_0 (0x18)
[all …]
/Zephyr-latest/drivers/mfd/
Dmfd_bd8lb600fs.c21 #define OUTPUT_OFF_WITH_OPEN_LOAD_DETECTION 0b11
22 #define OUTPUT_ON 0b10
33 /* each bit is one output channel, bit 0 = channel 1, ... */
46 uint16_t state_converted = 0; in bd8lb600fs_fill_tx_buffer()
48 LOG_DBG("%s: writing state 0x%08X to BD8LB600FS", dev->name, data->state); in bd8lb600fs_fill_tx_buffer()
50 memset(buffer, 0x00, buffer_size); in bd8lb600fs_fill_tx_buffer()
52 for (size_t j = 0; j < config->instance_count; ++j) { in bd8lb600fs_fill_tx_buffer()
55 state_converted = 0; in bd8lb600fs_fill_tx_buffer()
57 for (size_t i = 0; i < 8; ++i) { in bd8lb600fs_fill_tx_buffer()
58 if ((data->state & BIT(i + j * 8)) == 0) { in bd8lb600fs_fill_tx_buffer()
[all …]
/Zephyr-latest/drivers/crypto/
Dcrypto_si32.c40 #define DMA_CHANNEL_COUNT DT_PROP(DT_INST(0, silabs_si32_dma), dma_channels)
42 #define DMA_CHANNEL_ID_RX DT_INST_DMAS_CELL_BY_NAME(0, rx, channel)
43 #define DMA_CHANNEL_ID_TX DT_INST_DMAS_CELL_BY_NAME(0, tx, channel)
44 #define DMA_CHANNEL_ID_XOR DT_INST_DMAS_CELL_BY_NAME(0, xor, channel)
65 K_SEM_DEFINE(crypto_si32_work_done, 0, 1);
130 __ASSERT(SI32_AES_0->CONTROL.RESET == 0, "Reset done"); in crypto_si32_init()
144 IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), crypto_si32_irq_error_handler, in crypto_si32_init()
145 DEVICE_DT_INST_GET(0), 0); in crypto_si32_init()
146 irq_enable(DT_INST_IRQN(0)); in crypto_si32_init()
158 return 0; in crypto_si32_init()
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_rzt2m.c22 #define PMm_OFFSET 0x200
23 #define PMCm_OFFSET 0x400
24 #define PFCm_OFFSET 0x600
25 #define PINm_OFFSET 0x800
26 #define DRCTLm_OFFSET 0xa00
28 #define PMm_SIZE 0x2
29 #define DRCTLm_SIZE 0x8
30 #define PFCm_SIZE 0x4
33 #define DRIVE_SHIFT 0
38 #define PULL_NONE (0 << PULL_SHIFT)
[all …]
Dgpio_pca_series.c30 #define PCA_HAS_LATCH BIT(0) /** + output_drive_strength, + input_latch */
38 #define PCA_PIN(gpio_pin) (gpio_pin & GENMASK(2, 0))
40 #define PCA_REG_INVALID (0xff)
70 * - Type 0: PCA953X, PCA955X
77 PCA_REG_TYPE_1B_INPUT_PORT = 0U, /** x x x x */
137 PCA_INTERRUPT_LEVEL_CHANGE = 0U, /* default */
206 return 0; in gpio_pca_series_reg_get_addr()
219 * 0 if fail
227 return 0; in gpio_pca_series_reg_size_per_port()
259 return 0; /** should never happen */ in gpio_pca_series_reg_size_per_port()
[all …]
/Zephyr-latest/drivers/timer/
Dcortex_m_systick.c15 #define COUNTER_MAX 0x00ffffff
16 #define TIMER_STOPPED 0xff000000
125 * decrements from 1 to 0. Reading the control register in elapsed()
131 * Armv8-m (B11.1) https://developer.arm.com/documentation/ddi0553 in elapsed()
133 * First, manually wrap/realign val1 and val2 from [0:last_load-1] in elapsed()
146 if (val1 == 0) { in elapsed()
149 if (val2 == 0) { in elapsed()
182 overflow_cyc = 0; in sys_clock_isr()
201 * the counter (VAL = 0). in sys_clock_isr()
246 .flags = 0, in sys_clock_set_timeout()
[all …]
/Zephyr-latest/samples/boards/nordic/mesh/onoff_level_lighting_vnd_app/src/mesh/
Dtransition.c37 /* > 620 seconds -> resolution = 0b11 [10 minutes] */ in calculate_rt()
38 resolution = 0x03; in calculate_rt()
41 /* > 62 seconds -> resolution = 0b10 [10 seconds] */ in calculate_rt()
42 resolution = 0x02; in calculate_rt()
45 /* > 6.2 seconds -> resolution = 0b01 [1 seconds] */ in calculate_rt()
46 resolution = 0x01; in calculate_rt()
48 } else if (duration_remainder > 0) { in calculate_rt()
49 /* <= 6.2 seconds -> resolution = 0b00 [100 ms] */ in calculate_rt()
50 resolution = 0x00; in calculate_rt()
53 resolution = 0x00; in calculate_rt()
[all …]
/Zephyr-latest/drivers/sensor/nxp/fxls8974/
Dfxls8974.c19 #define DIR_READ(a) ((a) & 0x7f)
41 uint8_t reg_buf[3] = { DIR_READ(reg), ADDR_7(reg), 0 }; in fxls8974_read_spi()
57 uint8_t data[] = { DIR_READ(reg), ADDR_7(reg), 0}; in fxls8974_byte_read_spi()
83 if (fxls8974_byte_read_spi(dev, reg, &old_val) < 0) { in fxls8974_reg_field_update_spi()
196 case 0: in fxls8974_set_odr()
206 LOG_DBG("Set %s ODR to 0x%02x", (mode == FXLS8974_WAKE) ? "wake" : "sleep", odr); in fxls8974_set_odr()
235 return 0; in fxls8974_attr_set()
244 int ret = 0; in fxls8974_sample_fetch()
271 for (i = 0; i < FXLS8974_MAX_ACCEL_BYTES; i += 2) { in fxls8974_sample_fetch()
316 case 0b00: in fxls8974_get_accel_data()
[all …]
/Zephyr-latest/doc/services/device_mgmt/
Dsmp_protocol.rst32 |3 |2 |1 |0 |
34 |7|6|5|4|3|2|1|0|7|6|5|4|3|2|1|0|7|6|5|4|3|2|1|0|7|6|5|4|3|2|1|0|
63 | | always set to 0. |
66 | | used, this should be set to 0b01 to use the newer |
68 | | and returned in the map, otherwise left as 0b00 |
69 | | to use the legacy SMP protocol. Versions 0b10 and |
70 | | 0b11 are reserved for future use and should not |
79 | | yet, the field should be set to 0 |
120 | ``0`` | :ref:`mcumgr_smp_group_0` |
/Zephyr-latest/subsys/bluetooth/controller/hci/
Dhci_driver.c90 #define BT_HCI_EVT_FLAG_RECV_PRIO BIT(0)
140 return 0; in bt_recv_prio()
167 LL_ASSERT(0); in sink_sdu_alloc_hci()
178 const struct device *dev = DEVICE_DT_GET(DT_DRV_INST(0)); in sink_sdu_emit_hci()
211 * If Packet_Status_Flag equals 0b10 then PB_Flag shall equal 0b10. in sink_sdu_emit_hci()
212 * When Packet_Status_Flag is set to 0b10 in packets from the Controller to the in sink_sdu_emit_hci()
216 if (len > 0 && buf->len >= len) { in sink_sdu_emit_hci()
220 len = 0; in sink_sdu_emit_hci()
221 total_len = 0; in sink_sdu_emit_hci()
230 * 0b00 The ISO_Data_Load field contains a header and the first fragment in sink_sdu_emit_hci()
[all …]
Dhci.c100 #define STR_NULL_TERMINATOR 0x00
108 #if CONFIG_BT_CTLR_DUP_FILTER_LEN > 0
110 * 0 - Non-Connectable Non-Scannable advertising report
167 /* Set constant true so that (dup_count >= 0) decides if advertising duplicate
172 #endif /* CONFIG_BT_CTLR_DUP_FILTER_LEN > 0 */
203 /* In HCI event PHY indices start at 1 compare to 0 indexed in aux_ptr field in
208 #define DEFAULT_EVENT_MASK 0x1fffffffffff
209 #define DEFAULT_EVENT_MASK_PAGE_2 0x0
210 #define DEFAULT_LE_EVENT_MASK 0x1f
237 return 0; in ll_adv_cmds_set()
[all …]
/Zephyr-latest/arch/riscv/core/
Disr.S228 lw t2, 0(t0) /* t0 = mepc */
231 andi t0, t2, 0x7f /* keep only the opcode bits */
242 xori t1, t0, 0b1010011 /* OP-FP */
244 ori t1, t0, 0b0100000
245 xori t1, t1, 0b0100111 /* LOAD-FP / STORE-FP */
247 ori t1, t0, 0b0001100
248 xori t1, t1, 0b1001111 /* MADD / MSUB / NMSUB / NMADD */
255 * CSR format: csr#[31-20] src[19-15] op[14-12] dst[11-7] SYSTEM[6-0]
256 * SYSTEM = 0b1110011, op = 0b.xx where xx is never 0
259 xori t1, t0, 0b1110011 /* SYSTEM opcode */
[all …]
/Zephyr-latest/subsys/usb/device_next/class/
Dusbd_uac2_macros.h21 #define U16_LE(value) ((value) & 0xFF), (((value) & 0xFF00) >> 8)
23 ((value) & 0xFF), \
24 (((value) & 0xFF00) >> 8), \
25 (((value) & 0xFF0000) >> 16), \
26 (((value) & 0xFF000000) >> 24)
36 #define FIRST_INTERFACE_NUMBER 0x00
37 #define FIRST_IN_EP_ADDR 0x81
38 #define FIRST_OUT_EP_ADDR 0x01
44 #define FUNCTION_SUBCLASS_UNDEFINED 0x00
47 #define FUNCTION_PROTOCOL_UNDEFINED 0x00
[all …]
/Zephyr-latest/drivers/usb_c/tcpc/
Ducpd_stm32.c56 return (header.number_of_data_objects == 0 && in ucpd_msg_is_good_crc()
57 header.extended == 0 && in ucpd_msg_is_good_crc()
134 data->ucpd_tx_request = 0; in stm32_ucpd_state_init()
135 data->tx_retry_count = 0; in stm32_ucpd_state_init()
151 * @retval CC Enable mask (bit 0: CC1, bit 1: CC2)
177 * @retval 0 on success
198 * ANAMODE(src) = 0. in ucpd_get_cc()
204 * 0 -> 1 in ucpd_get_cc()
206 * 2 -> 0 in ucpd_get_cc()
254 return 0; in ucpd_get_cc()
[all …]
/Zephyr-latest/boards/snps/hsdk/doc/
Dindex.rst28 | 2:0 | GPIO_SEL_0 | RW | 0x0* | GPIO mux select for gpio[3:0] |
30 | 5:3 | GPIO_SEL_1 | RW | 0x0* | GPIO mux select for gpio[7:4] |
32 | 8:6 | GPIO_SEL_2 | RW | 0x0* | GPIO mux select for gpio[11:8] |
34 | 11:9 | GPIO_SEL_3 | RW | 0x0* | GPIO mux select for gpio[15:12] |
36 | 14:12 | GPIO_SEL_4 | RW | 0x0* | GPIO mux select for gpio[17:16] |
38 | 17:15 | GPIO_SEL_5 | RW | 0x0* | GPIO mux select for gpio[19:18] |
40 | 20:18 | GPIO_SEL_6 | RW | 0x0* | GPIO mux select for gpio[21:20] |
42 | 23:21 | GPIO_SEL_7 | RW | 0x0* | GPIO mux select for gpio[23:22] |
48 | SEL0 | 0 | gpio[0] | uart0_cts | spi1_cs[0] | gpio[0] | gpio[0] | pwm_ch[6] | pwm_c…
50 … | gpio[1] | uart0_txd | spi1_mosi | gpio[1] | pwm_ch[0] | gpio[1] | pwm_ch[0] | pwm_ch[0] …
[all …]
/Zephyr-latest/boards/snps/hsdk4xd/doc/
Dindex.rst25 | 2:0 | GPIO_SEL_0 | RW | 0x0 | GPIO mux select for gpio[3:0] |
27 | 5:3 | GPIO_SEL_1 | RW | 0x0 | GPIO mux select for gpio[7:4] |
29 | 8:6 | GPIO_SEL_2 | RW | 0x0 | GPIO mux select for gpio[11:8] |
31 | 11:9 | GPIO_SEL_3 | RW | 0x0 | GPIO mux select for gpio[15:12] |
33 | 14:12 | GPIO_SEL_4 | RW | 0x0 | GPIO mux select for gpio[17:16] |
35 | 17:15 | GPIO_SEL_5 | RW | 0x0 | GPIO mux select for gpio[19:18] |
37 | 20:18 | GPIO_SEL_6 | RW | 0x0 | GPIO mux select for gpio[21:20] |
39 | 23:21 | GPIO_SEL_7 | RW | 0x0 | GPIO mux select for gpio[23:22] |
45 | SEL0 | 0 | gpio[0] | uart0_cts | spi1_cs[0] | gpio[0] | gpio[0] | pwm_ch[6] | pwm_c…
47 … | gpio[1] | uart0_txd | spi1_mosi | gpio[1] | pwm_ch[0] | gpio[1] | pwm_ch[0] | pwm_ch[0] …
[all …]