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/nrf_hw_models-3.6.0/src/HW_models/
Dcrc.c17 return ((input * 0x80200802ULL) & 0x0884422110ULL) in rev_byte()
18 * 0x0101010101ULL >> 32; in rev_byte()
26 ret = rev_byte((input >> 0) & 0xff) << 16 in rev_24()
27 | rev_byte((input >> 8) & 0xff) << 8 in rev_24()
28 | rev_byte((input >> 16) & 0xff); in rev_24()
37 ret = rev_byte((input >> 0) & 0xff) << 8 in rev_16()
38 | rev_byte((input >> 8) & 0xff) << 0; in rev_16()
45 …Options="--std=C99 --width=24 --poly=0x100065B --algorithm=table-driven --xor-out=0x0 --xor-in=0x5…
51 0x000000, 0x01b4c0, 0x036980, 0x02dd40, 0x06d300, 0x0767c0, 0x05ba80, 0x040e40,
52 0x0da600, 0x0c12c0, 0x0ecf80, 0x0f7b40, 0x0b7500, 0x0ac1c0, 0x081c80, 0x09a840,
[all …]
DNRF_PPI.h15 //0 0x40000000 CLOCK
16 //0 0x40000000 POWER
33 //1 0x40001000 RADIO
60 // 2 0x40002000 UARTE
61 // 2 0x40002000 UART
74 // 3 0x40003000 TWIM
75 // 3 0x40003000 SPIS
76 // 3 0x40003000 SPIM
77 // 3 0x40003000 SPI
78 // 3 0x40003000 TWIS
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DNHW_config.h24 #define NHW_HAS_DPPI 0
28 #define NHW_AAR_0 0
29 #define NHW_AAR_INT_MAP {{0 , 15}} /*Only core,CCM_AAR_IRQn*/
33 #define NHW_CCM_0 0
34 #define NHW_CCM_INT_MAP {{0 , 15}} /*Only core,CCM_AAR_IRQn*/
37 #define NHW_CLKPWR_0 0
38 #define NHW_CLKPWR_INT_MAP {{0 , 0}} /*Only core, POWER_CLOCK_IRQn*/
39 #define NHW_CLKPWR_HAS_RESET 0
41 #define NHW_CLKPWR_HAS_HFCLKAUDIOCLK 0
42 #define NHW_CLKPWR_HAS_HFCLKAUDIOCLK_I {0}
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DNRF5340_peri_types.h39 …__IM uint32_t CONFIGID; /*!< (@ 0x00000000) Configuration identifier …
40 …__IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device i…
41 …__IM uint32_t PART; /*!< (@ 0x0000000C) Part code …
42 …__IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version a…
44 …__IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option …
45 …__IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant …
46 …__IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant …
47 …__IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size in bytes …
48 …__IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size …
49 …__IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type …
[all …]
DNHW_TEMP.c57 memset(&NRF_TEMP_regs, 0, sizeof(NRF_TEMP_regs)); in nhw_temp_init()
59 NRF_TEMP_regs.A0 = 0x00000326; in nhw_temp_init()
60 NRF_TEMP_regs.A1 = 0x00000348; in nhw_temp_init()
61 NRF_TEMP_regs.A2 = 0x000003AA; in nhw_temp_init()
62 NRF_TEMP_regs.A3 = 0x0000040E; in nhw_temp_init()
63 NRF_TEMP_regs.A4 = 0x000004BD; in nhw_temp_init()
64 NRF_TEMP_regs.A5 = 0x000005A3; in nhw_temp_init()
65 NRF_TEMP_regs.B0 = 0x00003FEF; in nhw_temp_init()
66 NRF_TEMP_regs.B1 = 0x00003FBE; in nhw_temp_init()
67 NRF_TEMP_regs.B2 = 0x00003FBE; in nhw_temp_init()
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DNHW_RADIO_timings.c43 radio_timings.TX_RU_time[0][1][0] = 41; // 41000 in nrfra_timings_init()
44 radio_timings.TX_RU_time[0][0][1] = 141; //141000 in nrfra_timings_init()
45 radio_timings.TX_RU_time[0][0][0] = 130; //130000 in nrfra_timings_init()
46 radio_timings.TX_RU_time[1][1][0] = 40; // 40000 in nrfra_timings_init()
47 radio_timings.TX_RU_time[1][0][1] = 140; //140000 in nrfra_timings_init()
48 radio_timings.TX_RU_time[1][0][0] = 129; //128900 in nrfra_timings_init()
49 radio_timings.TX_RU_time[2][1][0] = 40; // 40000 in nrfra_timings_init()
50 radio_timings.TX_RU_time[2][0][1] = 130; //130000 - Is this correct? or should it be 169us? in nrfra_timings_init()
51 radio_timings.TX_RU_time[2][0][0] = 129; //128900 ?? just copied from Ble 1Mbps in nrfra_timings_init()
54 radio_timings.RX_RU_time[0][1][0] = 40; // 40000 in nrfra_timings_init()
[all …]
DNHW_53_FICR.c35 memset(&NRF_FICR_APP_regs, 0xFF, sizeof(NRF_FICR_APP_regs)); in nhw_53_ficr_init()
36 memset(&NRF_FICR_NET_regs, 0xFF, sizeof(NRF_FICR_NET_regs)); in nhw_53_ficr_init()
38 …NRF_FICR_APP_regs.INFO.DEVICEID[0] = (bs_random_uint32() & 0xFFFFFF00) + bsim_args_get_global_devi… in nhw_53_ficr_init()
40 NRF_FICR_APP_regs.INFO.PART = 0x5340; in nhw_53_ficr_init()
41 NRF_FICR_APP_regs.INFO.FLASH = 0x400; /*1 MB*/ in nhw_53_ficr_init()
42 NRF_FICR_APP_regs.INFO.CODEPAGESIZE = 0x1000; in nhw_53_ficr_init()
44 NRF_FICR_APP_regs.INFO.DEVICETYPE = 0; in nhw_53_ficr_init()
46 NRF_FICR_NET_regs.INFO.DEVICEID[0] = NRF_FICR_APP_regs.INFO.DEVICEID[0]; in nhw_53_ficr_init()
48 NRF_FICR_NET_regs.INFO.PART = 0x5340; in nhw_53_ficr_init()
49 NRF_FICR_NET_regs.INFO.FLASH = 0x100; /*256 KB*/ in nhw_53_ficr_init()
[all …]
DNRF_PPI.c55 void nrf_ppi_TASK_CHG0_EN(void) { nrf_ppi_TASK_CHG_ENDIS(0,true); } in nrf_ppi_TASK_CHG0_EN()
61 void nrf_ppi_TASK_CHG0_DIS(void) { nrf_ppi_TASK_CHG_ENDIS(0,false); } in nrf_ppi_TASK_CHG0_DIS()
94 { (void*)&NRF_CLKPWR_regs[0].CLK.TASKS_LFCLKSTART , nhw_clock0_TASKS_LFCLKSTART},
95 { (void*)&NRF_CLKPWR_regs[0].CLK.TASKS_LFCLKSTOP , nhw_clock0_TASKS_LFCLKSTOP},
96 { (void*)&NRF_CLKPWR_regs[0].CLK.TASKS_HFCLKSTART , nhw_clock0_TASKS_HFCLKSTART},
97 { (void*)&NRF_CLKPWR_regs[0].CLK.TASKS_HFCLKSTOP , nhw_clock0_TASKS_HFCLKSTOP},
98 { (void*)&NRF_CLKPWR_regs[0].CLK.TASKS_CAL , nhw_clock0_TASKS_CAL},
99 { (void*)&NRF_CLKPWR_regs[0].CLK.TASKS_CTSTART , nhw_clock0_TASKS_CTSTART},
100 { (void*)&NRF_CLKPWR_regs[0].CLK.TASKS_CTSTOP , nhw_clock0_TASKS_CTSTOP},
118 { (void*)&NRF_UARTE_regs[0].TASKS_STARTRX, nhw_uarte0_TASKS_STARTRX},
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DNRF_GPIO.c19 * Reading OUTCLR & DIRCLR reads always 0
60 static uint32_t INPUT_mask[NRF_GPIOS]; /* As a 32bit mask, PIN_CNF[*].INPUT (0: enabled; 1: disable…
61 static uint32_t SENSE_mask[NRF_GPIOS]; /* As a 32bit mask, PIN_CNF[*].SENSE.en (1: enabled; 0: disa…
62 static uint32_t SENSE_inv[NRF_GPIOS]; /* As a 32bit mask, PIN_CNF[*].SENSE.inv (1: inverted;0: not…
65 * Is the output driven by another peripheral (1) or the GPIO directly (0).
72 /* Is the pin input controlled by a peripheral(1) or the GPIO(0) */
74 …ut_override, is the peripheral configuring the input buffer as connected (1) or disconnected (0) */
77 /* Is "dir" controlled by a peripheral(1) or the GPIO(0) */
79 …r_override is set, is the peripheral configuring the output as connected (1) or disconnected (0) */
90 memset(NRF_GPIO_regs, 0, sizeof(NRF_GPIO_regs)); in nrf_gpio_init()
[all …]
DNHW_52_FICR.c31 memset(&NRF_FICR_regs, 0xFF, sizeof(NRF_FICR_regs)); in nhw_52_ficr_init()
40 NRF_FICR_regs.DEVICEID[0] = (bs_random_uint32() & 0xFFFFFF00) + bsim_args_get_global_device_nbr(); in nhw_52_ficr_init()
42 NRF_FICR_regs.DEVICEADDRTYPE = 0; in nhw_52_ficr_init()
43 NRF_FICR_regs.DEVICEADDR[0] = bs_random_uint32(); in nhw_52_ficr_init()
46 for (int i = 0 ; i < 4; i++) { in nhw_52_ficr_init()
51 NRF_FICR_regs.INFO.PART = 0x52833; in nhw_52_ficr_init()
52 NRF_FICR_regs.INFO.VARIANT = 0x41414230; in nhw_52_ficr_init()
53 NRF_FICR_regs.PRODTEST[0] = 0xBB42319F; in nhw_52_ficr_init()
54 NRF_FICR_regs.PRODTEST[1] = 0xBB42319F; in nhw_52_ficr_init()
55 NRF_FICR_regs.PRODTEST[2] = 0xBB42319F; in nhw_52_ficr_init()
DNHW_RADIO_utils.c45 | (0 << RADIO_PCNF1_STATLEN_Pos); in nrfra_check_pcnf1_ble()
63 | ( 0 << RADIO_PCNF0_S1LEN_Pos ) in nrfra_check_ble1M_conf()
86 | ( 0 << RADIO_PCNF0_S1LEN_Pos ) in nrfra_check_ble2M_conf()
114 //TERM = 0 in nrfra_check_802154_conf()
117 //CILEN = 0 in nrfra_check_802154_conf()
118 //S1INCL = 0 in nrfra_check_802154_conf()
119 | ( 0 << RADIO_PCNF0_S1LEN_Pos ) in nrfra_check_802154_conf()
120 | ( 0 << RADIO_PCNF0_S0LEN_Pos ) in nrfra_check_802154_conf()
135 check = (0 << RADIO_PCNF1_WHITEEN_Pos) in nrfra_check_802154_conf()
137 | (0 << RADIO_PCNF1_BALEN_Pos) // => 1 byte for SFD in nrfra_check_802154_conf()
[all …]
DNHW_TIMER.c16 * * INTENCLR will always read as 0
88 memset(NRF_TIMER_regs, 0, sizeof(NRF_TIMER_regs)); in nhw_timer_init()
90 for (int t = 0; t < NHW_TIMER_TOTAL_INST ; t++) { in nhw_timer_init()
95 t_st->INTEN = 0; in nhw_timer_init()
98 t_st->Counter = 0; in nhw_timer_init()
105 for (int cc = 0; cc < t_st->n_CCs ; cc++) { in nhw_timer_init()
124 for (int t = 0; t< NHW_TIMER_TOTAL_INST; t++) { in nhw_timer_free()
167 case 0: in mask_from_bitmode()
168 return 0xFFFF; in mask_from_bitmode()
171 return 0xFF; in mask_from_bitmode()
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DNHW_NVMC.c34 * writes to them are ignored, reads read 0 (or whatever was written to them last)
87 NRF_NVMC_Type NRF_NVMC_regs[NHW_NVMC_UICR_TOTAL_INST] = {0};
90 enum flash_op_t {flash_idle = 0, flash_write, flash_erase, flash_erase_partial, flash_erase_uicr, f…
118 Timer_NVMC = hw_nvmc_st[0].timer; in nhw_nvmc_find_next_event()
138 memset(NRF_NVMC_regs, 0x00, sizeof(NRF_NVMC_regs)); in nhw_nvmc_uicr_init()
140 for (int inst = 0; inst < NHW_NVMC_UICR_TOTAL_INST; inst++) { in nhw_nvmc_uicr_init()
147 NRF_NVMC_regs[inst].ERASEPAGEPARTIALCFG = 0x0000000A; in nhw_nvmc_uicr_init()
171 for (int i = 0; i < this->flash_size; i+=4) { in nhw_nvmc_uicr_init()
172 if (*(uint32_t*)(this->flash_st.storage + i) != 0) { in nhw_nvmc_uicr_init()
190 for (int inst = 0; inst < NHW_NVMC_UICR_TOTAL_INST; inst++) { in nhw_nvmc_uicr_clean_up()
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DNHW_EGU.c56 memset(NRF_EGU_regs, 0, sizeof(NRF_EGU_Type) * NHW_EGU_TOTAL_INST); in nhw_egu_init()
58 for (int i = 0; i< NHW_EGU_TOTAL_INST; i++) { in nhw_egu_init()
77 for (int i = 0; i< NHW_EGU_TOTAL_INST; i++) { in nhw_egu_free()
102 for (int i = 0; i < this->n_events; i++) { in nhw_egu_eval_interrupt()
161 uint n = (uintptr_t)param & 0xFFFF; in nhw_egu_tasktrigger_wrap()
193 EGU_regs->INTENCLR = 0; //We do not model reading the INTEN register thru the INTENCLR one in nhw_egu_regw_sideeffect_INTENCLR()
213 if (NRF_EGU_regs[inst].TASKS_TRIGGER[task_nbr] != 0) { in nhw_egu_regw_sideeffects_TASK_TRIGGER()
214 NRF_EGU_regs[inst].TASKS_TRIGGER[task_nbr] = 0; in nhw_egu_regw_sideeffects_TASK_TRIGGER()
226 for inst in range(0,6):
227 for i in range(0,16):
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DNHW_AES_CCM.c60 memset(&NRF_CCM_regs, 0, sizeof(NRF_CCM_regs)); in nhw_aes_ccm_init()
61 NRF_CCM_regs.MODE = 0x01; in nhw_aes_ccm_init()
62 NRF_CCM_regs.HEADERMASK= 0xE3; in nhw_aes_ccm_init()
63 NRF_CCM_regs.MAXPACKETSIZE = 0xFB; in nhw_aes_ccm_init()
64 CCM_INTEN = 0; in nhw_aes_ccm_init()
90 nhw_CCM_signal_EVENTS_ENDKSGEN(0); in NHW_SIGNAL_EVENT_si()
105 uint8_t packet_direction, // Direction of packet (1:master to slave, 0: slave to master) in nonce_calc()
112 for (i = 0; i < NONCE_LEN - IV_LEN - 1; i++) in nonce_calc()
114 ccm_nonce[i] = packet_counter & 0xFF; in nonce_calc()
117 ccm_nonce[i] = (packet_counter & 0x7F) | (packet_direction == 1 /*master to slave*/ ? 0x80 : 0); in nonce_calc()
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DNHW_AAR.c54 static uint32_t AAR_INTEN = 0; //interrupt enable
59 memset(&NRF_AAR_regs, 0, sizeof(NRF_AAR_regs)); in nhw_aar_init()
60 AAR_INTEN = 0; in nhw_aar_init()
91 if (NRF_AAR_regs.ENABLE != 0x3) { in NHW_SIGNAL_EVENT_si()
110 nhw_AAR_signal_EVENTS_END(0); in nhw_AAR_TASK_STOP()
135 nhw_AAR_signal_EVENTS_RESOLVED(0); in NHW_SIDEEFFECTS_EVENTS()
137 nhw_AAR_signal_EVENTS_NOTRESOLVED(0); in NHW_SIDEEFFECTS_EVENTS()
139 nhw_AAR_signal_EVENTS_END(0); in NHW_SIDEEFFECTS_EVENTS()
145 uint32_t value = ptr[0] | (ptr[1] << 8) | (ptr[2] << 16); in read_3_bytes_value()
174 address_ptr[2], address_ptr[1], address_ptr[0]); in nhw_aar_resolve()
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DNHW_MUTEX.c28 memset(NRF_MUTEX_regs.MUTEX, 0, sizeof(NRF_MUTEX_regs.MUTEX)); in nhw_mutex_init()
29 memset(MUTEX_state, 0, sizeof(MUTEX_state)); in nhw_mutex_init()
35 * Handle the sideeffects of writing a 0 to the MUTEX register
38 MUTEX_state[n] = 0; in nhw_MUTEX_regw_sideeffects_MUTEX()
39 NRF_MUTEX_regs.MUTEX[n] = 0; in nhw_MUTEX_regw_sideeffects_MUTEX()
47 if (MUTEX_state[n] == 0) { in nhw_MUTEX_regr_sideeffects_MUTEX()
50 return 0; in nhw_MUTEX_regr_sideeffects_MUTEX()
/nrf_hw_models-3.6.0/docs/
DGPIO.md9 * Consider the output drivers to have 0 impedance: The drive is instantaneous.
39 * Port is the GPIO port number starting from 0 (for a nrf52833: 0 or 1).
40 * Pin is the pin number in that port (for a nrf52833: 0..31 for port 0, and 0..9 for port 1)
41 * Level is either 0 (for low) or 1 (for high)
47 0,0,0,1
48 200,0,0,0
49 600,0,0,1
50 800,0,0,0
51 1000,0,0,1
52 1000,0,0,0
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DRADIO_states.svg4 …0 Safari/537.36&quot; etag=&quot;cvx4YFSa83dn7WEUVjmV&quot; version=&quot;20.8.16&quot; type=&quot…
/nrf_hw_models-3.6.0/src/nrfx/hal/
Dnrf_ccm.c15 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; in nrf_ccm_task_trigger()
42 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; in nrf_ccm_event_clear()
43 nhw_CCM_regw_sideeffects_EVENTS_all(0); in nrf_ccm_event_clear()
52 nhw_CCM_regw_sideeffects_SUBSCRIBE_KSGEN(0); in nrf_ccm_subscribe_common()
54 nhw_CCM_regw_sideeffects_SUBSCRIBE_CRYPT(0); in nrf_ccm_subscribe_common()
56 nhw_CCM_regw_sideeffects_SUBSCRIBE_STOP(0); in nrf_ccm_subscribe_common()
58 nhw_CCM_regw_sideeffects_SUBSCRIBE_RATEOVERRIDE(0); in nrf_ccm_subscribe_common()
69 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = in nrf_ccm_subscribe_set()
77 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0; in nrf_ccm_subscribe_clear()
Dnrf_temp.c14 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)temp_task)) = 0x1UL; in nrf_temp_task_trigger()
39 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; in nrf_temp_event_clear()
40 nhw_TEMP_regw_sideeffects_EVENTS_all(0); in nrf_temp_event_clear()
49 nhw_TEMP_regw_sideeffects_SUBSCRIBE_START(0); in nrf_temp_subscribe_common()
51 nhw_TEMP_regw_sideeffects_SUBSCRIBE_STOP(0); in nrf_temp_subscribe_common()
62 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = in nrf_temp_subscribe_set()
70 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0; in nrf_temp_subscribe_clear()
Dnrf_rng.c16 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)rng_task)) = 0x1UL; in nrf_rng_task_trigger()
41 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)rng_event)) = 0x0UL; in nrf_rng_event_clear()
42 nhw_RNG_regw_sideeffects_EVENTS_all(0); in nrf_rng_event_clear()
51 nhw_RNG_regw_sideeffects_SUBSCRIBE_START(0); in nrf_rng_subscribe_common()
53 nhw_RNG_regw_sideeffects_SUBSCRIBE_STOP(0); in nrf_rng_subscribe_common()
64 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = in nrf_rng_subscribe_set()
72 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0; in nrf_rng_subscribe_clear()
Dnrf_ecb.c14 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; in nrf_ecb_task_trigger()
39 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; in nrf_ecb_event_clear()
40 nhw_ECB_regw_sideeffects_EVENTS_all(0); in nrf_ecb_event_clear()
49 nhw_ECB_regw_sideeffects_SUBSCRIBE_STARTECB(0); in nrf_ecb_subscribe_common()
51 nhw_ECB_regw_sideeffects_SUBSCRIBE_STOPECB(0); in nrf_ecb_subscribe_common()
62 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = in nrf_ecb_subscribe_set()
70 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0; in nrf_ecb_subscribe_clear()
Dnrf_hack.c44 * [0x000..0x080) are tasks in nrf_dppi_hack_is_task()
45 * [0x080..0x100) are subscribe registers in nrf_dppi_hack_is_task()
46 * [0x100..0x180) are events in nrf_dppi_hack_is_task()
47 * [0x180..0x200) are publish registers in nrf_dppi_hack_is_task()
49 if (task_event < 0x100) { in nrf_dppi_hack_is_task()
83 } else IF_PER(TIMER, 0, _NS, timer)
89 } else IF_PER(RTC, 0, _NS, rtc)
92 } else IF_PER(EGU, 0, _NS, egu)
111 } else IF_PER(SPIM, 0, _NS, spi)
116 } else IF_PER(GPIOTE, 0, _S, gpiote)
[all …]
/nrf_hw_models-3.6.0/src/nrfx/drivers/
Dnrfx_common.c33 } else if (IS_PERIPHERAL_REG(p_reg, UARTE, 0,)) { in nrfx_get_irq_number()
39 } else if (IS_PERIPHERAL_REG(p_reg, TIMER, 0,)) { in nrfx_get_irq_number()
45 } else if (IS_PERIPHERAL_REG(p_reg, RTC, 0,)) { in nrfx_get_irq_number()
61 } else if (IS_PERIPHERAL_REG(p_reg, EGU, 0,)) { in nrfx_get_irq_number()
81 return 0x1F; in nrfx_get_irq_number()
88 return 0; /* unreachable */ in nrfx_get_irq_number()
105 } else if (IS_PERIPHERAL_REG(p_reg, TIMER, 0, _NS)) { in nrfx_get_irq_number()
115 } else if (IS_PERIPHERAL_REG(p_reg, RTC, 0, _NS)) { in nrfx_get_irq_number()
119 } else if (IS_PERIPHERAL_REG(p_reg, UARTE, 0, _NS)) { in nrfx_get_irq_number()
121 } else if (IS_PERIPHERAL_REG(p_reg, EGU, 0, _NS)) { in nrfx_get_irq_number()
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