| /cmsis-dsp-latest/dsppp/Include/dsppp/ |
| D | fixed_point.hpp | 1 // -*- C++ -*-
24 to CMSIS-DSP and only to allow the use of this library from other
27 MSVC is not going to be used to cross-compile to ARM. So, having a MSVC
51 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); in __SSAT()
52 const int32_t min = -1 - max ; in __SSAT()
69 const uint32_t max = ((1U << sat) - 1U); in __USAT()
106 return ((int32_t)(clip_int64_to_q31((int64_t)x - (int32_t)y))); in __QSUB()
116 * @param M number of mantissa bit (without sign bit)
121 constexpr bool test64(const int M,const int F,const int S){return((M+F+S)>32 && (M+F+S)<=64);} in test64() argument
127 * @param M number of mantissa bit (without sign bit)
[all …]
|
| D | algorithms.hpp | 1 // -*- C++ -*-
6 * C++ template extension to CMSIS-DSP. It is not yet part of
8 * [CMSIS-DSP github](https://github.com/ARM-software/CMSIS-DSP/tree/main/dsppp/Include)
119 * @tparam M Any matrix type
121 * @param m matrix.
126 template<typename M,
128 typename std::enable_if<CompatibleStaticMatVecProduct<M,V>::value,bool>::type = true>
129 inline typename OutputVector<M,V>::type dot(const M&m,const V&v) in dot() argument
131 typename OutputVector<M,V>::type res; in dot()
132 _dot_m_v(res,m,v,CURRENT_ARCH); in dot()
[all …]
|
| D | forward.hpp | 1 // -*- C++ -*-
30 template<typename M>
33 template<typename M>
36 template<typename M,typename V>
39 template<typename M,typename V>
42 template<typename M,typename V>
45 template<typename M,typename V>
48 template<typename M,typename V>
51 template<typename M,typename V>
54 template<typename M,typename V>
|
| /cmsis-dsp-latest/Include/dsp/ |
| D | debug.h | 6 * Target Processor: Cortex-M and Cortex-A cores
9 * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
11 * SPDX-License-Identifier: Apache-2.0
17 * www.apache.org/licenses/LICENSE-2.0
64 #define PM_f16(S,M) \ argument
67 for(unsigned int row=0;row<(M)->numRows;row++) \
73 PROW_f16((M)->pData + row * (M)->numCols, (M)->numCols);\
97 #define PM_f32(S,M) \ argument
100 for(unsigned int row=0;row<(M)->numRows;row++) \
106 PROW_f32((M)->pData + row * (M)->numCols, (M)->numCols);\
[all …]
|
| /cmsis-dsp-latest/Testing/PatternGeneration/ |
| D | QR.py | 34 c = math.sqrt(1-s*s)
35 m = np.zeros((rows,cols))
38 for i in range(rows-1):
39 m[i,i] = sc
40 m[i,i+1:] = - sc * c * np.ones(rows-i-1)
43 m = m + m.T
45 return(m)
47 def householder(x,eps=1e-16):
64 beta = -math.sqrt(alpha*alpha + xnorm2)
66 r = (alpha - beta)
[all …]
|
| /cmsis-dsp-latest/dsppp/Include/dsppp/Scalar/ |
| D | matrix_multiply.hpp | 1 // -*- C++ -*-
37 * @param[in] m Matrix
40 * @tparam M Matrix datatype
44 template<typename M,
48 const M&m,const V&v, in _dot_m_v() argument
51 using T = typename traits<M>::Scalar; in _dot_m_v()
53 uint32_t numRows = m.rows(); in _dot_m_v()
54 uint32_t numCols = m.columns(); in _dot_m_v()
55 const T *pSrcA = m.ptr(); in _dot_m_v()
71 /* The following loop performs the dot-product of each row in pSrcA with the vector */ in _dot_m_v()
[all …]
|
| /cmsis-dsp-latest/Source/FilteringFunctions/ |
| D | arm_fir_decimate_f32.c | 1 /* ----------------------------------------------------------------------
4 * Description: FIR decimation for floating-point sequences
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
42 …When decimating by a factor of <code>M</code>, the signal should be prefiltered by a lowpass filte…
43 cutoff frequency of <code>1/M</code> in order to prevent aliasing distortion.
47 …lculating all of the FIR filter outputs and discarding <code>M-1</code> out of every <code>M</code…
[all …]
|
| D | arm_fir_decimate_q15.c | 1 /* ----------------------------------------------------------------------
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
48 The function is implemented using a 64-bit internal accumulator.
50 … The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
69 q15_t *pState = S->pState; /* State pointer */ in arm_fir_decimate_q15()
70 const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ in arm_fir_decimate_q15()
[all …]
|
| D | arm_fir_decimate_init_f32.c | 1 /* ----------------------------------------------------------------------
4 * Description: Floating-point FIR Decimator initialization function
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
41 @brief Initialization function for the floating-point FIR decimator.
42 @param[in,out] S points to an instance of the floating-point FIR decimator structure
44 @param[in] M decimation factor
[all …]
|
| D | arm_fir_decimate_init_f64.c | 1 /* ----------------------------------------------------------------------
4 * Description: Floating-point FIR Decimator initialization function
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2024 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
41 @brief Initialization function for the floating-point FIR decimator.
42 @param[in,out] S points to an instance of the floating-point FIR decimator structure
44 @param[in] M decimation factor
[all …]
|
| D | arm_fir_decimate_init_q15.c | 1 /* ----------------------------------------------------------------------
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
44 @param[in] M decimation factor
49 - \ref ARM_MATH_SUCCESS : Operation successful
50 … - \ref ARM_MATH_LENGTH_ERROR : <code>blockSize</code> is not a multiple of <code>M</code>
55 {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
[all …]
|
| D | arm_fir_decimate_init_q31.c | 1 /* ----------------------------------------------------------------------
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
44 @param[in] M decimation factor
49 - \ref ARM_MATH_SUCCESS : Operation successful
50 … - \ref ARM_MATH_LENGTH_ERROR : <code>blockSize</code> is not a multiple of <code>M</code>
55 {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
[all …]
|
| /cmsis-dsp-latest/Source/MatrixFunctions/ |
| D | arm_mat_add_f32.c | 1 /* ----------------------------------------------------------------------
4 * Description: Floating-point matrix addition
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
73 @brief Floating-point matrix addition.
78 - \ref ARM_MATH_SUCCESS : Operation successful
79 - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
[all …]
|
| D | arm_mat_sub_f32.c | 1 /* ----------------------------------------------------------------------
4 * Description: Floating-point matrix subtraction
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
47 -
55 a_{1,1}-b_{1,1} & a_{1,2}-b_{1,2} & a_{1,3}-b_{1,3} \\
56 a_{2,1}-b_{2,1} & a_{2,2}-b_{2,2} & a_{2,3}-b_{2,3} \\
[all …]
|
| D | arm_mat_sub_f16.c | 1 /* ----------------------------------------------------------------------
4 * Description: Floating-point matrix subtraction
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
45 @brief Floating-point matrix subtraction.
50 - \ref ARM_MATH_SUCCESS : Operation successful
51 - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
[all …]
|
| D | arm_mat_add_f16.c | 1 /* ----------------------------------------------------------------------
4 * Description: Floating-point matrix addition
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
46 @brief Floating-point matrix addition.
51 - \ref ARM_MATH_SUCCESS : Operation successful
52 - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
[all …]
|
| D | arm_mat_sub_q31.c | 1 /* ----------------------------------------------------------------------
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
46 - \ref ARM_MATH_SUCCESS : Operation successful
47 - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
67 pDataA = pSrcA->pData; in arm_mat_sub_q31()
68 pDataB = pSrcB->pData; in arm_mat_sub_q31()
[all …]
|
| D | arm_mat_add_q31.c | 1 /* ----------------------------------------------------------------------
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
46 - \ref ARM_MATH_SUCCESS : Operation successful
47 - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
67 pDataA = pSrcA->pData; in arm_mat_add_q31()
68 pDataB = pSrcB->pData; in arm_mat_add_q31()
[all …]
|
| D | arm_mat_sub_q15.c | 1 /* ----------------------------------------------------------------------
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
46 - \ref ARM_MATH_SUCCESS : Operation successful
47 - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
69 pDataA = pSrcA->pData; in arm_mat_sub_q15()
70 pDataB = pSrcB->pData; in arm_mat_sub_q15()
[all …]
|
| D | arm_mat_add_q15.c | 1 /* ----------------------------------------------------------------------
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
46 - \ref ARM_MATH_SUCCESS : Operation successful
47 - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
68 pDataA = pSrcA->pData; in arm_mat_add_q15()
69 pDataB = pSrcB->pData; in arm_mat_add_q15()
[all …]
|
| /cmsis-dsp-latest/dsppp/Include/dsppp/DSP/ |
| D | matrix_multiply.hpp | 1 // -*- C++ -*-
83 col--; in _arm_mat_trans()
87 col = nCols & (2*nb_lanes-1); in _arm_mat_trans()
97 col--; in _arm_mat_trans()
100 pIn += (src.stride()-nCols); in _arm_mat_trans()
105 row--; in _arm_mat_trans()
114 template<typename M,
118 !std::is_same<typename traits<M>::Scalar,Q31>::value &&
119 number_traits<typename traits<M>::Scalar>::is_fixed,bool>::type = true>
121 const M&m,const V&v, in _dot_m_v() argument
[all …]
|
| /cmsis-dsp-latest/Include/ |
| D | arm_vec_math_f16.h | 6 * Target Processor: Cortex-M and Cortex-A cores
9 * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
11 * SPDX-License-Identifier: Apache-2.0
17 * www.apache.org/licenses/LICENSE-2.0
50 q15x8_t m; in vrecip_medprec_f16() local
57 m = 0x03c00 - (xinv.i & 0x07c00); in vrecip_medprec_f16()
58 xinv.i = xinv.i + m; in vrecip_medprec_f16()
59 xinv.f = 1.41176471f16 - 0.47058824f16 * xinv.f; in vrecip_medprec_f16()
60 xinv.i = xinv.i + m; in vrecip_medprec_f16()
62 b = 2.0f16 - xinv.f * ax; in vrecip_medprec_f16()
[all …]
|
| D | arm_vec_math.h | 6 * Target Processor: Cortex-M and Cortex-A cores
9 * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
11 * SPDX-License-Identifier: Apache-2.0
17 * www.apache.org/licenses/LICENSE-2.0
49 q31x4_t m; in vrecip_medprec_f32() local
55 m = 0x3F800000 - (xinv.i & 0x7F800000); in vrecip_medprec_f32()
56 xinv.i = xinv.i + m; in vrecip_medprec_f32()
57 xinv.f = 1.41176471f - 0.47058824f * xinv.f; in vrecip_medprec_f32()
58 xinv.i = xinv.i + m; in vrecip_medprec_f32()
60 b = 2.0f - xinv.f * ax; in vrecip_medprec_f32()
[all …]
|
| /cmsis-dsp-latest/Source/TransformFunctions/ |
| D | arm_mfcc_q15.c | 1 /* ----------------------------------------------------------------------
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
81 q15_t m; in arm_mfcc_q15() local
95 arm_absmax_q15(pSrc,S->fftLen,&m,&index); in arm_mfcc_q15()
97 if ((m != 0) && (m != 0x7FFF)) in arm_mfcc_q15()
102 status = arm_divide_q15(0x7FFF,m,"ient,&shift); in arm_mfcc_q15()
[all …]
|
| D | arm_mfcc_q31.c | 1 /* ----------------------------------------------------------------------
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
82 q31_t m; in arm_mfcc_q31() local
96 arm_absmax_q31(pSrc,S->fftLen,&m,&index); in arm_mfcc_q31()
98 if ((m != 0) && (m != 0x7FFFFFFF)) in arm_mfcc_q31()
103 status = arm_divide_q31(0x7FFFFFFF,m,"ient,&shift); in arm_mfcc_q31()
[all …]
|
