| /cmsis-dsp-latest/Source/CommonTables/ |
| D | arm_common_tables_f16.c | 1 /* ----------------------------------------------------------------------
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
41 @brief Floating-point Twiddle factors Table Generation
54 * Example code for Floating-point Twiddle factors Generation:
68 (float16_t)1.000000000f, (float16_t)0.000000000f,
69 (float16_t)0.923879533f, (float16_t)0.382683432f,
[all …]
|
| D | arm_mve_tables_f16.c | 1 /* ----------------------------------------------------------------------
10 * Target Processor: Cortex-M and Cortex-A cores
11 * -------------------------------------------------------------------- */
13 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
15 * SPDX-License-Identifier: Apache-2.0
21 * www.apache.org/licenses/LICENSE-2.0
49 (float16_t)1.0000000000000f,(float16_t)0.0000000000000f,
50 (float16_t)0.9238281250000f,(float16_t)0.3825683593750f,
51 (float16_t)0.7070312500000f,(float16_t)0.7070312500000f,
52 (float16_t)0.3825683593750f,(float16_t)0.9238281250000f,};
[all …]
|
| D | arm_mve_tables.c | 1 /* ----------------------------------------------------------------------
10 * Target Processor: Cortex-M and Cortex-A cores
11 * -------------------------------------------------------------------- */
13 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
15 * SPDX-License-Identifier: Apache-2.0
21 * www.apache.org/licenses/LICENSE-2.0
49 1.00000000000000000000f,0.00000000000000000000f,0.92387950420379638672f,
50 0.38268342614173889160f,0.70710676908493041992f,0.70710676908493041992f,
51 0.38268342614173889160f,0.92387950420379638672f,};
54 1.00000000000000000000f,0.00000000000000000000f,0.70710676908493041992f,
[all …]
|
| D | arm_common_tables.c | 1 /* ----------------------------------------------------------------------
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
54 y[l] += (1 << ((logN2 - 1) - j));
174 @brief Double Precision Floating-point Twiddle factors Table Generation
179 Example code for Double Precision Floating-point Twiddle factors Generation:
197 0xbfd87de2a6aea963, 0x3fed906bcf328d46, //-0.38268, 0.92388'
[all …]
|
| /cmsis-dsp-latest/Examples/ARM/arm_fir_example/ |
| D | arm_fir_data.c | 1 /* ----------------------------------------------------------------------
2 * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
17 * - Redistributions of source code must retain the above copyright
19 * - Redistributions in binary form must reproduce the above copyright
23 * - Neither the name of ARM LIMITED nor the names of its contributors
39 * -------------------------------------------------------------------- */
43 /* ----------------------------------------------------------------------
45 ** ------------------------------------------------------------------- */
49 +0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.…
[all …]
|
| D | arm_fir_example_f32.c | 1 /* ----------------------------------------------------------------------
2 * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
13 * Target Processor: Cortex-M4/Cortex-M3
18 * - Redistributions of source code must retain the above copyright
20 * - Redistributions in binary form must reproduce the above copyright
24 * - Neither the name of ARM LIMITED nor the names of its contributors
40 * -------------------------------------------------------------------- */
52 * it in a block-by-block fashion.
108 * - arm_fir_init_f32()
109 * - arm_fir_f32()
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| /cmsis-dsp-latest/Testing/Include/Tests/ |
| D | mfccdata.c | 5 0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,
6 0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,
7 0.315253f,0.307490f,0.292156f,0.269628f,0.240461f,0.205374f,0.165229f,0.121015f,0.073822f,0.024811f,
8 -0.024811f,-0.073822f,-0.121015f,-0.165229f,-0.205374f,-0.240461f,-0.269628f,-0.292156f,-0.307490f,…
9 0.312334f,0.281761f,0.223607f,0.143564f,0.049469f,-0.049469f,-0.143564f,-0.223607f,-0.281761f,-0.31…
10 -0.312334f,-0.281761f,-0.223607f,-0.143564f,-0.049469f,0.049469f,0.143564f,0.223607f,0.281761f,0.31…
11 0.307490f,0.240461f,0.121015f,-0.024811f,-0.165229f,-0.269628f,-0.315253f,-0.292156f,-0.205374f,-0.…
12 0.073822f,0.205374f,0.292156f,0.315253f,0.269628f,0.165229f,0.024811f,-0.121015f,-0.240461f,-0.3074…
13 0.300750f,0.185874f,0.000000f,-0.185874f,-0.300750f,-0.300750f,-0.185874f,-0.000000f,0.185874f,0.30…
14 0.300750f,0.185874f,0.000000f,-0.185874f,-0.300750f,-0.300750f,-0.185874f,-0.000000f,0.185874f,0.30…
[all …]
|
| /cmsis-dsp-latest/Testing/Source/Tests/ |
| D | mfccdata_f16.c | 5 …f,(float16_t)0.316228f,(float16_t)0.316228f,(float16_t)0.316228f,(float16_t)0.316228f,(float16_t)0…
6 …f,(float16_t)0.316228f,(float16_t)0.316228f,(float16_t)0.316228f,(float16_t)0.316228f,(float16_t)0…
7 …f,(float16_t)0.307490f,(float16_t)0.292156f,(float16_t)0.269628f,(float16_t)0.240461f,(float16_t)0…
8 …-0.024811f,(float16_t)-0.073822f,(float16_t)-0.121015f,(float16_t)-0.165229f,(float16_t)-0.205374f…
9 …f,(float16_t)0.281761f,(float16_t)0.223607f,(float16_t)0.143564f,(float16_t)0.049469f,(float16_t)-…
10 …-0.312334f,(float16_t)-0.281761f,(float16_t)-0.223607f,(float16_t)-0.143564f,(float16_t)-0.049469f…
11 …f,(float16_t)0.240461f,(float16_t)0.121015f,(float16_t)-0.024811f,(float16_t)-0.165229f,(float16_t…
12 …f,(float16_t)0.205374f,(float16_t)0.292156f,(float16_t)0.315253f,(float16_t)0.269628f,(float16_t)0…
13 …f,(float16_t)0.185874f,(float16_t)0.000000f,(float16_t)-0.185874f,(float16_t)-0.300750f,(float16_t…
14 …f,(float16_t)0.185874f,(float16_t)0.000000f,(float16_t)-0.185874f,(float16_t)-0.300750f,(float16_t…
[all …]
|
| D | mfccdata.c | 5 0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,
6 0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,0.316228f,
7 0.315253f,0.307490f,0.292156f,0.269628f,0.240461f,0.205374f,0.165229f,0.121015f,0.073822f,0.024811f,
8 -0.024811f,-0.073822f,-0.121015f,-0.165229f,-0.205374f,-0.240461f,-0.269628f,-0.292156f,-0.307490f,…
9 0.312334f,0.281761f,0.223607f,0.143564f,0.049469f,-0.049469f,-0.143564f,-0.223607f,-0.281761f,-0.31…
10 -0.312334f,-0.281761f,-0.223607f,-0.143564f,-0.049469f,0.049469f,0.143564f,0.223607f,0.281761f,0.31…
11 0.307490f,0.240461f,0.121015f,-0.024811f,-0.165229f,-0.269628f,-0.315253f,-0.292156f,-0.205374f,-0.…
12 0.073822f,0.205374f,0.292156f,0.315253f,0.269628f,0.165229f,0.024811f,-0.121015f,-0.240461f,-0.3074…
13 0.300750f,0.185874f,0.000000f,-0.185874f,-0.300750f,-0.300750f,-0.185874f,-0.000000f,0.185874f,0.30…
14 0.300750f,0.185874f,0.000000f,-0.185874f,-0.300750f,-0.300750f,-0.185874f,-0.000000f,0.185874f,0.30…
[all …]
|
| /cmsis-dsp-latest/ComputeLibrary/Source/ |
| D | arm_cl_tables.c | 4 * SPDX-License-Identifier: MIT
32 1.f,1.f,1.f,1.f,
33 0.0416598916054f,0.0416598916054f,0.0416598916054f,0.0416598916054f,
34 0.500000596046f,0.500000596046f,0.500000596046f,0.500000596046f,
35 0.0014122662833f,0.0014122662833f,0.0014122662833f,0.0014122662833f,
36 1.00000011921f,1.00000011921f,1.00000011921f,1.00000011921f,
37 0.00833693705499f,0.00833693705499f,0.00833693705499f,0.00833693705499f,
38 0.166665703058f,0.166665703058f,0.166665703058f,0.166665703058f,
39 0.000195780929062f,0.000195780929062f,0.000195780929062f,0.000195780929062f
61 -2.29561495781f,-2.29561495781f,-2.29561495781f,-2.29561495781f,
[all …]
|
| /cmsis-dsp-latest/Include/ |
| D | arm_vec_math.h | 6 * Target Processor: Cortex-M and Cortex-A cores
9 * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
11 * SPDX-License-Identifier: Apache-2.0
17 * www.apache.org/licenses/LICENSE-2.0
42 static const float32_t __logf_rng_f32=0.693147180f;
54 xinv.f = ax; in vrecip_medprec_f32()
55 m = 0x3F800000 - (xinv.i & 0x7F800000); in vrecip_medprec_f32()
57 xinv.f = 1.41176471f - 0.47058824f * xinv.f; in vrecip_medprec_f32()
60 b = 2.0f - xinv.f * ax; in vrecip_medprec_f32()
61 xinv.f = xinv.f * b; in vrecip_medprec_f32()
[all …]
|
| D | arm_vec_math_f16.h | 6 * Target Processor: Cortex-M and Cortex-A cores
9 * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
11 * SPDX-License-Identifier: Apache-2.0
17 * www.apache.org/licenses/LICENSE-2.0
55 xinv.f = ax; in vrecip_medprec_f16()
57 m = 0x03c00 - (xinv.i & 0x07c00); in vrecip_medprec_f16()
59 xinv.f = 1.41176471f16 - 0.47058824f16 * xinv.f; in vrecip_medprec_f16()
62 b = 2.0f16 - xinv.f * ax; in vrecip_medprec_f16()
63 xinv.f = xinv.f * b; in vrecip_medprec_f16()
65 b = 2.0f16 - xinv.f * ax; in vrecip_medprec_f16()
[all …]
|
| /cmsis-dsp-latest/Scripts/ |
| D | genMVETwiddleCoefs.py | 17 return struct.unpack('<f', struct.pack('<f', x))[0]
20 parser.add_argument('-f', nargs='?',type = str, default="../Source/CommonTables/arm_mve_tables.c", …
21 parser.add_argument('-f16', nargs='?',type = str, default="../Source/CommonTables/arm_mve_tables_f1…
22 parser.add_argument('-he', nargs='?',type = str, default="../Include/arm_mve_tables.h", help="H Fil…
23 parser.add_argument('-he16', nargs='?',type = str, default="../Include/arm_mve_tables_f16.h", help=…
38 def printCUInt32Array(f,name,arr): argument
40 print("const uint32_t %s[%d]={" % (name,len(arr)),file=f)
46 print("",file=f)
48 print(val,end="",file=f)
50 print("};\n",file=f)
[all …]
|
| /cmsis-dsp-latest/Source/FilteringFunctions/ |
| D | arm_biquad_cascade_df1_init_f16.c | 2 /* ----------------------------------------------------------------------
5 * Description: Floating-point Biquad cascade DirectFormI(DF1) filter initialization function
10 * Target Processor: Cortex-M and Cortex-A cores
11 * -------------------------------------------------------------------- */
13 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
15 * SPDX-License-Identifier: Apache-2.0
21 * www.apache.org/licenses/LICENSE-2.0
43 @brief Initialization function for the floating-point Biquad cascade filter.
44 @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
61 …Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</cod…
[all …]
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| /cmsis-dsp-latest/Examples/ARM/arm_svm_example/ |
| D | arm_svm_example_f32.c | 1 /* ----------------------------------------------------------------------
2 * Copyright (C) 2019-2020 ARM Limited. All rights reserved.
12 * Target Processor: Cortex-M/Cortex-A
17 * - Redistributions of source code must retain the above copyright
19 * - Redistributions in binary form must reproduce the above copyright
23 * - Neither the name of ARM LIMITED nor the names of its contributors
39 * -------------------------------------------------------------------- */
50 * about classical ML with CMSIS-DSP and python scikit-learn:
51 …oper.arm.com/solutions/machine-learning-on-arm/developer-material/how-to-guides/implement-classica…
63 Those parameters can be generated with the python library scikit-learn.
[all …]
|
| /cmsis-dsp-latest/Source/MatrixFunctions/ |
| D | arm_householder_f32.c | 1 /* ----------------------------------------------------------------------
4 * Description: Floating-point Householder transform
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
50 \f[
52 \f]
54 and a scalar \f$\beta\f$ such that:
[all …]
|
| /cmsis-dsp-latest/dsppp/Include/dsppp/ |
| D | fixed_point.hpp | 1 // -*- C++ -*-
24 to CMSIS-DSP and only to allow the use of this library from other
27 MSVC is not going to be used to cross-compile to ARM. So, having a MSVC
51 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); in __SSAT()
52 const int32_t min = -1 - max ; in __SSAT()
69 const uint32_t max = ((1U << sat) - 1U); in __USAT()
106 return ((int32_t)(clip_int64_to_q31((int64_t)x - (int32_t)y))); in __QSUB()
117 * @param F number of fractional bits
121 constexpr bool test64(const int M,const int F,const int S){return((M+F+S)>32 && (M+F+S)<=64);} in test64() argument
128 * @param F number of fractional bits
[all …]
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| /cmsis-dsp-latest/ComputeLibrary/Include/ |
| D | NEMath.h | 4 * SPDX-License-Identifier: MIT
118 * tanh(x) = (e^2x - 1)/(e^2x + 1)
120 * @note We clamp x to [-5,5] to avoid overflowing issues.
142 * tanh(x) = (e^2x - 1)/(e^2x + 1)
144 * @note We clamp x to [-5,5] to avoid overflowing issues.
218 static const float32_t CONST_1[4] = {1.f,1.f,1.f,1.f}; in vfloorq_f32()
303 …c const float32_t CONST_LN2[4] = {0.6931471805f,0.6931471805f,0.6931471805f,0.6931471805f… in vexpq_f32()
304 …c const float32_t CONST_INV_LN2[4] = {1.4426950408f,1.4426950408f,1.4426950408f,1.4426950408f… in vexpq_f32()
305 static const float32_t CONST_0[4] = {0.f,0.f,0.f,0.f}; in vexpq_f32()
306 static const int32_t CONST_NEGATIVE_126[4] = {-126,-126,-126,-126}; in vexpq_f32()
[all …]
|
| /cmsis-dsp-latest/Source/SupportFunctions/ |
| D | arm_float_to_q31.c | 1 /* ----------------------------------------------------------------------
4 * Description: Converts the elements of the floating-point vector to Q31 vector
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
36 * @defgroup float_to_x Convert 32-bit floating point value
45 @brief Converts the elements of the floating-point vector to Q31 vector.
46 @param[in] pSrc points to the floating-point input vector
[all …]
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| D | arm_float_to_q15.c | 1 /* ----------------------------------------------------------------------
4 * Description: Converts the elements of the floating-point vector to Q15 vector
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
41 @brief Converts the elements of the floating-point vector to Q15 vector.
42 @param[in] pSrc points to the floating-point input vector
92 blkCnt--; in arm_float_to_q15()
[all …]
|
| /cmsis-dsp-latest/PythonWrapper/examples/ |
| D | testdsp2.py | 5 import cmsisdsp.fixedpoint as f namespace
42 a=np.array([1.,-3.,4.,0.,-10.,8.])
56 a31 = f.toQ31(a)
58 print(f.Q31toF32(i[0]),i[1])
60 a15 = f.toQ15(a)
62 print(f.Q15toF32(i[0]),i[1])
64 a7 = f.toQ7(a)
66 print(f.Q7toF32(i[0]),i[1])
71 a=np.array([1.,-3.,4.,0.5,-10.,8.])
89 a31 = f.toQ31(a)
[all …]
|
| /cmsis-dsp-latest/Source/QuaternionMathFunctions/ |
| D | arm_rotation2quaternion_f32.c | 1 /* ----------------------------------------------------------------------
4 * Description: Floating-point rotation to quaternion conversion
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
56 * q and -q are representing the same rotation. This ambiguity must be taken into
85 q = vdupq_n_f32(0.0f); in arm_rotation2quaternion_f32()
102 (void)arm_sqrt_f32(trace + 1.0f, &doubler) ; // invs=4*qw in arm_rotation2quaternion_f32()
[all …]
|
| /cmsis-dsp-latest/Examples/ARM/arm_bayes_example/ |
| D | arm_bayes_example_f32.c | 1 /* ----------------------------------------------------------------------
2 * Copyright (C) 2019-2020 ARM Limited. All rights reserved.
12 * Target Processor: Cortex-M/Cortex-A
17 * - Redistributions of source code must retain the above copyright
19 * - Redistributions in binary form must reproduce the above copyright
23 * - Neither the name of ARM LIMITED nor the names of its contributors
39 * -------------------------------------------------------------------- */
50 * about classical ML with CMSIS-DSP and python scikit-learn:
51 …oper.arm.com/solutions/machine-learning-on-arm/developer-material/how-to-guides/implement-classica…
62 Those parameters can be generated with the python library scikit-learn.
[all …]
|
| /cmsis-dsp-latest/Source/FastMathFunctions/ |
| D | arm_atan2_f32.c | 1 /* ----------------------------------------------------------------------
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
38 #define ATANHALFF32 0.463648f
39 #define PIHALFF32 1.5707963267948966192313f
43 static const float32_t atan2_coefs_f32[ATAN2_NB_COEFS_F32]={0.0f
44 ,1.0000001638308195518f
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|
| /cmsis-dsp-latest/Source/WindowFunctions/ |
| D | arm_hft248d_f32.c | 1 /* ----------------------------------------------------------------------
4 * Description: Floating-point (f32) Hft248d window
9 * Target Processor: Cortex-M and Cortex-A cores
10 * -------------------------------------------------------------------- */
12 * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved.
14 * SPDX-License-Identifier: Apache-2.0
20 * www.apache.org/licenses/LICENSE-2.0
61 | ------------------------------------: | -----------------: |
68 Included in CMSIS-DSP with authorization from professor
75 flat-top windows.
[all …]
|
