| /Zephyr-Core-3.5.0/samples/shields/x_nucleo_53l0a1/src/ |
| D | display_7seg.h | 7 * SPDX-License-Identifier: Apache-2.0
15 * ---
17 * -2-
19 * ---
25 #define CHAR_0 (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
26 #define CHAR_1 (BIT(5) | BIT(6))
27 #define CHAR_2 (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
28 #define CHAR_3 (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
29 #define CHAR_4 (BIT(1) | BIT(2) | BIT(5) | BIT(6))
30 #define CHAR_5 (BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(6))
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| /Zephyr-Core-3.5.0/tests/kernel/common/src/ |
| D | bitfield.c | 4 * SPDX-License-Identifier: Apache-2.0
14 #define BIT_INDEX(bit) ((3 - ((bit >> 3) & 0x3)) + 4*(bit >> 5)) argument
16 #define BIT_INDEX(bit) (bit >> 3) argument
18 #define BIT_VAL(bit) (1 << (bit & 0x7)) argument
41 unsigned int bit; in ZTEST()
46 for (bit = 0U; bit < 32; ++bit) { in ZTEST()
47 sys_set_bit((mem_addr_t)&b1, bit); in ZTEST()
49 zassert_equal(b1, (1 << bit), in ZTEST()
50 "sys_set_bit failed on bit %d\n", bit); in ZTEST()
52 zassert_true(sys_test_bit((mem_addr_t)&b1, bit), in ZTEST()
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| /Zephyr-Core-3.5.0/drivers/ieee802154/ |
| D | ieee802154_mcr20a_regs.h | 1 /* ieee802154_mcr20a_regs.h - Registers definition for NXP MCR20A */
6 * SPDX-License-Identifier: Apache-2.0
11 * which are used in the macros for the bit field manipulation.
47 #define MCR20A_REG_READ (BIT(7))
48 #define MCR20A_BUF_READ (BIT(7) | BIT(6))
49 #define MCR20A_BUF_BYTE_READ (BIT(7) | BIT(6) | BIT(5))
51 #define MCR20A_BUF_WRITE (BIT(6))
52 #define MCR20A_BUF_BYTE_WRITE (BIT(6) | BIT(5))
93 /* ---------------- (0x27) */
112 /* ---------------- (0x3a) */
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| /Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/reg/ |
| D | mec172x_ecia.h | 4 * SPDX-License-Identifier: Apache-2.0
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
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| D | mec172x_i2c_smb.h | 4 * SPDX-License-Identifier: Apache-2.0
36 * Size 8-bit
40 #define MCHP_I2C_SMB_CTRL_ACK BIT(0)
41 #define MCHP_I2C_SMB_CTRL_STO BIT(1)
42 #define MCHP_I2C_SMB_CTRL_STA BIT(2)
43 #define MCHP_I2C_SMB_CTRL_ENI BIT(3)
45 #define MCHP_I2C_SMB_CTRL_ESO BIT(6)
46 #define MCHP_I2C_SMB_CTRL_PIN BIT(7)
47 /* Status Read-only */
49 #define MCHP_I2C_SMB_STS_NBB BIT(0)
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| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | gpio_ite_it8xxx2.c | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
12 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
35 /* gpio port data register (bit mapping to pin) */
39 /* gpio port data mirror register (bit mapping to pin) */
41 /* gpio port output type register (bit mapping to pin) */
57 ((struct gpio_ite_data *)(dev)->data)
60 ((const struct gpio_ite_cfg *)(dev)->config)
63 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
73 * From WUESR1-WUESR4, the address increases by ones. From WUESR5 on in wuesr()
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| /Zephyr-Core-3.5.0/drivers/sensor/lps25hb/ |
| D | lps25hb.h | 1 /* sensor_lps25hb.h - header file for LPS25HB pressure and temperature
8 * SPDX-License-Identifier: Apache-2.0
26 #define LPS25HB_MASK_RES_CONF_AVGT (BIT(3) | BIT(2))
28 #define LPS25HB_MASK_RES_CONF_AVGP (BIT(1) | BIT(0))
32 #define LPS25HB_MASK_CTRL_REG1_PD BIT(7)
34 #define LPS25HB_MASK_CTRL_REG1_ODR (BIT(6) | BIT(5) | BIT(4))
36 #define LPS25HB_MASK_CTRL_REG1_DIFF_EN BIT(3)
38 #define LPS25HB_MASK_CTRL_REG1_BDU BIT(2)
40 #define LPS25HB_MASK_CTRL_REG1_RESET_AZ BIT(1)
42 #define LPS25HB_MASK_CTRL_REG1_SIM BIT(0)
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| /Zephyr-Core-3.5.0/drivers/sensor/lsm9ds0_gyro/ |
| D | lsm9ds0_gyro.h | 1 /* sensor_lsm9ds0_gyro.h - header file for LSM9DS0 gyroscope sensor driver */
6 * SPDX-License-Identifier: Apache-2.0
23 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6))
25 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_BW (BIT(5) | BIT(4))
27 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_PD BIT(3)
29 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_ZEN BIT(2)
31 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_XEN BIT(1)
33 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_YEN BIT(0)
37 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPM (BIT(5) | BIT(4))
39 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPCF (BIT(3) | BIT(2) | BIT(1) | \
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| /Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/neorv32/ |
| D | soc.h | 4 * SPDX-License-Identifier: Apache-2.0
23 #define NEORV32_SYSINFO_CPU_ZICSR BIT(0)
24 #define NEORV32_SYSINFO_CPU_ZIFENCEI BIT(1)
25 #define NEORV32_SYSINFO_CPU_ZMMUL BIT(2)
26 #define NEORV32_SYSINFO_CPU_ZBB BIT(3)
27 #define NEORV32_SYSINFO_CPU_ZFINX BIT(5)
28 #define NEORV32_SYSINFO_CPU_ZXSCNT BIT(6)
29 #define NEORV32_SYSINFO_CPU_ZXNOCNT BIT(7)
30 #define NEORV32_SYSINFO_CPU_PMP BIT(8)
31 #define NEORV32_SYSINFO_CPU_HPM BIT(9)
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| /Zephyr-Core-3.5.0/include/zephyr/math/ |
| D | ilog2.h | 4 * SPDX-License-Identifier: Apache-2.0
25 * This calculates the floor of log2 (integer log2) for 32-bit
31 * nested if-else blocks.
42 (((n) & BIT(31)) == BIT(31)) ? 31 : \
43 (((n) & BIT(30)) == BIT(30)) ? 30 : \
44 (((n) & BIT(29)) == BIT(29)) ? 29 : \
45 (((n) & BIT(28)) == BIT(28)) ? 28 : \
46 (((n) & BIT(27)) == BIT(27)) ? 27 : \
47 (((n) & BIT(26)) == BIT(26)) ? 26 : \
48 (((n) & BIT(25)) == BIT(25)) ? 25 : \
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| /Zephyr-Core-3.5.0/drivers/sensor/lps22hb/ |
| D | lps22hb.h | 1 /* sensor_lps25hb.h - header file for LPS22HB pressure and temperature
8 * SPDX-License-Identifier: Apache-2.0
22 #define LPS22HB_MASK_INTERRUPT_CFG_AUTORIFP BIT(7)
24 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_ARP BIT(6)
26 #define LPS22HB_MASK_INTERRUPT_CFG_AUTOZERO BIT(5)
28 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_AZ BIT(4)
30 #define LPS22HB_MASK_INTERRUPT_CFG_DIFF_EN BIT(3)
32 #define LPS22HB_MASK_INTERRUPT_CFG_LIR BIT(2)
34 #define LPS22HB_MASK_INTERRUPT_CFG_PL_E BIT(1)
36 #define LPS22HB_MASK_INTERRUPT_CFG_PH_E BIT(0)
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| /Zephyr-Core-3.5.0/drivers/audio/ |
| D | tas6422dac.h | 4 * SPDX-License-Identifier: Apache-2.0
18 #define MODE_CTRL_RESET BIT(7)
19 #define MODE_CTRL_RESET_MASK BIT(7)
20 #define MODE_CTRL_PBTL_CH12 BIT(4)
21 #define MODE_CTRL_PBTL_CH12_MASK BIT(4)
22 #define MODE_CTRL_CH1_LO_MODE BIT(3)
23 #define MODE_CTRL_CH1_LO_MODE_MASK BIT(3)
24 #define MODE_CTRL_CH2_LO_MODE BIT(2)
25 #define MODE_CTRL_CH2_LO_MODE_MASK BIT(2)
29 #define MISC_CTRL_1_HPF_BYPASS BIT(7)
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| /Zephyr-Core-3.5.0/drivers/sensor/apds9960/ |
| D | apds9960.h | 5 * SPDX-License-Identifier: Apache-2.0
14 #define APDS9960_ENABLE_GEN BIT(6)
15 #define APDS9960_ENABLE_PIEN BIT(5)
16 #define APDS9960_ENABLE_AIEN BIT(4)
17 #define APDS9960_ENABLE_WEN BIT(3)
18 #define APDS9960_ENABLE_PEN BIT(2)
19 #define APDS9960_ENABLE_AEN BIT(1)
20 #define APDS9960_ENABLE_PON BIT(0)
32 #define APDS9960_PERS_PPERS (BIT(4) | BIT(5) | BIT(6) | BIT(7))
33 #define APDS9960_APERS_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
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| /Zephyr-Core-3.5.0/drivers/ipm/ |
| D | ipm_nrfx_ipc.h | 4 * SPDX-License-Identifier: Apache-2.0
13 * Message channels are one-way connections between cores.
19 * SIGNAL0 -> CHANNEL0 -> EVENT0
24 * EVENT1 <- CHANNEL1 <- SIGNAL1
52 [0] = BIT(0),
53 [1] = BIT(1),
54 [2] = BIT(2),
55 [3] = BIT(3),
56 [4] = BIT(4),
57 [5] = BIT(5),
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| /Zephyr-Core-3.5.0/drivers/sensor/tmd2620/ |
| D | tmd2620.h | 4 * SPDX-License-Identifier: Apache-2.0
15 #define TMD2620_ENABLE_WEN BIT(3)
16 #define TMD2620_ENABLE_PEN BIT(2)
17 #define TMD2620_ENABLE_PON BIT(0)
28 * If the WLONG bit is set:
57 #define TMD2620_PERS_PPERS (BIT(4) | BIT(5) | BIT(6) | BIT(7))
60 #define TMD2620_CFG0_WLONG BIT(2)
65 #define TMD2620_PCFG0_PPULSE_LEN_8US BIT(6)
66 #define TMD2620_PCFG0_PPULSE_LEN_16US BIT(7)
67 #define TMD2620_PCFG0_PPULSE_LEN_32US (BIT(6) | BIT(7))
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| /Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/reg/ |
| D | mec_kbc.h | 4 * SPDX-License-Identifier: Apache-2.0
13 /* ---- EM8042 Keyboard Controller (KBC) ---- */
15 /* EC_KBC_STS and KBC_STS_RD bit definitions */
17 #define MCHP_KBC_STS_OBF BIT(MCHP_KBC_STS_OBF_POS)
19 #define MCHP_KBC_STS_IBF BIT(MCHP_KBC_STS_IBF_POS)
21 #define MCHP_KBC_STS_UD0 BIT(MCHP_KBC_STS_UD0_POS)
23 #define MCHP_KBC_STS_CD BIT(MCHP_KBC_STS_CD_POS)
25 #define MCHP_KBC_STS_UD1 BIT(MCHP_KBC_STS_UD1_POS)
27 #define MCHP_KBC_STS_AUXOBF BIT(MCHP_KBC_STS_AUXOBF_POS)
32 #define MCHP_KBC_STS_UD2_0 BIT(6)
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| /Zephyr-Core-3.5.0/drivers/sensor/lsm9ds0_mfd/ |
| D | lsm9ds0_mfd.h | 1 /* sensor_lsm9ds0_mfd.h - header file for LSM9DS0 accelerometer, magnetometer
8 * SPDX-License-Identifier: Apache-2.0
22 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMOR BIT(7)
24 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMOR BIT(6)
26 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMOR BIT(5)
28 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMOR BIT(4)
30 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMDA BIT(3)
32 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMDA BIT(2)
34 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMDA BIT(1)
36 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMDA BIT(0)
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| /Zephyr-Core-3.5.0/drivers/can/ |
| D | can_mcp251xfd.h | 5 * SPDX-License-Identifier: Apache-2.0
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
82 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
87 #define MCP251XFD_REG_CON_ABAT BIT(27)
98 #define MCP251XFD_REG_CON_TXQEN BIT(20)
99 #define MCP251XFD_REG_CON_STEF BIT(19)
100 #define MCP251XFD_REG_CON_SERR2LOM BIT(18)
101 #define MCP251XFD_REG_CON_ESIGM BIT(17)
102 #define MCP251XFD_REG_CON_RTXAT BIT(16)
103 #define MCP251XFD_REG_CON_BRSDIS BIT(12)
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| /Zephyr-Core-3.5.0/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/nrfx_glue/ |
| D | bt_ctlr_used_resources.h | 4 * SPDX-License-Identifier: Apache-2.0
19 #define HAL_PALNA_GPIOTE_MASK BIT(HAL_PALNA_GPIOTE_CHAN)
27 #define HAL_PDN_CSN_GPIOTE_MASK (BIT(HAL_PDN_GPIOTE_CHAN) | BIT(HAL_CSN_GPIOTE_CHAN))
37 (BIT(HAL_RADIO_ENABLE_TX_ON_TICK_PPI) | \
38 BIT(HAL_RADIO_ENABLE_RX_ON_TICK_PPI) | \
39 BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) | \
40 BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI) | \
41 BIT(HAL_RADIO_END_TIME_CAPTURE_PPI) | \
42 BIT(HAL_EVENT_TIMER_START_PPI) | \
43 BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) | \
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| /Zephyr-Core-3.5.0/drivers/serial/ |
| D | uart_pl011_registers.h | 6 * SPDX-License-Identifier: Apache-2.0
45 #define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
48 #define PL011_FR_CTS BIT(0) /* clear to send - inverted */
49 #define PL011_FR_DSR BIT(1) /* data set ready - inverted */
50 #define PL011_FR_DCD BIT(2) /* data carrier detect - inverted */
51 #define PL011_FR_BUSY BIT(3) /* busy transmitting data */
52 #define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
53 #define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
54 #define PL011_FR_RXFF BIT(6) /* receive FIFO full */
55 #define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
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| /Zephyr-Core-3.5.0/include/zephyr/arch/common/ |
| D | sys_bitops.h | 6 * SPDX-License-Identifier: Apache-2.0
9 /* Memory bits manipulation functions in non-arch-specific C code */
24 static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit) in sys_set_bit() argument
28 *(volatile uint32_t *)addr = temp | (1 << bit); in sys_set_bit()
31 static ALWAYS_INLINE void sys_clear_bit(mem_addr_t addr, unsigned int bit) in sys_clear_bit() argument
35 *(volatile uint32_t *)addr = temp & ~(1 << bit); in sys_clear_bit()
38 static ALWAYS_INLINE int sys_test_bit(mem_addr_t addr, unsigned int bit) in sys_test_bit() argument
42 return temp & (1 << bit); in sys_test_bit()
60 void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit) in sys_bitfield_set_bit() argument
62 /* Doing memory offsets in terms of 32-bit values to prevent in sys_bitfield_set_bit()
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| /Zephyr-Core-3.5.0/drivers/sensor/lsm6ds0/ |
| D | lsm6ds0.h | 1 /* sensor_lsm6ds0.h - header file for LSM6DS0 accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
19 #define LSM6DS0_MASK_ACT_THS_SLEEP_ON_INACT_EN BIT(7)
21 #define LSM6DS0_MASK_ACT_THS_ACT_THS (BIT(6) | BIT(5) | BIT(4) | \
22 BIT(3) | BIT(2) | BIT(1) | \
23 BIT(0))
29 #define LSM6DS0_MASK_INT_GEN_CFG_XL_AOI_XL BIT(7)
31 #define LSM6DSO_MASK_INT_GEN_CFG_XL_6D BIT(6)
33 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZHIE_XL BIT(5)
35 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZLIE_XL BIT(4)
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| /Zephyr-Core-3.5.0/include/zephyr/arch/arm64/ |
| D | cpu.h | 4 * SPDX-License-Identifier: Apache-2.0
13 #define DAIFSET_FIQ_BIT BIT(0)
14 #define DAIFSET_IRQ_BIT BIT(1)
15 #define DAIFSET_ABT_BIT BIT(2)
16 #define DAIFSET_DBG_BIT BIT(3)
18 #define DAIFCLR_FIQ_BIT BIT(0)
19 #define DAIFCLR_IRQ_BIT BIT(1)
20 #define DAIFCLR_ABT_BIT BIT(2)
21 #define DAIFCLR_DBG_BIT BIT(3)
23 #define DAIF_FIQ_BIT BIT(6)
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| /Zephyr-Core-3.5.0/drivers/sensor/lsm6dsl/ |
| D | lsm6dsl.h | 1 /* sensor_lsm6dsl.h - header file for LSM6DSL accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
29 #define LSM6DSL_MASK_FUNC_CFG_EN BIT(7)
31 #define LSM6DSL_MASK_FUNC_CFG_EN_B BIT(5)
35 #define LSM6DSL_MASK_SENSOR_SYNC_TIME_FRAME_TPH (BIT(3) | BIT(2) | \
36 BIT(1) | BIT(0))
40 #define LSM6DSL_MASK_SENSOR_SYNC_RES_RATIO (BIT(1) | BIT(0))
44 #define LSM6DSL_MASK_FIFO_CTRL1_FTH (BIT(7) | BIT(6) | \
45 BIT(5) | BIT(4) | \
46 BIT(3) | BIT(2) | \
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| /Zephyr-Core-3.5.0/dts/riscv/ite/ |
| D | it8xxx2-wuc-map.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/dt-util.h>
11 it8xxx2-wuc-map {
12 compatible = "ite,it8xxx2-wuc-map";
16 wucs = <&wuc2 BIT(0)>; /* GPD0 */
19 wucs = <&wuc2 BIT(1)>; /* GPD1 */
22 wucs = <&wuc2 BIT(2)>; /* GPC4 */
25 wucs = <&wuc2 BIT(3)>; /* GPC6 */
28 wucs = <&wuc2 BIT(4)>; /* GPD2 */
31 wucs = <&wuc2 BIT(5)>; /* GPE4 */
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