| /Zephyr-latest/samples/modules/cmsis_dsp/moving_average/ |
| D | sample.yaml | 7 - samples
9 - qemu_cortex_m0
10 - native_sim
12 - cmsis-dsp
17 - "Input\\[00\\]: 0 0 0 0 0 0 0 0 0 0 | Output\\[00\\]: 0.00"
18 - "Input\\[01\\]: 0 0 0 0 0 0 0 0 0 1 | Output\\[01\\]: 0.10"
19 - "Input\\[02\\]: 0 0 0 0 0 0 0 0 1 2 | Output\\[02\\]: 0.30"
20 - "Input\\[03\\]: 0 0 0 0 0 0 0 1 2 3 | Output\\[03\\]: 0.60"
21 - "Input\\[04\\]: 0 0 0 0 0 0 1 2 3 4 | Output\\[04\\]: 1.00"
22 - "Input\\[05\\]: 0 0 0 0 0 1 2 3 4 5 | Output\\[05\\]: 1.50"
[all …]
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| /Zephyr-latest/tests/lib/cmsis_dsp/filtering/src/ |
| D | misc_q15.c | 3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
53 DEFINE_CORRELATE_TEST(14, 17);
58 DEFINE_CORRELATE_TEST(15, 17);
63 DEFINE_CORRELATE_TEST(16, 17);
66 DEFINE_CORRELATE_TEST(17, 15);
67 DEFINE_CORRELATE_TEST(17, 16);
68 DEFINE_CORRELATE_TEST(17, 17);
69 DEFINE_CORRELATE_TEST(17, 18);
70 DEFINE_CORRELATE_TEST(17, 33);
[all …]
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| /Zephyr-latest/boards/shields/waveshare_epaper/ |
| D | waveshare_epaper_gdew075t7.overlay | 4 * SPDX-License-Identifier: Apache-2.0
15 compatible = "zephyr,mipi-dbi-spi";
16 spi-dev = <&arduino_spi>;
17 dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */
18 reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
19 write-only;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 mipi-max-frequency = <4000000>;
29 busy-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */
[all …]
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| D | waveshare_epaper_gdew042t2.overlay | 14 compatible = "zephyr,mipi-dbi-spi";
15 spi-dev = <&arduino_spi>;
16 dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */
17 reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
18 write-only;
19 #address-cells = <1>;
20 #size-cells = <0>;
24 mipi-max-frequency = <4000000>;
28 busy-gpios = <&arduino_header 13 GPIO_ACTIVE_LOW>; /* D7 */
30 softstart = [17 17 17];
|
| D | waveshare_epaper_gdew042t2-p.overlay | 4 * SPDX-License-Identifier: Apache-2.0
14 mipi_dbi_waveshare_epaper_gdew042t2-p {
15 compatible = "zephyr,mipi-dbi-spi";
16 spi-dev = <&arduino_spi>;
17 dc-gpios = <&arduino_header 15 GPIO_ACTIVE_HIGH>; /* D9 */
18 reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
19 write-only;
20 #address-cells = <1>;
21 #size-cells = <0>;
29 mipi-max-frequency = <4000000>;
[all …]
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| /Zephyr-latest/tests/subsys/display/cfb/basic/src/ |
| D | print_rectspace1016.c | 4 * SPDX-License-Identifier: Apache-2.0
104 zassert_ok(cfb_print(dev, " ", 11, 17)); in ZTEST()
107 zassert_true(verify_image_and_bg(11, 17, rectspace1016, 10, 16, 0)); in ZTEST()
152 zassert_ok(cfb_print(dev, " ", 11, 17)); in ZTEST()
155 zassert_true(verify_image_and_bg(11, 17, kerning_3_2rectspace1016, 23, 16, 0)); in ZTEST()
161 zassert_ok(cfb_print(dev, " ", display_width - 23, 17)); in ZTEST()
164 zassert_true(verify_image(display_width - 23, 17, kerning_3_2rectspace1016, 23, 16)); in ZTEST()
170 zassert_ok(cfb_print(dev, " ", display_width - 22, 17)); in ZTEST()
173 zassert_true(verify_image(display_width - 22, 17, rectspace1016, 10, 16)); in ZTEST()
179 zassert_ok(cfb_print(dev, " ", -(10 - 3), -(16 - 4))); in ZTEST()
[all …]
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| D | draw_text_rectspace1016.c | 4 * SPDX-License-Identifier: Apache-2.0
104 zassert_ok(cfb_draw_text(dev, " ", 11, 17)); in ZTEST()
107 zassert_true(verify_image_and_bg(11, 17, rectspace1016, 10, 16, 0)); in ZTEST()
152 zassert_ok(cfb_draw_text(dev, " ", 11, 17)); in ZTEST()
155 zassert_true(verify_image_and_bg(11, 17, kerning_3_2rectspace1016, 23, 16, 0)); in ZTEST()
161 zassert_ok(cfb_draw_text(dev, " ", display_width - 23, 17)); in ZTEST()
164 zassert_true(verify_image(display_width - 23, 17, kerning_3_2rectspace1016, 23, 16)); in ZTEST()
170 zassert_ok(cfb_draw_text(dev, " ", display_width - 22, 17)); in ZTEST()
174 verify_image(display_width - 22, 17, kerning_3_rightclip_1_2rectspace1016, 22, 16)); in ZTEST()
179 zassert_ok(cfb_draw_text(dev, " ", -(10 - 3), -(16 - 4))); in ZTEST()
[all …]
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/ |
| D | pinctrl-r8a77961.h | 3 * Copyright (c) 2023-2024 EPAM Systems
5 * SPDX-License-Identifier: Apache-2.0
10 #include "pinctrl-rcar-common.h"
13 #define PIN_NONE -1
47 #define PIN_A17 RCAR_GP_PIN(1, 17)
107 #define PIN_SD3_DS RCAR_GP_PIN(4, 17)
125 #define PIN_MSIOF0_SCK RCAR_GP_PIN(5, 17)
151 #define PIN_SSI_SCK78 RCAR_GP_PIN(6, 17)
186 #define PIN_DU_DOTCLKIN1 RCAR_NOGP_PIN(17)
863 #define FUNC_AUDIO_CLKA_A IPSR(17, 0, 0)
[all …]
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| D | pinctrl-r8a77951.h | 4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
46 #define PIN_A17 RCAR_GP_PIN(1, 17)
106 #define PIN_SD3_DS RCAR_GP_PIN(4, 17)
124 #define PIN_MSIOF0_SCK RCAR_GP_PIN(5, 17)
150 #define PIN_SSI_SCK78 RCAR_GP_PIN(6, 17)
185 #define PIN_DU_DOTCLKIN1 RCAR_NOGP_PIN(17)
867 #define FUNC_AUDIO_CLKA_A IPSR(17, 0, 0)
868 #define FUNC_AUDIO_CLKB_B IPSR(17, 4, 0)
[all …]
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| /Zephyr-latest/dts/arm/microchip/ |
| D | mec172x_common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "microchip,xec-pcr";
13 reg-names = "pcrr", "vbatr";
15 core-clock-div = <1>;
17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
19 clk32kmon-period-min = <1435>;
20 clk32kmon-period-max = <1495>;
21 clk32kmon-duty-cycle-var-max = <132>;
22 clk32kmon-valid-min = <4>;
[all …]
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | ite,it8xxx2-pinctrl-func.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
32 volt-sel:
[all …]
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| D | sifive,pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
12 - SIFIVE_PINMUX_IOF0
13 - SIFIVE_PINMUX_IOF1
15 For example, setting pins 16 and 17 both to IOF0 would look like this:
17 #include <dt-bindings/pinctrl/sifive-pinctrl.h>
24 pinmux = <17 SIFIVE_PINMUX_IOF0>;
36 child-binding:
|
| /Zephyr-latest/dts/arm/ene/ |
| D | kb1200.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-m4";
24 clock-frequency = <DT_FREQ_M(48)>;
29 compatible = "mmio-sram";
34 flash-controller@50100000 {
35 compatible = "ene,kb1200-flash-controller";
37 #address-cells = <1>;
[all …]
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| /Zephyr-latest/include/zephyr/dt-bindings/reset/ |
| D | gd32f3x0.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-common.h"
36 #define GD32_RESET_TIMER15 GD32_RESET_CONFIG(APB2RST, 17U)
46 #define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U)
53 #define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHBRST, 17U)
|
| /Zephyr-latest/boards/nordic/nrf9160dk/dts/nrf9160/ |
| D | nrf9160dk_uart1_on_if0_3.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 <NRF_PSEL(UART_RX, 0, 17)>,
20 <NRF_PSEL(UART_RX, 0, 17)>,
23 low-power-enable;
31 pinctrl-0 = <&uart1_default_alt>;
32 pinctrl-1 = <&uart1_sleep_alt>;
33 pinctrl-names = "default", "sleep";
|
| /Zephyr-latest/samples/userspace/shared_mem/src/ |
| D | main.h | 4 * SPDX-License-Identifier: Apache-2.0
54 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25}
56 17, 18, 19, 20, 21, 22, 23, 24, 25, 5, 0, 4, 1, 3, 2}
58 15, 14, 17, 16, 19, 18, 21, 20, 23, 22, 25, 24}
|
| /Zephyr-latest/samples/drivers/rtc/ |
| D | README.rst | 1 .. zephyr:code-sample:: rtc
2 :name: Real-Time Clock (RTC)
3 :relevant-api: rtc_interface
5 Set and read the date/time from a Real-Time Clock.
19 .. zephyr-app-commands::
20 :zephyr-app: samples/drivers/rtc
28 .. code-block:: console
30 RTC date and time: 2024-11-17 04:19:00
31 RTC date and time: 2024-11-17 04:19:01
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| /Zephyr-latest/boards/nordic/nrf9160dk/dts/nrf52840/ |
| D | nrf9160dk_uart1_on_if0_3.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
18 psels = <NRF_PSEL(UART_TX, 0, 17)>,
27 psels = <NRF_PSEL(UART_TX, 0, 17)>,
31 low-power-enable;
39 pinctrl-0 = <&uart1_default_alt>;
40 pinctrl-1 = <&uart1_sleep_alt>;
41 pinctrl-names = "default", "sleep";
|
| /Zephyr-latest/boards/ebyte/e73_tbb/ |
| D | ebyte_e73_tbb_nrf52832-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
22 low-power-enable;
28 psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
35 psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
36 low-power-enable;
|
| /Zephyr-latest/subsys/net/lib/lwm2m/ |
| D | ucifi_lpwan.h | 4 * SPDX-License-Identifier: Apache-2.0
10 /* Mandatory resource: ID 6 - IEEE MAC address of the device (up to 64 bits) */
11 #define MAC_ADDRESS_SIZE 17 /* 16 hex digits, eg. "01a2b3c4d5e6f708\0" */
14 /* clang-format off */
31 #define UCIFI_LPWAN_NUMBER_REPEATS_RID 17
39 /* clang-format on */
|
| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | gd32f3x0-clocks.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #include "gd32-clocks-common.h"
35 #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHBEN, 17U)
49 #define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U)
63 #define GD32_CLOCK_TIMER15 GD32_CLOCK_CONFIG(APB2EN, 17U)
|
| /Zephyr-latest/tests/drivers/flash/common/boards/ |
| D | nrf52840dk_mx25r_high_perf.overlay | 1 /delete-node/ &qspi;
4 gpio-reserved-ranges = <0 2>, <6 1>, <8 3>, <18 6>;
8 compatible = "nordic,nrf-spim";
10 cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
13 compatible = "jedec,spi-nor";
15 spi-max-frequency = <33000000>;
16 jedec-id = [c2 28 17];
17 sfdp-bfp = [
24 has-dpd;
25 t-enter-dpd = <10000>;
[all …]
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| /Zephyr-latest/soc/intel/apollo_lake/ |
| D | soc_gpio.h | 2 * Copyright (c) 2018-2019, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
40 #define APL_GPIO_17 17
74 #define APL_GPIO_49 17
124 #define APL_GPIO_204 17
158 #define APL_GPIO_89 17
207 #define APL_GPIO_147 17
258 #define APL_GPIO_169 17
306 ((cfg->pin_offset >> 5) << 2)
|
| /Zephyr-latest/tests/subsys/dsp/basicmath/src/ |
| D | q15.c | 3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
19 #define ABS_ERROR_THRESH_Q63 ((q63_t)(1 << 17))
51 17);
53 17);
87 ref_add_possat, 17);
89 ref_add_negsat, 17);
123 17);
125 17);
159 ref_sub_possat, 17);
[all …]
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| /Zephyr-latest/samples/boards/nordic/nrfx_prs/boards/ |
| D | nrf9160dk_nrf9160.overlay | 5 <NRF_PSEL(SPIM_MOSI, 0, 17)>;
9 bias-pull-down;
16 <NRF_PSEL(SPIM_MOSI, 0, 17)>,
18 low-power-enable;
29 bias-pull-down;
45 compatible = "nordic,nrf-spim";
47 cs-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
48 pinctrl-0 = <&spi1_default_alt>;
49 pinctrl-1 = <&spi1_sleep_alt>;
50 pinctrl-names = "default", "sleep";
[all …]
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