1 /* 2 * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 * Copyright 2016-2017 NXP 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * o Redistributions of source code must retain the above copyright notice, this list 9 * of conditions and the following disclaimer. 10 * 11 * o Redistributions in binary form must reproduce the above copyright notice, this 12 * list of conditions and the following disclaimer in the documentation and/or 13 * other materials provided with the distribution. 14 * 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "fsl_xcvr.h" 32 33 /******************************************************************************* 34 * Definitions 35 ******************************************************************************/ 36 37 /******************************************************************************* 38 * Prototypes 39 ******************************************************************************/ 40 41 /******************************************************************************* 42 * Variables 43 ******************************************************************************/ 44 45 /******************************************************************************* 46 * Code 47 ******************************************************************************/ 48 const xcvr_mode_config_t zgbe_mode_config = 49 { 50 .radio_mode = ZIGBEE_MODE, 51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_ZigBee_MASK, 52 53 /* XCVR_MISC configs */ 54 .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | 55 XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | 56 XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, 57 .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(4) | 58 XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | 59 XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(2), 60 61 /* XCVR_PHY configs */ 62 .phy_pre_ref0_init = 0x0, /* Not used in Zigbee */ 63 .phy_pre_ref1_init = 0x0, /* Not used in Zigbee */ 64 .phy_pre_ref2_init = 0x0, /* Not used in Zigbee */ 65 66 .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | 67 XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 68 XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | 69 XCVR_PHY_CFG1_BSM_EN_BLE(0) | 70 XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | 71 XCVR_PHY_CFG1_CTS_THRESH(0xC0) | 72 XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), 73 74 .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) 75 #if !RADIO_IS_GEN_2P1 76 | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) 77 #endif /* !RADIO_IS_GEN_2P1 */ 78 , 79 80 /* XCVR_PLL_DIG configs */ 81 82 /* XCVR_RX_DIG configs */ 83 .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */ 84 XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ 85 XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), 86 87 .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */ 88 XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ 89 90 .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), 91 /* XCVR_TSM configs */ 92 #if (DATA_PADDING_EN) 93 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+ZGBE_TX_DIG_EN_TX_HI_ADJ), /* DATA_PADDING adjustments are specified relative to the non-Zigbee base timing */ 94 #else 95 .tsm_timing_35_init = B0(ZGBE_TX_DIG_EN_ASSERT), 96 #endif /* (DATA_PADDING_EN) */ 97 98 /* XCVR_TX_DIG configs */ 99 .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | 100 XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | 101 XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | 102 XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | 103 XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | 104 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | 105 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | 106 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | 107 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0) , 108 .tx_gfsk_coeff1_26mhz = 0, 109 .tx_gfsk_coeff2_26mhz = 0, 110 .tx_gfsk_coeff1_32mhz = 0, 111 .tx_gfsk_coeff2_32mhz = 0, 112 }; 113 114 const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config = 115 { 116 .radio_mode = ZIGBEE_MODE, 117 .data_rate = DR_500KBPS, 118 119 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, 120 .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ 121 122 .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, 123 .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(1) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(1), /* BBA_BW_SEL and BBA2_BW_SEL */ 124 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, 125 .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(1), /*TZA_BW_SEL */ 126 127 .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | 128 XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , 129 130 /* AGC configs */ 131 .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(8) | 132 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 133 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 134 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 135 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | 136 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 137 .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | 138 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 139 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 140 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 141 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | 142 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 143 144 /* All constant values are represented as 16 bits, register writes will remove unused bits */ 145 .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF, 146 .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, 147 .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0002, 148 .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0008, 149 .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, 150 .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0000, 151 .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE8, 152 .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFD7, 153 .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFE6, 154 .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0022, 155 .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0075, 156 .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00B2, 157 158 /* IEEE 802.15.4 32MHz Channel Filter -- 1.55/1.25/5/0.97/B5 */ 159 .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, 160 .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF, 161 .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005, 162 .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0004, 163 .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, 164 .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, 165 .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001D, 166 .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0025, 167 .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFCE, 168 .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFA1, 169 .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0040, 170 .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0124, 171 172 .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | 173 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | 174 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | 175 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | 176 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | 177 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | 178 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | 179 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , 180 .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | 181 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | 182 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | 183 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | 184 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | 185 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , 186 187 .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), 188 .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), 189 }; 190 191 /* CUSTOM datarate dependent config structure for ONLY 802.15.4 */ 192 /*! 193 * @brief XCVR 500K bps DATA RATE specific configure structure 194 */ 195 const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config = 196 { 197 .data_rate = DR_500KBPS, 198 .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | 199 XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x8) | 200 XCVR_PHY_EL_CFG_EL_INTERVAL(0x10) , 201 .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | 202 XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), 203 .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) | 204 XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), 205 206 .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(13) | 207 XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), 208 .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(10) | 209 XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), 210 211 .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(13) | 212 XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(29), 213 .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(21) | 214 XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(47), 215 216 .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | 217 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | 218 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | 219 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | 220 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | 221 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | 222 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), 223 224 .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | 225 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | 226 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | 227 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | 228 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | 229 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | 230 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), 231 232 .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | 233 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | 234 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), 235 .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(1) | 236 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | 237 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1), 238 239 .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(26) | 240 XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), 241 .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(48) | 242 XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(0), 243 }; 244 245
