1// 2// syscache_asm.S - system-dependent assembly language cache management routines 3// 4// These functions are now obsolete. They cannot be properly implemented 5// in the HAL, because the required settings of CACHEATTR are entirely 6// system- or board-dependent. The HAL is not board specific; it is merely 7// processor-configuration specific. These cache enable and disable 8// functions do a "best-guess" of what values may be appropriate. 9// They should be avoided. (Instead, use xthal_set_[id]cacheattr() 10// and provide specific CACHEATTR values for the board or system. 11// See the LSP ref manual for info on how to obtain such a value as 12// computed by xt-genldscripts for a specific LSP, e.g. by using the 13// address of the _memmap_cacheattr_reset symbol.) 14// 15// $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/syscache_asm.S#1 $ 16 17// Copyright (c) 2003-2013 Tensilica Inc. 18// 19// Permission is hereby granted, free of charge, to any person obtaining 20// a copy of this software and associated documentation files (the 21// "Software"), to deal in the Software without restriction, including 22// without limitation the rights to use, copy, modify, merge, publish, 23// distribute, sublicense, and/or sell copies of the Software, and to 24// permit persons to whom the Software is furnished to do so, subject to 25// the following conditions: 26// 27// The above copyright notice and this permission notice shall be included 28// in all copies or substantial portions of the Software. 29// 30// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 31// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 32// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 33// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 34// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 35// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 36// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 37 38#ifdef INCLUDE_DEPRECATED_HAL_CACHE_CODE 39 40#include <xtensa/cacheasm.h> 41#include <xtensa/cacheattrasm.h> 42#include <xtensa/config/system.h> 43 44/*** Modify this for your particular board or system: ***/ 45#define CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_DEFAULT 46#define CACHEATTR_BYPASS XSHAL_ISS_CACHEATTR_BYPASS 47 48//---------------------------------------------------------------------- 49// Enable and disable the caches 50//---------------------------------------------------------------------- 51 52 .text 53 54 .global xthal_icache_enable 55 .global xthal_dcache_enable 56 .global xthal_icache_enable_nw 57 .global xthal_dcache_enable_nw 58 59 .global xthal_icache_disable 60 .global xthal_dcache_disable 61 .global xthal_icache_disable_nw 62 .global xthal_dcache_disable_nw 63 64 /* 65 * Since we can't enable/disable the icache and dcache independently, 66 * and don't have a nice place to store a state which would enable 67 * us to only enable them both when both have been requested to be 68 * enabled, we simply enable both for any request to enable either, 69 * and disable both for any request to disable either cache. 70 */ 71 72 .align 4 73xthal_icache_enable: 74 abi_entry 75 movi a3, xthal_set_icacheattr 76 movi a6, CACHEATTR_DEFAULT // get cache-enabled attributes 77 callx4 a3 // enable i-cache 78 mov a2, a6 // (in case future version has a return value) 79 abi_return 80 .size xthal_icache_enable, . - xthal_icache_enable 81 82 .align 4 83xthal_dcache_enable: 84 abi_entry 85 movi a3, xthal_set_dcacheattr 86 movi a6, CACHEATTR_DEFAULT // get cache-enabled attributes 87 callx4 a3 // enable d-cache 88 mov a2, a6 // (in case future version has a return value) 89 abi_return 90 .size xthal_dcache_enable, . - xthal_dcache_enable 91 92 .align 4 93xthal_icache_disable: 94 abi_entry 95 movi a3, xthal_set_icacheattr 96 movi a6, CACHEATTR_BYPASS // get cache-disabled attributes 97 callx4 a3 // disable i-cache 98 mov a2, a6 // (in case future version has a return value) 99 abi_return 100 .size xthal_icache_disable, . - xthal_icache_disable 101 102 .align 4 103xthal_dcache_disable: 104 abi_entry 105 movi a3, xthal_set_dcacheattr 106 movi a6, CACHEATTR_BYPASS // get cache-disabled attributes 107 callx4 a3 // disable d-cache 108 mov a2, a6 // (in case future version has a return value) 109 abi_return 110 .size xthal_dcache_disable, . - xthal_dcache_disable 111 112 .align 4 113xthal_icache_enable_nw: 114 movi a3, xthal_set_icacheattr_nw 115 movi a2, CACHEATTR_DEFAULT // get cache-enabled attributes 116 jx a3 // enable i-cache 117 .size xthal_icache_enable_nw, . - xthal_icache_enable_nw 118 119 .align 4 120xthal_dcache_enable_nw: 121 movi a3, xthal_set_dcacheattr_nw 122 movi a2, CACHEATTR_DEFAULT // get cache-enabled attributes 123 jx a3 // enable d-cache 124 .size xthal_dcache_enable_nw, . - xthal_dcache_enable_nw 125 126 .align 4 127xthal_icache_disable_nw: 128 movi a3, xthal_set_icacheattr_nw 129 movi a2, CACHEATTR_BYPASS // get cache-disabled attributes 130 jx a3 // disable i-cache 131 .size xthal_icache_disable_nw, . - xthal_icache_disable_nw 132 133 .align 4 134xthal_dcache_disable_nw: 135 movi a3, xthal_set_dcacheattr_nw 136 movi a2, CACHEATTR_BYPASS // get cache-disabled attributes 137 jx a3 // disable d-cache 138 .size xthal_dcache_disable_nw, . - xthal_dcache_disable_nw 139 140#endif /* INCLUDE_DEPRECATED_HAL_CACHE_CODE */ 141 142
