1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_XRDC_H_
10 #define _FSL_XRDC_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup xrdc
16 * @{
17 */
18
19 /******************************************************************************
20 * Definitions
21 *****************************************************************************/
22 #define FSL_XRDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */
23
24 #ifndef FSL_CLOCK_XRDC_GATE_COUNT
25 #define FSL_CLOCK_XRDC_GATE_COUNT 1U
26 #endif
27
28 /*! @brief XRDC status. */
29 enum _xrdc_status
30 {
31 kStatus_XRDC_NoError = MAKE_STATUS(kStatusGroup_XRDC, 0) /*!< No error captured. */
32 };
33
34 /*!
35 * @brief XRDC hardware configuration.
36 */
37 typedef struct _xrdc_hardware_config
38 {
39 uint8_t masterNumber; /*!< Number of bus masters. */
40 uint8_t domainNumber; /*!< Number of domains. */
41 uint8_t pacNumber; /*!< Number of PACs. */
42 uint8_t mrcNumber; /*!< Number of MRCs. */
43 } xrdc_hardware_config_t;
44
45 /*!
46 * @brief XRDC PID enable mode, the register bit XRDC_MDA_Wx[PE], used for domain hit evaluation.
47 */
48 typedef enum _xrdc_pid_enable
49 {
50 kXRDC_PidDisable, /*!< PID is not used in domain hit evalution. */
51 kXRDC_PidDisable1, /*!< PID is not used in domain hit evalution. */
52 kXRDC_PidExp0, /*!< ((XRDC_MDA_W[PID] & ~XRDC_MDA_W[PIDM]) == (XRDC_PID[PID] & ~XRDC_MDA_W[PIDM])). */
53 kXRDC_PidExp1 /*!< ~((XRDC_MDA_W[PID] & ~XRDC_MDA_W[PIDM]) == (XRDC_PID[PID] & ~XRDC_MDA_W[PIDM])). */
54 } xrdc_pid_enable_t;
55
56 /*!
57 * @brief XRDC domain ID select method, the register bit XRDC_MDA_Wx[DIDS], used for
58 * domain hit evaluation.
59 */
60 typedef enum _xrdc_did_sel
61 {
62 kXRDC_DidMda, /*!< Use MDAn[3:0] as DID. */
63 kXRDC_DidInput, /*!< Use the input DID (DID_in) as DID. */
64 kXRDC_DidMdaAndInput, /*!< Use MDAn[3:2] concatenated with DID_in[1:0] as DID. */
65 kXRDC_DidReserved /*!< Reserved. */
66 } xrdc_did_sel_t;
67
68 /*!
69 * @brief XRDC secure attribute, the register bit XRDC_MDA_Wx[SA], used for non-processor
70 * bus master domain assignment.
71 */
72 typedef enum _xrdc_secure_attr
73 {
74 kXRDC_ForceSecure, /*!< Force the bus attribute for this master to secure. */
75 kXRDC_ForceNonSecure, /*!< Force the bus attribute for this master to non-secure. */
76 kXRDC_MasterSecure, /*!< Use the bus master's secure/nonsecure attribute directly. */
77 kXRDC_MasterSecure1, /*!< Use the bus master's secure/nonsecure attribute directly. */
78 } xrdc_secure_attr_t;
79
80 /*!
81 * @brief XRDC privileged attribute, the register bit XRDC_MDA_Wx[PA], used for non-processor
82 * bus master domain assignment.
83 */
84 typedef enum _xrdc_privilege_attr
85 {
86 kXRDC_ForceUser, /*!< Force the bus attribute for this master to user. */
87 kXRDC_ForcePrivilege, /*!< Force the bus attribute for this master to privileged. */
88 kXRDC_MasterPrivilege, /*!< Use the bus master's attribute directly. */
89 kXRDC_MasterPrivilege1, /*!< Use the bus master's attribute directly. */
90 } xrdc_privilege_attr_t;
91
92 /*!
93 * @brief Domain assignment for the processor bus master.
94 */
95 typedef struct _xrdc_processor_domain_assignment
96 {
97 uint32_t domainId : 4U; /*!< Domain ID. */
98 uint32_t domainIdSelect : 2U; /*!< Domain ID select method, see @ref xrdc_did_sel_t. */
99 uint32_t pidEnable : 2U; /*!< PId enable method, see @ref xrdc_pid_enable_t. */
100 uint32_t pidMask : 6U; /*!< PId mask. */
101 uint32_t : 2U; /*!< Reserved. */
102 uint32_t pid : 6U; /*!< PId value. */
103 uint32_t : 2U; /*!< Reserved. */
104 #if !(defined(FSL_FEATURE_XRDC_NO_MDA_LPID) && FSL_FEATURE_XRDC_NO_MDA_LPID)
105 uint32_t logicPartId : 4U; /*!< Logical partition ID. */
106 #else
107 uint32_t : 4U; /*!< Reserved. */
108 #endif
109 #if !(defined(FSL_FEATURE_XRDC_NO_MDA_LPE) && FSL_FEATURE_XRDC_NO_MDA_LPE)
110 uint32_t enableLogicPartId : 1U; /*!< Logical partition ID. */
111 #else
112 uint32_t : 1U; /*!< Reserved. */
113 #endif /* FSL_FEATURE_XRDC_NO_MDA_LPE */
114 uint32_t : 1U; /*!< Reserved. */
115 uint32_t lock : 1U; /*!< Lock the register. */
116 uint32_t : 1U; /*!< Reserved. */
117 } xrdc_processor_domain_assignment_t;
118
119 /*!
120 * @brief Domain assignment for the non-processor bus master.
121 */
122 typedef struct _xrdc_non_processor_domain_assignment
123 {
124 uint32_t domainId : 4U; /*!< Domain ID. */
125 uint32_t privilegeAttr : 2U; /*!< Privileged attribute, see @ref xrdc_privilege_attr_t. */
126 uint32_t secureAttr : 2U; /*!< Secure attribute, see @ref xrdc_secure_attr_t. */
127 uint32_t bypassDomainId : 1U; /*!< Bypass domain ID. */
128 uint32_t : 15U; /*!< Reserved. */
129 #if !(defined(FSL_FEATURE_XRDC_NO_MDA_LPID) && FSL_FEATURE_XRDC_NO_MDA_LPID)
130 uint32_t logicPartId : 4U; /*!< Logical partition ID. */
131 #else
132 uint32_t : 4U; /*!< Reserved. */
133 #endif
134 #if !(defined(FSL_FEATURE_XRDC_NO_MDA_LPE) && FSL_FEATURE_XRDC_NO_MDA_LPE)
135 uint32_t enableLogicPartId : 1U; /*!< Enable logical partition ID. */
136 #else
137 uint32_t : 1U; /*!< Reserved. */
138 #endif
139 uint32_t : 1U; /*!< Reserved. */
140 uint32_t lock : 1U; /*!< Lock the register. */
141 uint32_t : 1U; /*!< Reserved. */
142 } xrdc_non_processor_domain_assignment_t;
143
144 /*!
145 * @brief XRDC PID LK2 definition XRDC_PIDn[LK2]
146 */
147 typedef enum _xrdc_pid_lock
148 {
149 kXRDC_PidLockSecurePrivilegeWritable = 0U, /*!< Writable by any secure privileged write. */
150 kXRDC_PidLockSecurePrivilegeWritable1 = 1U, /*!< Writable by any secure privileged write. */
151 kXRDC_PidLockMasterXOnly = 2U, /*!< PIDx is only writable by master x. */
152 kXRDC_PidLockLocked = 3U /*!< Read-only until the next reset. */
153 } xrdc_pid_lock_t;
154
155 /*!
156 * @brief XRDC process identifier (PID) configuration.
157 */
158 typedef struct _xrdc_pid_config
159 {
160 uint32_t pid : 6U; /*!< PID value, PIDn[PID]. */
161 #if (defined(FSL_FEATURE_XRDC_HAS_PID_SP4SM) && FSL_FEATURE_XRDC_HAS_PID_SP4SM)
162 uint32_t : 21U; /*!< Reserved. */
163 uint32_t sp4smEnable : 1U; /*!< Enable special 4-state model. */
164 #else
165 uint32_t : 22U; /*!< Reserved. */
166 #endif
167 uint32_t tsmEnable : 1U; /*!< Enable three-state model. */
168 uint32_t lockMode : 2U; /*!< PIDn configuration lock mode, see @ref xrdc_pid_lock_t. */
169 uint32_t : 1U; /*!< Reserved. */
170 } xrdc_pid_config_t;
171
172 /*!
173 * @brief XRDC domain access control policy.
174 */
175 typedef enum _xrdc_access_policy
176 {
177 /* policy SecurePriv SecureUser NonSecurePriv NonSecureUsr*/
178 kXRDC_AccessPolicyNone = 0U, /* 000 none none none none */
179 kXRDC_AccessPolicySpuR = 1U, /* 001 r r none none */
180 kXRDC_AccessPolicySpRw = 2U, /* 010 r,w none none none */
181 kXRDC_AccessPolicySpuRw = 3U, /* 011 r,w r,w none none */
182 kXRDC_AccessPolicySpuRwNpR = 4U, /* 100 r,w r,w r none */
183 kXRDC_AccessPolicySpuRwNpuR = 5U, /* 101 r,w r,w r r */
184 kXRDC_AccessPolicySpuRwNpRw = 6U, /* 110 r,w r,w r,w none */
185 kXRDC_AccessPolicyAll = 7U /* 111 r,w r,w r,w r,w */
186 } xrdc_access_policy_t;
187
188 /*!
189 * @brief Access configuration lock mode, the register field PDAC and MRGD LK2.
190 */
191 typedef enum _xrdc_access_config_lock
192 {
193 kXRDC_AccessConfigLockWritable = 0U, /*!< Entire PDACn/MRGDn can be written. */
194 kXRDC_AccessConfigLockWritable1 = 1U, /*!< Entire PDACn/MRGDn can be written. */
195 kXRDC_AccessConfigLockDomainXOnly = 2U, /*!< Domain x only write the DxACP field. */
196 kXRDC_AccessConfigLockLocked = 3U /*!< PDACn is read-only until the next reset. */
197 } xrdc_access_config_lock_t;
198
199 #if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL) || \
200 (defined(FSL_FEATURE_XRDC_HAS_MRGD_EAL) && FSL_FEATURE_XRDC_HAS_MRGD_EAL)
201 /*!
202 * @brief Exclusive access lock mode configuration, the register field PDAC and MRGD EAL.
203 */
204 typedef enum _xrdc_excl_access_lock_config
205 {
206 kXRDC_ExclAccessLockDisabled = 0U, /*!< Lock disabled. */
207 kXRDC_ExclAccessLockDisabledUntilNextRst = 1U, /*!< Lock disabled until next reset. */
208 kXRDC_ExclAccessLockEnabledStateAvail = 2U, /*!< Lock enabled, lock state = available. */
209 kXRDC_ExclAccessLockEnabledStateNotAvail = 3U /*!< Lock enabled, lock state = not available. */
210 } xrdc_excl_access_lock_config_t;
211 #endif
212
213 /*!
214 * @brief XRDC peripheral domain access control configuration.
215 */
216 typedef struct _xrdc_periph_access_config
217 {
218 xrdc_periph_t periph; /*!< Peripheral name. */
219 xrdc_access_config_lock_t lockMode; /*!< PDACn lock configuration. */
220 #if !(defined(FSL_FEATURE_XRDC_NO_PDAC_SE) && FSL_FEATURE_XRDC_NO_PDAC_SE)
221 bool enableSema; /*!< Enable semaphore or not. */
222 uint32_t semaNum; /*!< Semaphore number. */
223 #endif
224 #if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL)
225 xrdc_excl_access_lock_config_t exclAccessLockMode; /*!< Exclusive access lock configuration. */
226 #endif
227 xrdc_access_policy_t policy[FSL_FEATURE_XRDC_DOMAIN_COUNT]; /*!< Access policy for each domain. */
228 } xrdc_periph_access_config_t;
229
230 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SZ) && FSL_FEATURE_XRDC_NO_MRGD_SZ)
231 /*!
232 * @brief XRDC memory size definition.
233 */
234 typedef enum _xrdc_mem_size
235 {
236 kXRDC_MemSizeNone = 0U, /*!< None size. */
237 kXRDC_MemSize32B = 4U, /*!< 2^(4+1) = 32 */
238 kXRDC_MemSize64B = 5U, /*!< 2^(5+1) = 64 */
239 kXRDC_MemSize128B = 6U, /*!< 2^(6+1) = 128 */
240 kXRDC_MemSize256B = 7U, /*!< 2^(7+1) = 256 */
241 kXRDC_MemSize512B = 8U, /*!< 2^(8+1) = 512 */
242 kXRDC_MemSize1K = 9U, /*!< 2^(9+1) = 1kB */
243 kXRDC_MemSize2K = 10U, /*!< 2^(10+1) = 2kB */
244 kXRDC_MemSize4K = 11U, /*!< 2^(11+1) = 4kB */
245 kXRDC_MemSize8K = 12U, /*!< 2^(12+1) = 8kB */
246 kXRDC_MemSize16K = 13U, /*!< 2^(13+1) = 16kB */
247 kXRDC_MemSize32K = 14U, /*!< 2^(14+1) = 32kB */
248 kXRDC_MemSize64K = 15U, /*!< 2^(15+1) = 64kB */
249 kXRDC_MemSize128K = 16U, /*!< 2^(16+1) = 128kB */
250 kXRDC_MemSize256K = 17U, /*!< 2^(17+1) = 256kB */
251 kXRDC_MemSize512K = 18U, /*!< 2^(18+1) = 512kB */
252 kXRDC_MemSize1M = 19U, /*!< 2^(19+1) = 1MB */
253 kXRDC_MemSize2M = 20U, /*!< 2^(20+1) = 2MB */
254 kXRDC_MemSize4M = 21U, /*!< 2^(21+1) = 4MB */
255 kXRDC_MemSize8M = 22U, /*!< 2^(22+1) = 8MB */
256 kXRDC_MemSize16M = 23U, /*!< 2^(23+1) = 16MB */
257 kXRDC_MemSize32M = 24U, /*!< 2^(24+1) = 32MB */
258 kXRDC_MemSize64M = 25U, /*!< 2^(25+1) = 64MB */
259 kXRDC_MemSize128M = 26U, /*!< 2^(26+1) = 128MB */
260 kXRDC_MemSize256M = 27U, /*!< 2^(27+1) = 256MB */
261 kXRDC_MemSize512M = 28U, /*!< 2^(28+1) = 512MB */
262 kXRDC_MemSize1G = 29U, /*!< 2^(29+1) = 1GB */
263 kXRDC_MemSize2G = 30U, /*!< 2^(30+1) = 2GB */
264 kXRDC_MemSize4G = 31U /*!< 2^(31+1) = 4GB */
265 } xrdc_mem_size_t;
266 #endif /* FSL_FEATURE_XRDC_NO_MRGD_SZ */
267
268 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) && FSL_FEATURE_XRDC_HAS_MRGD_ACCSET)
269 /*!
270 * @brief XRDC memory ACCSET (SET of programmable access flags).
271 */
272 typedef enum _xrdc_mem_accset
273 {
274 kXRDC_MemAccset1 = 0U, /*!< Memory region SET 1 of programmable access flags. */
275 kXRDC_MemAccset2 = 1U, /*!< Memory region SET 2 of programmable access flags. */
276 } xrdc_mem_accset_t;
277 #endif /* FSL_FEATURE_XRDC_HAS_MRGD_ACCSET */
278
279 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_CR) && FSL_FEATURE_XRDC_HAS_MRGD_CR)
280 /*!
281 * @brief XRDC memory code region indicator.
282 */
283 typedef enum _xrdc_mem_code_region
284 {
285 kXRDC_MemCodeRegion0 = 0U, /*!< Code region indicator 0=data. */
286 kXRDC_MemCodeRegion1 = 1U, /*!< Code region indicator 1=code. */
287 } xrdc_mem_code_region_t;
288 #endif /* FSL_FEATURE_XRDC_HAS_MRGD_CR */
289
290 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_DXSEL) && FSL_FEATURE_XRDC_HAS_MRGD_DXSEL)
291 /*!
292 * @brief XRDC domain access flags/policy select.
293 *
294 * Policy:
295 * {R,W,X} Read, write, execute flags.
296 * flag = 0 : inhibits access, flag = 1 : allows access.
297 * policy => SecurePriv_NonSecurePriv_SecureUser_NonSecureUsr
298 * xxx_xxx_xxx_xxx => PS{R,W,X}_PN{R,W,X}_US{R,W,X}_UN{R,W,X}
299 *
300 * PS > PN > US > UN PS > PN > US > UN
301 * DxSEL CodeRegion = 0 CodeRegion = 1
302 * 000 000_000_000_000 = 0x000 000_000_000_000 = 0x000
303 * 001 ACCSET1
304 * 010 ACCSET2
305 * 011 110_000_000_000 = 0xC00 001_001_001_001 = 0x249
306 * 100 110_110_000_000 = 0xD80 111_000_000_000 = 0xE00
307 * 101 110_110_100_100 = 0xDA4 110_111_000_000 = 0xDC0
308 * 110 110_110_110_000 = 0xDB0 110_110_111_000 = 0xDB8
309 * 111 110_110_110_110 = 0xDB6 110_110_111_111 = 0xDBF
310 */
311 typedef enum _xrdc_access_flags_select
312 {
313 kXRDC_AccessFlagsNone = 0U, /* Select predefined constant {r,w,x} flags. See the table above. */
314 kXRDC_AccessFlagsAlt1 = 1U, /* Select ACCSET1 4*{r,w,x} fully‐programmable access flags. */
315 kXRDC_AccessFlagsAlt2 = 2U, /* Select ACCSET2 4*{r,w,x} fully‐programmable access flags. */
316 kXRDC_AccessFlagsAlt3 = 3U, /* Select predefined constant {r,w,x} flags. See the table above. */
317 kXRDC_AccessFlagsAlt4 = 4U, /* Select predefined constant {r,w,x} flags. See the table above. */
318 kXRDC_AccessFlagsAlt5 = 5U, /* Select predefined constant {r,w,x} flags. See the table above. */
319 kXRDC_AccessFlagsAlt6 = 6U, /* Select predefined constant {r,w,x} flags. See the table above. */
320 kXRDC_AccessFlagsAlt7 = 7U /* Select predefined constant {r,w,x} flags. See the table above. */
321 } xrdc_access_flags_select_t;
322 #endif /* FSL_FEATURE_XRDC_HAS_MRGD_DXSEL */
323
324 /*!
325 * @brief XRDC memory region domain access control configuration.
326 */
327 typedef struct _xrdc_mem_access_config
328 {
329 xrdc_mem_t mem; /*!< Memory region descriptor name. */
330 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SE) && FSL_FEATURE_XRDC_NO_MRGD_SE)
331 bool enableSema; /*!< Enable semaphore or not. */
332 uint8_t semaNum; /*!< Semaphore number. */
333 #endif
334 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SZ) && FSL_FEATURE_XRDC_NO_MRGD_SZ)
335 xrdc_mem_size_t size; /*!< Memory region size. */
336 #endif
337 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_SRD) && FSL_FEATURE_XRDC_NO_MRGD_SRD)
338 uint8_t subRegionDisableMask; /*!< Sub-region disable mask. */
339 #endif
340
341 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) && FSL_FEATURE_XRDC_HAS_MRGD_ACCSET)
342 bool enableAccset1Lock; /*!< Enable ACCSET1 access lock or not. */
343 bool enableAccset2Lock; /*!< Enable ACCSET2 access lock or not. */
344 uint16_t accset1; /*!< SET 1 of Programmable access flags.
345 xxx_xxx_xxx_xxx => PS{R,W,X}_PN{R,W,X}_US{R,W,X}_UN{R,W,X}.
346 flag = 0 : inhibits access, flag = 1 : allows access. */
347 uint16_t accset2; /*!< SET 2 of Programmable access flags.
348 xxx_xxx_xxx_xxx => PS{R,W,X}_PN{R,W,X}_US{R,W,X}_UN{R,W,X}.
349 flag = 0 : inhibits access, flag = 1 : allows access. */
350 #endif
351 xrdc_access_config_lock_t lockMode; /*!< MRGDn lock configuration. */
352
353 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_DXACP) && FSL_FEATURE_XRDC_NO_MRGD_DXACP)
354 xrdc_access_policy_t policy[FSL_FEATURE_XRDC_DOMAIN_COUNT]; /*!< Access policy for each domain. */
355 #elif(defined(FSL_FEATURE_XRDC_HAS_MRGD_DXSEL) && FSL_FEATURE_XRDC_HAS_MRGD_DXSEL)
356 xrdc_access_flags_select_t
357 policy[FSL_FEATURE_XRDC_DOMAIN_COUNT]; /*!< Access policy/flags select for each domain. */
358 #endif
359
360 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_CR) && FSL_FEATURE_XRDC_HAS_MRGD_CR)
361 xrdc_mem_code_region_t codeRegion; /*!< Code region select. @ref xrdc_mem_code_region_t. */
362 #endif
363
364 uint32_t baseAddress; /*!< Memory region base/start address. */
365 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR) && FSL_FEATURE_XRDC_HAS_MRGD_ENDADDR)
366 uint32_t endAddress; /*!< Memory region end address. The 5 LSB of end address
367 is ignored and forced to 0x1F by hardware. */
368 #endif
369 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_EAL) && FSL_FEATURE_XRDC_HAS_MRGD_EAL)
370 xrdc_excl_access_lock_config_t exclAccessLockMode; /*!< Exclusive access lock configuration. */
371 #endif
372 } xrdc_mem_access_config_t;
373
374 /*!
375 * @brief XRDC controller definition for domain error check.
376 */
377 typedef enum _xrdc_controller
378 {
379 kXRDC_MemController0 = 0U, /*!< Memory region controller 0. */
380 kXRDC_MemController1 = 1U, /*!< Memory region controller 1. */
381 kXRDC_MemController2 = 2U, /*!< Memory region controller 2. */
382 kXRDC_MemController3 = 3U, /*!< Memory region controller 3. */
383 kXRDC_MemController4 = 4U, /*!< Memory region controller 4. */
384 kXRDC_MemController5 = 5U, /*!< Memory region controller 5. */
385 kXRDC_MemController6 = 6U, /*!< Memory region controller 6. */
386 kXRDC_MemController7 = 7U, /*!< Memory region controller 7. */
387 kXRDC_MemController8 = 8U, /*!< Memory region controller 8. */
388 kXRDC_MemController9 = 9U, /*!< Memory region controller 9. */
389 kXRDC_MemController10 = 10U, /*!< Memory region controller 10. */
390 kXRDC_MemController11 = 11U, /*!< Memory region controller 11. */
391 kXRDC_MemController12 = 12U, /*!< Memory region controller 12. */
392 kXRDC_MemController13 = 13U, /*!< Memory region controller 13. */
393 kXRDC_MemController14 = 14U, /*!< Memory region controller 14. */
394 kXRDC_MemController15 = 15U, /*!< Memory region controller 15. */
395 kXRDC_PeriphController0 = 16U, /*!< Peripheral access controller 0. */
396 kXRDC_PeriphController1 = 17U, /*!< Peripheral access controller 1. */
397 kXRDC_PeriphController2 = 18U, /*!< Peripheral access controller 2. */
398 kXRDC_PeriphController3 = 19U, /*!< Peripheral access controller 3. */
399 } xrdc_controller_t;
400
401 /*!
402 * @brief XRDC domain error state definition XRDC_DERR_W1_n[EST].
403 */
404 typedef enum _xrdc_error_state
405 {
406 kXRDC_ErrorStateNone = 0x00U, /*!< No access violation detected. */
407 kXRDC_ErrorStateNone1 = 0x01U, /*!< No access violation detected. */
408 kXRDC_ErrorStateSingle = 0x02U, /*!< Single access violation detected. */
409 kXRDC_ErrorStateMulti = 0x03U /*!< Multiple access violation detected. */
410 } xrdc_error_state_t;
411
412 /*!
413 * @brief XRDC domain error attribute definition XRDC_DERR_W1_n[EATR].
414 */
415 typedef enum _xrdc_error_attr
416 {
417 kXRDC_ErrorSecureUserInst = 0x00U, /*!< Secure user mode, instruction fetch access. */
418 kXRDC_ErrorSecureUserData = 0x01U, /*!< Secure user mode, data access. */
419 kXRDC_ErrorSecurePrivilegeInst = 0x02U, /*!< Secure privileged mode, instruction fetch access. */
420 kXRDC_ErrorSecurePrivilegeData = 0x03U, /*!< Secure privileged mode, data access. */
421 kXRDC_ErrorNonSecureUserInst = 0x04U, /*!< NonSecure user mode, instruction fetch access. */
422 kXRDC_ErrorNonSecureUserData = 0x05U, /*!< NonSecure user mode, data access. */
423 kXRDC_ErrorNonSecurePrivilegeInst = 0x06U, /*!< NonSecure privileged mode, instruction fetch access. */
424 kXRDC_ErrorNonSecurePrivilegeData = 0x07U /*!< NonSecure privileged mode, data access. */
425 } xrdc_error_attr_t;
426
427 /*!
428 * @brief XRDC domain error access type definition XRDC_DERR_W1_n[ERW].
429 */
430 typedef enum _xrdc_error_type
431 {
432 kXRDC_ErrorTypeRead = 0x00U, /*!< Error occurs on read reference. */
433 kXRDC_ErrorTypeWrite = 0x01U /*!< Error occurs on write reference. */
434 } xrdc_error_type_t;
435
436 /*!
437 * @brief XRDC domain error definition.
438 */
439 typedef struct _xrdc_error
440 {
441 xrdc_controller_t controller; /*!< Which controller captured access violation. */
442 uint32_t address; /*!< Access address that generated access violation. */
443 xrdc_error_state_t errorState; /*!< Error state. */
444 xrdc_error_attr_t errorAttr; /*!< Error attribute. */
445 xrdc_error_type_t errorType; /*!< Error type. */
446 uint8_t errorPort; /*!< Error port. */
447 uint8_t domainId; /*!< Domain ID. */
448 } xrdc_error_t;
449
450 /*******************************************************************************
451 * API
452 ******************************************************************************/
453
454 #if defined(__cplusplus)
455 extern "C" {
456 #endif
457
458 /*!
459 * @brief Initializes the XRDC module.
460 *
461 * This function enables the XRDC clock.
462 *
463 * @param base XRDC peripheral base address.
464 */
465 void XRDC_Init(XRDC_Type *base);
466
467 /*!
468 * @brief De-initializes the XRDC module.
469 *
470 * This function disables the XRDC clock.
471 *
472 * @param base XRDC peripheral base address.
473 */
474 void XRDC_Deinit(XRDC_Type *base);
475
476 /*!
477 * @name XRDC manager (XRDC_MGR)
478 * @{
479 */
480
481 /*!
482 * @brief Gets the XRDC hardware configuration.
483 *
484 * This function gets the XRDC hardware configurations, including number of bus
485 * masters, number of domains, number of MRCs and number of PACs.
486 *
487 * @param base XRDC peripheral base address.
488 * @param config Pointer to the structure to get the configuration.
489 */
490 void XRDC_GetHardwareConfig(XRDC_Type *base, xrdc_hardware_config_t *config);
491
492 /*!
493 * @brief Locks the XRDC global control register XRDC_CR.
494 *
495 * This function locks the XRDC_CR register. After it is locked, the register is
496 * read-only until the next reset.
497 *
498 * @param base XRDC peripheral base address.
499 */
XRDC_LockGlobalControl(XRDC_Type * base)500 static inline void XRDC_LockGlobalControl(XRDC_Type *base)
501 {
502 base->CR |= XRDC_CR_LK1_MASK;
503 }
504
505 /*!
506 * @brief Sets the XRDC global valid.
507 *
508 * This function sets the XRDC global valid or invalid. When the XRDC is global
509 * invalid, all accesses from all bus masters to all slaves are allowed.
510 *
511 * @param base XRDC peripheral base address.
512 * @param valid True to valid XRDC.
513 */
XRDC_SetGlobalValid(XRDC_Type * base,bool valid)514 static inline void XRDC_SetGlobalValid(XRDC_Type *base, bool valid)
515 {
516 if (valid)
517 {
518 #if (defined(FSL_FEATURE_XRDC_HAS_NO_CR_GVLD) && FSL_FEATURE_XRDC_HAS_NO_CR_GVLD)
519 base->CR |= (XRDC_CR_GVLDM_MASK | XRDC_CR_GVLDC_MASK | XRDC_CR_GVLDP_MASK);
520 #else
521 base->CR |= XRDC_CR_GVLD_MASK;
522 #endif
523 }
524 else
525 {
526 #if (defined(FSL_FEATURE_XRDC_HAS_NO_CR_GVLD) && FSL_FEATURE_XRDC_HAS_NO_CR_GVLD)
527 base->CR &= ~(XRDC_CR_GVLDM_MASK | XRDC_CR_GVLDC_MASK | XRDC_CR_GVLDP_MASK);
528 #else
529 base->CR &= ~XRDC_CR_GVLD_MASK;
530 #endif
531 }
532 }
533
534 /*!
535 * @brief Gets the domain ID of the current bus master.
536 *
537 * This function returns the domain ID of the current bus master.
538 *
539 * @param base XRDC peripheral base address.
540 * @return Domain ID of current bus master.
541 */
XRDC_GetCurrentMasterDomainId(XRDC_Type * base)542 static inline uint8_t XRDC_GetCurrentMasterDomainId(XRDC_Type *base)
543 {
544 return (uint8_t)((base->HWCFG1 & XRDC_HWCFG1_DID_MASK) >> XRDC_HWCFG1_DID_SHIFT);
545 }
546
547 /*!
548 * @brief Gets and clears the first domain error of the current domain.
549 *
550 * This function gets the first access violation information for the current domain
551 * and clears the pending flag. There might be multiple access violations pending
552 * for the current domain. This function only processes the first error.
553 *
554 * @param base XRDC peripheral base address.
555 * @param error Pointer to the error information.
556 * @return If the access violation is captured, this function returns the kStatus_Success.
557 * The error information can be obtained from the parameter error. If no
558 * access violation is captured, this function returns the kStatus_XRDC_NoError.
559 */
560 status_t XRDC_GetAndClearFirstDomainError(XRDC_Type *base, xrdc_error_t *error);
561
562 /*!
563 * @brief Gets and clears the first domain error of the specific domain.
564 *
565 * This function gets the first access violation information for the specific domain
566 * and clears the pending flag. There might be multiple access violations pending
567 * for the current domain. This function only processes the first error.
568 *
569 * @param base XRDC peripheral base address.
570 * @param error Pointer to the error information.
571 * @param domainId The error of which domain to get and clear.
572 * @return If the access violation is captured, this function returns the kStatus_Success.
573 * The error information can be obtained from the parameter error. If no
574 * access violation is captured, this function returns the kStatus_XRDC_NoError.
575 */
576 status_t XRDC_GetAndClearFirstSpecificDomainError(XRDC_Type *base, xrdc_error_t *error, uint8_t domainId);
577
578 /*@}*/
579
580 /*!
581 * @name XRDC Master Domain Assignment Controller (XRDC_MDAC).
582 * @{
583 */
584
585 /*!
586 * @brief Gets the default PID configuration structure.
587 *
588 * This function initializes the configuration structure to default values. The default
589 * values are:
590 *
591 * @code
592 * config->pid = 0U;
593 * config->tsmEnable = 0U;
594 * config->sp4smEnable = 0U;
595 * config->lockMode = kXRDC_PidLockSecurePrivilegeWritable;
596 * @endcode
597 *
598 * @param config Pointer to the configuration structure.
599 */
XRDC_GetPidDefaultConfig(xrdc_pid_config_t * config)600 static inline void XRDC_GetPidDefaultConfig(xrdc_pid_config_t *config)
601 {
602 assert(config);
603
604 (*((uint32_t *)config)) = 0U;
605 }
606
607 /*!
608 * @brief Configures the PID for a specific bus master.
609 *
610 * This function configures the PID for a specific bus master. Do not use this
611 * function for non-processor bus masters.
612 *
613 * @param base XRDC peripheral base address.
614 * @param master Which bus master to configure.
615 * @param config Pointer to the configuration structure.
616 */
XRDC_SetPidConfig(XRDC_Type * base,xrdc_master_t master,const xrdc_pid_config_t * config)617 static inline void XRDC_SetPidConfig(XRDC_Type *base, xrdc_master_t master, const xrdc_pid_config_t *config)
618 {
619 assert(config);
620
621 base->PID[master] = *((const uint32_t *)config);
622 }
623
624 /*!
625 * @brief Sets the PID configuration register lock mode.
626 *
627 * This function sets the PID configuration register lock XRDC_PIDn[LK2].
628 *
629 * @param base XRDC peripheral base address.
630 * @param master Which master's PID to lock.
631 * @param lockMode Lock mode to set.
632 */
XRDC_SetPidLockMode(XRDC_Type * base,xrdc_master_t master,xrdc_pid_lock_t lockMode)633 static inline void XRDC_SetPidLockMode(XRDC_Type *base, xrdc_master_t master, xrdc_pid_lock_t lockMode)
634 {
635 uint32_t reg = base->PID[master];
636
637 reg = ((reg & ~XRDC_PID_LK2_MASK) | XRDC_PID_LK2(lockMode));
638
639 base->PID[master] = reg;
640 }
641
642 /*!
643 * @brief Gets the default master domain assignment for non-processor bus master.
644 *
645 * This function gets the default master domain assignment for non-processor bus master.
646 * It should only be used for the no-processor bus masters, such as DMA. This function
647 * sets the assignment as follows:
648 *
649 * @code
650 * assignment->domainId = 0U;
651 * assignment->privilegeAttr = kXRDC_ForceUser;
652 * assignment->privilegeAttr = kXRDC_ForceSecure;
653 * assignment->bypassDomainId = 0U;
654 * assignment->blogicPartId = 0U;
655 * assignment->benableLogicPartId = 0U;
656 * assignment->lock = 0U;
657 * @endcode
658 *
659 * @param assignment Pointer to the assignment structure.
660 */
XRDC_GetDefaultNonProcessorDomainAssignment(xrdc_non_processor_domain_assignment_t * assignment)661 static inline void XRDC_GetDefaultNonProcessorDomainAssignment(xrdc_non_processor_domain_assignment_t *assignment)
662 {
663 assert(assignment);
664
665 *(uint32_t *)assignment = 0U;
666 }
667
668 /*!
669 * @brief Gets the default master domain assignment for the processor bus master.
670 *
671 * This function gets the default master domain assignment for the processor bus master.
672 * It should only be used for the processor bus masters, such as CORE0. This function
673 * sets the assignment as follows:
674 *
675 * @code
676 * assignment->domainId = 0U;
677 * assignment->domainIdSelect = kXRDC_DidMda;
678 * assignment->dpidEnable = kXRDC_PidDisable;
679 * assignment->pidMask = 0U;
680 * assignment->pid = 0U;
681 * assignment->logicPartId = 0U;
682 * assignment->enableLogicPartId = 0U;
683 * assignment->lock = 0U;
684 * @endcode
685 *
686 * @param assignment Pointer to the assignment structure.
687 */
XRDC_GetDefaultProcessorDomainAssignment(xrdc_processor_domain_assignment_t * assignment)688 static inline void XRDC_GetDefaultProcessorDomainAssignment(xrdc_processor_domain_assignment_t *assignment)
689 {
690 assert(assignment);
691
692 *(uint32_t *)assignment = 0U;
693 }
694
695 /*!
696 * @brief Sets the non-processor bus master domain assignment.
697 *
698 * This function sets the non-processor master domain assignment as valid.
699 * One bus master might have multiple domain assignment registers. The parameter
700 * \p assignIndex specifies which assignment register to set.
701 *
702 * Example: Set domain assignment for DMA0.
703 * @code
704 * xrdc_non_processor_domain_assignment_t nonProcessorAssignment;
705 *
706 * XRDC_GetDefaultNonProcessorDomainAssignment(&nonProcessorAssignment); // Get default assignment
707 * // Modify necessary members.
708 * nonProcessorAssignment.domainId = 1;
709 * nonProcessorAssignment.xxx = xxx; // Other modifications.
710 *
711 * // Set the domain assignment. Only 1 assignment register for DMA0. Pass in 0U as assignIndex;
712 * XRDC_SetMasterDomainAssignment(XRDC, kXrdcMasterDma0, 0U, &nonProcessorAssignment);
713 * @endcode
714 *
715 * @param base XRDC peripheral base address.
716 * @param master Which master to configure.
717 * @param assignIndex Which assignment register to set.
718 * @param assignment Pointer to the assignment structure.
719 */
XRDC_SetNonProcessorDomainAssignment(XRDC_Type * base,xrdc_master_t master,uint8_t assignIndex,const xrdc_non_processor_domain_assignment_t * assignment)720 static inline void XRDC_SetNonProcessorDomainAssignment(XRDC_Type *base,
721 xrdc_master_t master,
722 uint8_t assignIndex,
723 const xrdc_non_processor_domain_assignment_t *assignment)
724 {
725 /* Make sure the master is a non-CPU/non-processor master */
726 assert(base->MDACFG[master] & XRDC_MDACFG_NCM_MASK);
727 /* Make sure the master has the assignment register. */
728 assert(assignIndex < ((base->MDACFG[master] & XRDC_MDACFG_NMDAR_MASK) >> XRDC_MDACFG_NMDAR_SHIFT));
729 assert(assignment);
730
731 base->MDA[master].MDA_W[assignIndex] = ((*(const uint32_t *)assignment) | XRDC_MDA_W_VLD_MASK);
732 }
733
734 /*!
735 * @brief Sets the processor bus master domain assignment.
736 *
737 * This function sets the processor master domain assignment as valid.
738 * One bus master might have multiple domain assignment registers. The parameter
739 * \p assignIndex specifies which assignment register to set.
740 *
741 * Example: Set domain assignment for core 0.
742 * @code
743 * xrdc_processor_domain_assignment_t processorAssignment;
744 *
745 * XRDC_GetDefaultProcessorDomainAssignment(&processorAssignment); // Get default assignment
746 *
747 * // Set the domain assignment. There are 3 assignment registers for core 0.
748 * // Set assignment register 0.
749 * processorAssignment.domainId = 1;
750 * processorAssignment.xxx = xxx; // Other modifications.
751 * XRDC_SetMasterDomainAssignment(XRDC, kXrdcMasterCpu0, 0U, &processorAssignment);
752 *
753 * // Set assignment register 1.
754 * processorAssignment.domainId = 2;
755 * processorAssignment.xxx = xxx; // Other modifications.
756 * XRDC_SetMasterDomainAssignment(XRDC, kXrdcMasterCpu0, 1U, &processorAssignment);
757 *
758 * // Set assignment register 2.
759 * processorAssignment.domainId = 0;
760 * processorAssignment.xxx = xxx; // Other modifications.
761 * XRDC_SetMasterDomainAssignment(XRDC, kXrdcMasterCpu0, 2U, &processorAssignment);
762 * @endcode
763 *
764 * @param base XRDC peripheral base address.
765 * @param master Which master to configure.
766 * @param assignIndex Which assignment register to set.
767 * @param assignment Pointer to the assignment structure.
768 */
XRDC_SetProcessorDomainAssignment(XRDC_Type * base,xrdc_master_t master,uint8_t assignIndex,const xrdc_processor_domain_assignment_t * assignment)769 static inline void XRDC_SetProcessorDomainAssignment(XRDC_Type *base,
770 xrdc_master_t master,
771 uint8_t assignIndex,
772 const xrdc_processor_domain_assignment_t *assignment)
773 {
774 /* Make sure the master is a CPU/processor master */
775 assert(!(base->MDACFG[master] & XRDC_MDACFG_NCM_MASK));
776 /* Make sure the master has the assignment register. */
777 assert(assignIndex < ((base->MDACFG[master] & XRDC_MDACFG_NMDAR_MASK) >> XRDC_MDACFG_NMDAR_SHIFT));
778 assert(assignment);
779
780 base->MDA[master].MDA_W[assignIndex] = ((*(const uint32_t *)assignment) | XRDC_MDA_W_VLD_MASK);
781 }
782
783 /*!
784 * @brief Locks the bus master domain assignment register.
785 *
786 * This function locks the master domain assignment. One bus master might have
787 * multiple domain assignment registers. The parameter \p assignIndex specifies
788 * which assignment register to lock. After it is locked, the register can't be changed
789 * until next reset.
790 *
791 * @param base XRDC peripheral base address.
792 * @param master Which master to configure.
793 * @param assignIndex Which assignment register to lock.
794 */
XRDC_LockMasterDomainAssignment(XRDC_Type * base,xrdc_master_t master,uint8_t assignIndex)795 static inline void XRDC_LockMasterDomainAssignment(XRDC_Type *base, xrdc_master_t master, uint8_t assignIndex)
796 {
797 /* Make sure the master has the assignment register. */
798 assert(assignIndex < ((base->MDACFG[master] & XRDC_MDACFG_NMDAR_MASK) >> XRDC_MDACFG_NMDAR_SHIFT));
799
800 base->MDA[master].MDA_W[assignIndex] |= XRDC_MDA_W_LK1_MASK;
801 }
802
803 /*!
804 * @brief Sets the master domain assignment as valid or invalid.
805 *
806 * This function sets the master domain assignment as valid or invalid. One bus master might have
807 * multiple domain assignment registers. The parameter \p assignIndex specifies
808 * which assignment register to configure.
809 *
810 * @param base XRDC peripheral base address.
811 * @param master Which master to configure.
812 * @param assignIndex Index for the domain assignment register.
813 * @param valid True to set valid, false to set invalid.
814 */
XRDC_SetMasterDomainAssignmentValid(XRDC_Type * base,xrdc_master_t master,uint8_t assignIndex,bool valid)815 static inline void XRDC_SetMasterDomainAssignmentValid(XRDC_Type *base,
816 xrdc_master_t master,
817 uint8_t assignIndex,
818 bool valid)
819 {
820 /* Make sure the master has the assignment register. */
821 assert(assignIndex < ((base->MDACFG[master] & XRDC_MDACFG_NMDAR_MASK) >> XRDC_MDACFG_NMDAR_SHIFT));
822
823 if (valid)
824 {
825 base->MDA[master].MDA_W[assignIndex] |= XRDC_MDA_W_VLD_MASK;
826 }
827 else
828 {
829 base->MDA[master].MDA_W[assignIndex] &= ~XRDC_MDA_W_VLD_MASK;
830 }
831 }
832
833 /*@}*/
834
835 /*!
836 * @name XRDC Memory Region Controller (XRDC_MRC)
837 * @{
838 */
839
840 /*!
841 * @brief Gets the default memory region access policy.
842 *
843 * This function gets the default memory region access policy.
844 * It sets the policy as follows:
845 * @code
846 * config->enableSema = false;
847 * config->semaNum = 0U;
848 * config->subRegionDisableMask = 0U;
849 * config->size = kXrdcMemSizeNone;
850 * config->lockMode = kXRDC_AccessConfigLockWritable;
851 * config->baseAddress = 0U;
852 * config->policy[0] = kXRDC_AccessPolicyNone;
853 * config->policy[1] = kXRDC_AccessPolicyNone;
854 * ...
855 * config->policy[15] = kXRDC_AccessPolicyNone;
856 * @endcode
857 *
858 * @param config Pointer to the configuration structure.
859 */
860 void XRDC_GetMemAccessDefaultConfig(xrdc_mem_access_config_t *config);
861
862 /*!
863 * @brief Sets the memory region access policy.
864 *
865 * This function sets the memory region access configuration as valid.
866 * There are two methods to use it:
867 *
868 * Example 1: Set one configuration run time.
869 * @code
870 * // Set memory region 0x20000000 ~ 0x20000400 accessible by domain 0, use MRC0_1.
871 * xrdc_mem_access_config_t config =
872 * {
873 * .mem = kXRDC_MemMrc0_1,
874 * .baseAddress = 0x20000000U,
875 * .size = kXRDC_MemSize1K,
876 * .policy[0] = kXRDC_AccessPolicyAll
877 * };
878 * XRDC_SetMemAccessConfig(XRDC, &config);
879 * @endcode
880 *
881 * Example 2: Set multiple configurations during startup.
882 * @code
883 * // Set memory region 0x20000000 ~ 0x20000400 accessible by domain 0, use MRC0_1.
884 * // Set memory region 0x1FFF0000 ~ 0x1FFF0800 accessible by domain 0, use MRC0_2.
885 * xrdc_mem_access_config_t configs[] =
886 * {
887 * {
888 * .mem = kXRDC_MemMrc0_1,
889 * .baseAddress = 0x20000000U,
890 * .size = kXRDC_MemSize1K,
891 * .policy[0] = kXRDC_AccessPolicyAll
892 * },
893 * {
894 * .mem = kXRDC_MemMrc0_2,
895 * .baseAddress = 0x1FFF0000U,
896 * .size = kXRDC_MemSize2K,
897 * .policy[0] = kXRDC_AccessPolicyAll
898 * }
899 * };
900 *
901 * // Set the configurations.
902 * for (i=0U; i<((sizeof(configs)/sizeof(configs[0]))); i++)
903 * {
904 * XRDC_SetMemAccessConfig(XRDC, &configs[i]);
905 * }
906 * @endcode
907 *
908 * @param base XRDC peripheral base address.
909 * @param config Pointer to the access policy configuration structure.
910 */
911 void XRDC_SetMemAccessConfig(XRDC_Type *base, const xrdc_mem_access_config_t *config);
912
913 /*!
914 * @brief Sets the memory region descriptor register lock mode.
915 *
916 * @param base XRDC peripheral base address.
917 * @param mem Which memory region descriptor to lock.
918 * @param lockMode The lock mode to set.
919 */
XRDC_SetMemAccessLockMode(XRDC_Type * base,xrdc_mem_t mem,xrdc_access_config_lock_t lockMode)920 static inline void XRDC_SetMemAccessLockMode(XRDC_Type *base, xrdc_mem_t mem, xrdc_access_config_lock_t lockMode)
921 {
922 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_W3_LK2) && FSL_FEATURE_XRDC_NO_MRGD_W3_LK2)
923 uint32_t reg = base->MRGD[mem].MRGD_W[3];
924
925 reg = ((reg & ~XRDC_MRGD_W_LK2_MASK) | XRDC_MRGD_W_LK2(lockMode));
926
927 base->MRGD[mem].MRGD_W[3] = reg;
928 #elif(defined(FSL_FEATURE_XRDC_HAS_MRGD_W4_LK2) && FSL_FEATURE_XRDC_HAS_MRGD_W4_LK2)
929 uint32_t reg = base->MRGD[mem].MRGD_W[4];
930
931 reg = ((reg & ~XRDC_MRGD_W_LK2_MASK) | XRDC_MRGD_W_LK2(lockMode));
932
933 base->MRGD[mem].MRGD_W[4] = reg;
934 #endif
935 }
936
937 /*!
938 * @brief Sets the memory region descriptor as valid or invalid.
939 *
940 * This function sets the memory region access configuration dynamically. For example:
941 *
942 * @code
943 * // Set memory region 0x20000000 ~ 0x20000400 accessible by domain 0, use MRC0_1.
944 * xrdc_mem_access_config_t config =
945 * {
946 * .mem = kXRDC_MemMrc0_1,
947 * .baseAddress = 0x20000000U,
948 * .size = kXRDC_MemSize1K,
949 * .policy[0] = kXRDC_AccessPolicyAll
950 * };
951 * XRDC_SetMemAccessConfig(XRDC, &config);
952 *
953 * // Set the memory access configuration invalid.
954 * XRDC_SetMemAccessValid(kXRDC_MemMrc0_1, false);
955 *
956 * // Set the memory access configuration valid, the region 0x20000000 ~ 0x20000400 accessible by domain 0
957 * XRDC_SetMemAccessValid(kXRDC_MemMrc0_1, true);
958 * @endcode
959 *
960 * @param base XRDC peripheral base address.
961 * @param mem Which memory region descriptor to set.
962 * @param valid True to set valid, false to set invalid.
963 */
XRDC_SetMemAccessValid(XRDC_Type * base,xrdc_mem_t mem,bool valid)964 static inline void XRDC_SetMemAccessValid(XRDC_Type *base, xrdc_mem_t mem, bool valid)
965 {
966 #if !(defined(FSL_FEATURE_XRDC_NO_MRGD_W3_VLD) && FSL_FEATURE_XRDC_NO_MRGD_W3_VLD)
967 if (valid)
968 {
969 base->MRGD[mem].MRGD_W[3] |= XRDC_MRGD_W_VLD_MASK;
970 }
971 else
972 {
973 base->MRGD[mem].MRGD_W[3] &= ~XRDC_MRGD_W_VLD_MASK;
974 }
975 #elif(defined(FSL_FEATURE_XRDC_HAS_MRGD_W4_VLD) && FSL_FEATURE_XRDC_HAS_MRGD_W4_VLD)
976 if (valid)
977 {
978 base->MRGD[mem].MRGD_W[4] |= XRDC_MRGD_W_VLD_MASK;
979 }
980 else
981 {
982 base->MRGD[mem].MRGD_W[4] &= ~XRDC_MRGD_W_VLD_MASK;
983 }
984 #endif
985 }
986
987 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_EAL) && FSL_FEATURE_XRDC_HAS_MRGD_EAL)
988 /*!
989 * @brief Sets the memory region exclusive access lock mode configuration.
990 *
991 * Note: Any write to MRGD_W[0-3]_n clears the MRGD_W4_n[VLD] indicator so a coherent register state can be supported.
992 * It is indispensable to re-assert the valid bit when dynamically changing the EAL in the MRGD, which is done in
993 * this API.
994 *
995 * @param base XRDC peripheral base address.
996 * @param mem Which memory region's exclusive access lock mode to configure.
997 * @param lockMode The exclusive access lock mode to set.
998 */
999 void XRDC_SetMemExclAccessLockMode(XRDC_Type *base, xrdc_mem_t mem, xrdc_excl_access_lock_config_t lockMode);
1000
1001 /*!
1002 * @brief Forces the release of the memory region exclusive access lock.
1003 *
1004 * A lock can be forced to the available state (EAL=10) by a domain that does not own the
1005 * lock through the forced lock release procedure:
1006 * The procedure to force a exclusive access lock release is as follows:
1007 * 1. Write 0x02000046 to W1 register (PAC/MSC) or W3 register (MRC)
1008 * 2. Write 0x02000052 to W1 register (PAC/MSC) or W3 register (MRC)
1009 *
1010 * Note: The two writes must be consecutive, any intervening write to the register resets the sequence.
1011 *
1012 * @param base XRDC peripheral base address.
1013 * @param mem Which memory region's exclusive access lock to force release.
1014 */
1015 void XRDC_ForceMemExclAccessLockRelease(XRDC_Type *base, xrdc_mem_t mem);
1016
1017 /*!
1018 * @brief Gets the exclusive access lock domain owner of the memory region.
1019 *
1020 * This function returns the domain ID of the exclusive access lock owner of the memory region.
1021 *
1022 * @param base XRDC peripheral base address.
1023 * @param mem Which memory region's exclusive access lock domain owner to get.
1024 * @return Domain ID of the memory region exclusive access lock owner.
1025 */
XRDC_GetMemExclAccessLockDomainOwner(XRDC_Type * base,xrdc_mem_t mem)1026 static inline uint8_t XRDC_GetMemExclAccessLockDomainOwner(XRDC_Type *base, xrdc_mem_t mem)
1027 {
1028 return (uint8_t)((base->MRGD[mem].MRGD_W[2U] & XRDC_MRGD_W_EALO_MASK) >> XRDC_MRGD_W_EALO_SHIFT);
1029 }
1030 #endif /* FSL_FEATURE_XRDC_HAS_MRGD_EAL */
1031
1032 #if (defined(FSL_FEATURE_XRDC_HAS_MRGD_ACCSET) && FSL_FEATURE_XRDC_HAS_MRGD_ACCSET)
1033 /*!
1034 * @brief Sets the memory region ACCSET (programmable access flags) lock.
1035 *
1036 * @param base XRDC peripheral base address.
1037 * @param mem Which memory region descriptor to lock.
1038 * @param mem Which set/index of ACCSET to lock.
1039 * @param lock True to set lock, false to set unlock.
1040 */
1041 void XRDC_SetMemAccsetLock(XRDC_Type *base, xrdc_mem_t mem, xrdc_mem_accset_t accset, bool lock);
1042 #endif /* FSL_FEATURE_XRDC_HAS_MRGD_ACCSET */
1043
1044 /*@}*/
1045
1046 /*!
1047 * @name XRDC Peripheral Access Controller (XRDC_PAC)
1048 * @{
1049 */
1050
1051 /*!
1052 * @brief Gets the default peripheral access configuration.
1053 *
1054 * The default configuration is set as follows:
1055 * @code
1056 * config->enableSema = false;
1057 * config->semaNum = 0U;
1058 * config->lockMode = kXRDC_AccessConfigLockWritable;
1059 * config->policy[0] = kXRDC_AccessPolicyNone;
1060 * config->policy[1] = kXRDC_AccessPolicyNone;
1061 * ...
1062 * config->policy[15] = kXRDC_AccessPolicyNone;
1063 * @endcode
1064 *
1065 * @param config Pointer to the configuration structure.
1066 */
1067 void XRDC_GetPeriphAccessDefaultConfig(xrdc_periph_access_config_t *config);
1068
1069 /*!
1070 * @brief Sets the peripheral access configuration.
1071 *
1072 * This function sets the peripheral access configuration as valid. Two
1073 * methods to use it:
1074 * Method 1: Set for one peripheral, which is used for runtime settings.
1075 * @code
1076 * xrdc_periph_access_config_t config;
1077 *
1078 * // Set LPTMR0 accessible by domain 0
1079 * config.periph = kXRDC_PeriphLptmr0;
1080 * config.policy[0] = kXRDC_AccessPolicyAll;
1081 * XRDC_SetPeriphAccessConfig(XRDC, &config);
1082 * @endcode
1083 *
1084 * Method 2: Set for multiple peripherals, which is used for initialization settings.
1085 * @code
1086 * // Prepare the configurations
1087 * xrdc_periph_access_config_t configs[] =
1088 * {
1089 * {
1090 * .periph = kXRDC_PeriphLptmr0,
1091 * .policy[0] = kXRDC_AccessPolicyAll,
1092 * .policy[1] = kXRDC_AccessPolicyAll
1093 * },
1094 * {
1095 * .periph = kXRDC_PeriphLpuart0,
1096 * .policy[0] = kXRDC_AccessPolicyAll,
1097 * .policy[1] = kXRDC_AccessPolicyAll
1098 * }
1099 * };
1100 *
1101 * // Set the configurations.
1102 * for (i=0U; i<(sizeof(configs)/sizeof(configs[0])), i++)
1103 * {
1104 * XRDC_SetPeriphAccessConfig(XRDC, &config[i]);
1105 * }
1106 * @endcode
1107 *
1108 * @param base XRDC peripheral base address.
1109 * @param config Pointer to the configuration structure.
1110 */
1111 void XRDC_SetPeriphAccessConfig(XRDC_Type *base, const xrdc_periph_access_config_t *config);
1112
1113 /*!
1114 * @brief Sets the peripheral access configuration register lock mode.
1115 *
1116 * @param base XRDC peripheral base address.
1117 * @param periph Which peripheral access configuration register to lock.
1118 * @param lockMode The lock mode to set.
1119 */
XRDC_SetPeriphAccessLockMode(XRDC_Type * base,xrdc_periph_t periph,xrdc_access_config_lock_t lockMode)1120 static inline void XRDC_SetPeriphAccessLockMode(XRDC_Type *base,
1121 xrdc_periph_t periph,
1122 xrdc_access_config_lock_t lockMode)
1123 {
1124 uint32_t reg = base->PDAC_W[periph][1];
1125
1126 #if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL)
1127 /* If there is PDAC_W1[EAL], should not write non-zero value to EAL. */
1128 reg = ((reg & ~(XRDC_PDAC_W_LK2_MASK | XRDC_PDAC_W_EAL_MASK)) | XRDC_PDAC_W_LK2(lockMode));
1129 #else
1130 reg = ((reg & ~XRDC_PDAC_W_LK2_MASK) | XRDC_PDAC_W_LK2(lockMode));
1131 #endif
1132
1133 base->PDAC_W[periph][1] = reg;
1134 }
1135
1136 /*!
1137 * @brief Sets the peripheral access as valid or invalid.
1138 *
1139 * This function sets the peripheral access configuration dynamically. For example:
1140 *
1141 * @code
1142 * // Set LPTMR0 accessible by domain 0.
1143 * xrdc_periph_access_config_t config =
1144 * {
1145 * .periph = kXRDC_PeriphLptmr0;
1146 * .policy[0] = kXRDC_AccessPolicyAll;
1147 * };
1148 * XRDC_SetPeriphAccessConfig(XRDC, &config);
1149 *
1150 * // Set the LPTMR0 access configuration invalid.
1151 * XRDC_SetPeriphAccessValid(kXrdcPeriLptmr0, false);
1152 *
1153 * // Set the LPTMR0 access configuration valid, the LPTMR0 accessible by domain 0.
1154 * XRDC_SetPeriphAccessValid(kXrdcPeriLptmr0, true);
1155 * @endcode
1156 *
1157 * @param base XRDC peripheral base address.
1158 * @param periph Which peripheral access configuration to set.
1159 * @param valid True to set valid, false to set invalid.
1160 */
XRDC_SetPeriphAccessValid(XRDC_Type * base,xrdc_periph_t periph,bool valid)1161 static inline void XRDC_SetPeriphAccessValid(XRDC_Type *base, xrdc_periph_t periph, bool valid)
1162 {
1163 #if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL)
1164 /* If there is PDAC_W1[EAL], should not write non-zero value to EAL. */
1165 uint32_t reg = base->PDAC_W[periph][1] & ~XRDC_PDAC_W_EAL_MASK;
1166
1167 if (valid)
1168 {
1169 base->PDAC_W[periph][1] = reg | XRDC_PDAC_W_VLD_MASK;
1170 }
1171 else
1172 {
1173 base->PDAC_W[periph][1] = reg & ~XRDC_PDAC_W_VLD_MASK;
1174 }
1175 #else
1176 if (valid)
1177 {
1178 base->PDAC_W[periph][1] |= XRDC_PDAC_W_VLD_MASK;
1179 }
1180 else
1181 {
1182 base->PDAC_W[periph][1] &= ~XRDC_PDAC_W_VLD_MASK;
1183 }
1184 #endif
1185 }
1186
1187 #if (defined(FSL_FEATURE_XRDC_HAS_PDAC_EAL) && FSL_FEATURE_XRDC_HAS_PDAC_EAL)
1188 /*!
1189 * @brief Sets the peripheral exclusive access lock mode configuration.
1190 *
1191 * @param base XRDC peripheral base address.
1192 * @param periph Which peripheral's exclusive access lock mode to configure.
1193 * @param lockMode The exclusive access lock mode to set.
1194 */
XRDC_SetPeriphExclAccessLockMode(XRDC_Type * base,xrdc_periph_t periph,xrdc_excl_access_lock_config_t lockMode)1195 static inline void XRDC_SetPeriphExclAccessLockMode(XRDC_Type *base,
1196 xrdc_periph_t periph,
1197 xrdc_excl_access_lock_config_t lockMode)
1198 {
1199 /* Write kXRDC_ExclAccessLockDisabled is not allowed. */
1200 assert(kXRDC_ExclAccessLockDisabled != lockMode);
1201
1202 uint32_t reg = base->PDAC_W[periph][1];
1203
1204 reg = ((reg & ~XRDC_PDAC_W_EAL_MASK) | XRDC_PDAC_W_EAL(lockMode));
1205
1206 base->PDAC_W[periph][1] = reg;
1207 }
1208
1209 /*!
1210 * @brief Forces the release of the peripheral exclusive access lock.
1211 *
1212 * A lock can be forced to the available state (EAL=10) by a domain that does not own the
1213 * lock through the forced lock release procedure:
1214 * The procedure to force a exclusive access lock release is as follows:
1215 * 1. Write 0x02000046 to W1 register (PAC/MSC) or W3 register (MRC)
1216 * 2. Write 0x02000052 to W1 register (PAC/MSC) or W3 register (MRC)
1217 *
1218 * Note: The two writes must be consecutive, any intervening write to the register resets the sequence.
1219 *
1220 * @param base XRDC peripheral base address.
1221 * @param periph Which peripheral's exclusive access lock to force release.
1222 */
1223 void XRDC_ForcePeriphExclAccessLockRelease(XRDC_Type *base, xrdc_periph_t periph);
1224
1225 /*!
1226 * @brief Gets the exclusive access lock domain owner of the peripheral.
1227 *
1228 * This function returns the domain ID of the exclusive access lock owner of the peripheral.
1229 *
1230 * @param base XRDC peripheral base address.
1231 * @param periph Which peripheral's exclusive access lock domain owner to get.
1232 * @return Domain ID of the peripheral exclusive access lock owner.
1233 */
XRDC_GetPeriphExclAccessLockDomainOwner(XRDC_Type * base,xrdc_periph_t periph)1234 static inline uint8_t XRDC_GetPeriphExclAccessLockDomainOwner(XRDC_Type *base, xrdc_periph_t periph)
1235 {
1236 return (uint8_t)((base->PDAC_W[periph][0U] & XRDC_PDAC_W_EALO_MASK) >> XRDC_PDAC_W_EALO_SHIFT);
1237 }
1238 #endif /* FSL_FEATURE_XRDC_HAS_PDAC_EAL */
1239 /*@}*/
1240
1241 #if defined(__cplusplus)
1242 }
1243 #endif
1244
1245 /*!
1246 * @}
1247 */
1248
1249 #endif /* _FSL_XRDC_H_ */
1250
