1/* SPDX-License-Identifier: Apache-2.0 */
2
3#include <arm/armv7-m.dtsi>
4#include <mem.h>
5#include <freq.h>
6#include <zephyr/dt-bindings/i2c/i2c.h>
7#include <zephyr/dt-bindings/gpio/gpio.h>
8
9/ {
10	clocks {
11		uartclk: apb-pclk {
12			compatible = "fixed-clock";
13			clock-frequency = <DT_FREQ_M(24)>;
14			#clock-cells = <0>;
15		};
16		xo32m: xo32m {
17			compatible = "ambiq,clkctrl";
18			clock-frequency = <DT_FREQ_M(32)>;
19			#clock-cells = <1>;
20		};
21		xo32k: xo32k {
22			compatible = "ambiq,clkctrl";
23			clock-frequency = <DT_FREQ_K(32)>;
24			#clock-cells = <1>;
25		};
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu0: cpu@0 {
33			compatible = "arm,cortex-m4f";
34			reg = <0>;
35			#address-cells = <1>;
36			#size-cells = <1>;
37
38			itm: itm@e0000000 {
39				compatible = "arm,armv7m-itm";
40				reg = <0xe0000000 0x1000>;
41				swo-ref-frequency = <DT_FREQ_M(48)>;
42			};
43		};
44	};
45
46	/* TCM */
47	tcm: tcm@10000000 {
48		compatible = "zephyr,memory-region";
49		reg = <0x10000000 0x10000>;
50		zephyr,memory-region = "ITCM";
51	};
52
53	/* SRAM */
54	sram0: memory@10010000 {
55		compatible = "mmio-sram";
56		reg = <0x10010000 0x2B0000>;
57	};
58
59	soc {
60		compatible = "ambiq,apollo4p-blue", "ambiq,apollo4x", "simple-bus";
61
62		flash: flash-controller@18000 {
63			compatible = "ambiq,flash-controller";
64			reg = <0x00018000 0x1e8000>;
65
66			#address-cells = <1>;
67			#size-cells = <1>;
68
69			/* MRAM region */
70			flash0: flash@18000 {
71				compatible = "soc-nv-flash";
72				reg = <0x00018000 0x1e8000>;
73			};
74		};
75
76		pwrcfg: pwrcfg@40021000 {
77			compatible = "ambiq,pwrctrl";
78			reg = <0x40021000 0x400>;
79			#pwrcfg-cells = <2>;
80		};
81
82		stimer0: stimer@40008800 {
83			compatible = "ambiq,stimer";
84			reg = <0x40008800 0x80>;
85			interrupts = <32 0>;
86			status = "okay";
87		};
88
89		counter0: counter@40008200 {
90			compatible = "ambiq,counter";
91			reg = <0x40008200 0x20>;
92			interrupts = <67 0>;
93			clock-frequency = <DT_FREQ_M(6)>;
94			clk-source = <1>;
95			status = "disabled";
96		};
97
98		uart0: uart@4001c000 {
99			compatible = "ambiq,uart", "arm,pl011";
100			reg = <0x4001c000 0x1000>;
101			interrupts = <15 0>;
102			interrupt-names = "UART0";
103			status = "disabled";
104			clocks = <&uartclk>;
105			ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
106		};
107		uart1: uart@4001d000 {
108			compatible = "ambiq,uart", "arm,pl011";
109			reg = <0x4001d000 0x1000>;
110			interrupts = <16 0>;
111			interrupt-names = "UART1";
112			status = "disabled";
113			clocks = <&uartclk>;
114			ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
115		};
116
117		uart2: uart@4001e000 {
118			compatible = "ambiq,uart", "arm,pl011";
119			reg = <0x4001e000 0x1000>;
120			interrupts = <17 0>;
121			interrupt-names = "UART2";
122			status = "disabled";
123			clocks = <&uartclk>;
124			ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
125		};
126
127		uart3: uart@4001f000 {
128			compatible = "ambiq,uart", "arm,pl011";
129			reg = <0x4001f000 0x1000>;
130			interrupts = <18 0>;
131			interrupt-names = "UART3";
132			status = "disabled";
133			clocks = <&uartclk>;
134			ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
135		};
136
137		spi0: spi@40050000 {
138			reg = <0x40050000 0x1000>;
139			#address-cells = <1>;
140			#size-cells = <0>;
141			interrupts = <6 0>;
142			status = "disabled";
143			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
144		};
145
146		spi1: spi@40051000 {
147			reg = <0x40051000 0x1000>;
148			#address-cells = <1>;
149			#size-cells = <0>;
150			interrupts = <7 0>;
151			status = "disabled";
152			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
153		};
154
155		spi2: spi@40052000 {
156			reg = <0x40052000 0x1000>;
157			#address-cells = <1>;
158			#size-cells = <0>;
159			interrupts = <8 0>;
160			status = "disabled";
161			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
162		};
163
164		spi3: spi@40053000 {
165			reg = <0x40053000 0x1000>;
166			#address-cells = <1>;
167			#size-cells = <0>;
168			interrupts = <9 0>;
169			status = "disabled";
170			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
171		};
172
173		spi4: spi@40054000 {
174			/* IOM4 works as SPI and is wired internally for BLE HCI. */
175			compatible = "ambiq,spi";
176			reg = <0x40054000 0x1000>;
177			#address-cells = <1>;
178			#size-cells = <0>;
179			interrupts = <10 0>;
180			cs-gpios = <&gpio32_63 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
181			clock-frequency = <DT_FREQ_M(24)>;
182			status = "disabled";
183			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
184
185			bt_hci_apollo: bt-hci@0 {
186				compatible = "ambiq,bt-hci-spi";
187				reg = <0>;
188				spi-max-frequency = <DT_FREQ_M(24)>;
189				irq-gpios = <&gpio32_63 21 GPIO_ACTIVE_HIGH>;
190				reset-gpios = <&gpio32_63 23 GPIO_ACTIVE_LOW>;
191				clkreq-gpios = <&gpio32_63 20 GPIO_ACTIVE_HIGH>;
192			};
193		};
194
195		spi5: spi@40055000 {
196			reg = <0x40055000 0x1000>;
197			#address-cells = <1>;
198			#size-cells = <0>;
199			interrupts = <11 0>;
200			status = "disabled";
201			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
202		};
203
204		spi6: spi@40056000 {
205			reg = <0x40056000 0x1000>;
206			#address-cells = <1>;
207			#size-cells = <0>;
208			interrupts = <12 0>;
209			status = "disabled";
210			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
211		};
212
213		spi7: spi@40057000 {
214			reg = <0x40057000 0x1000>;
215			#address-cells = <1>;
216			#size-cells = <0>;
217			interrupts = <13 0>;
218			status = "disabled";
219			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
220		};
221
222		i2c0: i2c@40050000 {
223			reg = <0x40050000 0x1000>;
224			#address-cells = <1>;
225			#size-cells = <0>;
226			interrupts = <6 0>;
227			status = "disabled";
228			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
229		};
230
231		i2c1: i2c@40051000 {
232			reg = <0x40051000 0x1000>;
233			#address-cells = <1>;
234			#size-cells = <0>;
235			interrupts = <7 0>;
236			status = "disabled";
237			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
238		};
239
240		i2c2: i2c@40052000 {
241			reg = <0x40052000 0x1000>;
242			#address-cells = <1>;
243			#size-cells = <0>;
244			interrupts = <8 0>;
245			status = "disabled";
246			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
247		};
248
249		i2c3: i2c@40053000 {
250			reg = <0x40053000 0x1000>;
251			#address-cells = <1>;
252			#size-cells = <0>;
253			interrupts = <9 0>;
254			status = "disabled";
255			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
256		};
257
258		i2c4: i2c@40054000 {
259			reg = <0x40054000 0x1000>;
260			#address-cells = <1>;
261			#size-cells = <0>;
262			interrupts = <10 0>;
263			status = "disabled";
264			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
265		};
266
267		i2c5: i2c@40055000 {
268			reg = <0x40055000 0x1000>;
269			#address-cells = <1>;
270			#size-cells = <0>;
271			interrupts = <11 0>;
272			status = "disabled";
273			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
274		};
275
276		i2c6: i2c@40056000 {
277			reg = <0x40056000 0x1000>;
278			#address-cells = <1>;
279			#size-cells = <0>;
280			interrupts = <12 0>;
281			status = "disabled";
282			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
283		};
284
285		i2c7: i2c@40057000 {
286			reg = <0x40057000 0x1000>;
287			#address-cells = <1>;
288			#size-cells = <0>;
289			interrupts = <13 0>;
290			status = "disabled";
291			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
292		};
293
294		mspi0: spi@40060000 {
295			compatible = "ambiq,mspi";
296			reg = <0x40060000 0x400>;
297			interrupts = <20 0>;
298			#address-cells = <1>;
299			#size-cells = <0>;
300			status = "disabled";
301			ambiq,pwrcfg = <&pwrcfg 0x4 0x4000>;
302		};
303
304		mspi1: spi@40061000 {
305			compatible = "ambiq,mspi";
306			reg = <0x40061000 0x400>;
307			interrupts = <21 0>;
308			#address-cells = <1>;
309			#size-cells = <0>;
310			status = "disabled";
311			ambiq,pwrcfg = <&pwrcfg 0x4 0x8000>;
312		};
313
314		mspi2: spi@40062000 {
315			compatible = "ambiq,mspi";
316			reg = <0x40062000 0x400>;
317			interrupts = <22 0>;
318			#address-cells = <1>;
319			#size-cells = <0>;
320			status = "disabled";
321			ambiq,pwrcfg = <&pwrcfg 0x4 0x10000>;
322		};
323
324		usb: usb@400b0000 {
325			compatible = "ambiq,usb";
326			reg = <0x400B0000 0x4100>;
327			interrupts = <27 0>;
328			num-bidir-endpoints = <6>;
329			maximum-speed = "full-speed";
330			status = "disabled";
331			ambiq,pwrcfg = <&pwrcfg 0x4 0x400000>;
332		};
333
334		rtc0: rtc@40004800 {
335			compatible = "ambiq,rtc";
336			reg = <0x40004800 0x210>;
337			interrupts = <2 0>;
338			alarms-count = <1>;
339			status = "disabled";
340		};
341
342		pinctrl: pin-controller@40010000 {
343			compatible = "ambiq,apollo4-pinctrl";
344			reg = <0x40010000 0x800>;
345			#address-cells = <1>;
346			#size-cells = <0>;
347
348			gpio: gpio@40010000 {
349				compatible = "ambiq,gpio";
350				gpio-map-mask = <0xffffffe0 0xffffffc0>;
351				gpio-map-pass-thru = <0x1f 0x3f>;
352				gpio-map = <
353					0x00 0x0 &gpio0_31 0x0 0x0
354					0x20 0x0 &gpio32_63 0x0 0x0
355					0x40 0x0 &gpio64_95 0x0 0x0
356					0x60 0x0 &gpio96_127 0x0 0x0
357				>;
358				reg = <0x40010000>;
359				#gpio-cells = <2>;
360				#address-cells = <1>;
361				#size-cells = <0>;
362				ranges;
363
364				gpio0_31: gpio0_31@0 {
365					compatible = "ambiq,gpio-bank";
366					gpio-controller;
367					#gpio-cells = <2>;
368					reg = <0>;
369					interrupts = <56 0>;
370					status = "disabled";
371				};
372
373				gpio32_63: gpio32_63@80 {
374					compatible = "ambiq,gpio-bank";
375					gpio-controller;
376					#gpio-cells = <2>;
377					reg = <0x80>;
378					interrupts = <57 0>;
379					status = "disabled";
380				};
381
382				gpio64_95: gpio64_95@100 {
383					compatible = "ambiq,gpio-bank";
384					gpio-controller;
385					#gpio-cells = <2>;
386					reg = <0x100>;
387					interrupts = <58 0>;
388					status = "disabled";
389				};
390
391				gpio96_127: gpio96_127@180 {
392					compatible = "ambiq,gpio-bank";
393					gpio-controller;
394					#gpio-cells = <2>;
395					reg = <0x180>;
396					interrupts = <59 0>;
397					status = "disabled";
398				};
399			};
400		};
401
402		wdt0: watchdog@40024000 {
403			compatible = "ambiq,watchdog";
404			reg = <0x40024000 0x400>;
405			interrupts = <1 0>;
406			clock-frequency = <16>;
407			status = "disabled";
408		};
409
410	};
411};
412
413&nvic {
414	arm,num-irq-priority-bits = <3>;
415};
416