1 /* SPDX-License-Identifier: MIT */ 2 3 /****************************************************************************** 4 * arch-arm.h 5 * 6 * Guest OS interface to ARM Xen. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to 10 * deal in the Software without restriction, including without limitation the 11 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 12 * sell copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Copyright 2011 (C) Citrix Systems 27 */ 28 29 #ifndef __XEN_PUBLIC_ARCH_ARM_H__ 30 #define __XEN_PUBLIC_ARCH_ARM_H__ 31 32 #include <zephyr/kernel.h> 33 34 /* 35 * `incontents 50 arm_abi Hypercall Calling Convention 36 * 37 * A hypercall is issued using the ARM HVC instruction. 38 * 39 * A hypercall can take up to 5 arguments. These are passed in 40 * registers, the first argument in x0/r0 (for arm64/arm32 guests 41 * respectively irrespective of whether the underlying hypervisor is 42 * 32- or 64-bit), the second argument in x1/r1, the third in x2/r2, 43 * the forth in x3/r3 and the fifth in x4/r4. 44 * 45 * The hypercall number is passed in r12 (arm) or x16 (arm64). In both 46 * cases the relevant ARM procedure calling convention specifies this 47 * is an inter-procedure-call scratch register (e.g. for use in linker 48 * stubs). This use does not conflict with use during a hypercall. 49 * 50 * The HVC ISS must contain a Xen specific TAG: XEN_HYPERCALL_TAG. 51 * 52 * The return value is in x0/r0. 53 * 54 * The hypercall will clobber x16/r12 and the argument registers used 55 * by that hypercall (except r0 which is the return value) i.e. in 56 * addition to x16/r12 a 2 argument hypercall will clobber x1/r1 and a 57 * 4 argument hypercall will clobber x1/r1, x2/r2 and x3/r3. 58 * 59 * Parameter structs passed to hypercalls are laid out according to 60 * the Procedure Call Standard for the ARM Architecture (AAPCS, AKA 61 * EABI) and Procedure Call Standard for the ARM 64-bit Architecture 62 * (AAPCS64). Where there is a conflict the 64-bit standard should be 63 * used regardless of guest type. Structures which are passed as 64 * hypercall arguments are always little endian. 65 * 66 * All memory which is shared with other entities in the system 67 * (including the hypervisor and other guests) must reside in memory 68 * which is mapped as Normal Inner Write-Back Outer Write-Back Inner-Shareable. 69 * This applies to: 70 * - hypercall arguments passed via a pointer to guest memory. 71 * - memory shared via the grant table mechanism (including PV I/O 72 * rings etc). 73 * - memory shared with the hypervisor (struct shared_info, struct 74 * vcpu_info, the grant table, etc). 75 * 76 * Any cache allocation hints are acceptable. 77 */ 78 79 /* 80 * `incontents 55 arm_hcall Supported Hypercalls 81 * 82 * Xen on ARM makes extensive use of hardware facilities and therefore 83 * only a subset of the potential hypercalls are required. 84 * 85 * Since ARM uses second stage paging any machine/physical addresses 86 * passed to hypercalls are Guest Physical Addresses (Intermediate 87 * Physical Addresses) unless otherwise noted. 88 * 89 * The following hypercalls (and sub operations) are supported on the 90 * ARM platform. Other hypercalls should be considered 91 * unavailable/unsupported. 92 * 93 * HYPERVISOR_memory_op 94 * All generic sub-operations 95 * 96 * HYPERVISOR_domctl 97 * All generic sub-operations, with the exception of: 98 * * XEN_DOMCTL_irq_permission (not yet implemented) 99 * 100 * HYPERVISOR_sched_op 101 * All generic sub-operations, with the exception of: 102 * * SCHEDOP_block -- prefer wfi hardware instruction 103 * 104 * HYPERVISOR_console_io 105 * All generic sub-operations 106 * 107 * HYPERVISOR_xen_version 108 * All generic sub-operations 109 * 110 * HYPERVISOR_event_channel_op 111 * All generic sub-operations 112 * 113 * HYPERVISOR_physdev_op 114 * No sub-operations are currently supported 115 * 116 * HYPERVISOR_sysctl 117 * All generic sub-operations, with the exception of: 118 * * XEN_SYSCTL_page_offline_op 119 * * XEN_SYSCTL_get_pmstat 120 * * XEN_SYSCTL_pm_op 121 * 122 * HYPERVISOR_hvm_op 123 * Exactly these sub-operations are supported: 124 * * HVMOP_set_param 125 * * HVMOP_get_param 126 * 127 * HYPERVISOR_grant_table_op 128 * All generic sub-operations 129 * 130 * HYPERVISOR_vcpu_op 131 * Exactly these sub-operations are supported: 132 * * VCPUOP_register_vcpu_info 133 * * VCPUOP_register_runstate_memory_area 134 * 135 * 136 * Other notes on the ARM ABI: 137 * 138 * - struct start_info is not exported to ARM guests. 139 * 140 * - struct shared_info is mapped by ARM guests using the 141 * HYPERVISOR_memory_op sub-op XENMEM_add_to_physmap, passing 142 * XENMAPSPACE_shared_info as space parameter. 143 * 144 * - All the per-cpu struct vcpu_info are mapped by ARM guests using the 145 * HYPERVISOR_vcpu_op sub-op VCPUOP_register_vcpu_info, including cpu0 146 * struct vcpu_info. 147 * 148 * - The grant table is mapped using the HYPERVISOR_memory_op sub-op 149 * XENMEM_add_to_physmap, passing XENMAPSPACE_grant_table as space 150 * parameter. The memory range specified under the Xen compatible 151 * hypervisor node on device tree can be used as target gpfn for the 152 * mapping. 153 * 154 * - Xenstore is initialized by using the two hvm_params 155 * HVM_PARAM_STORE_PFN and HVM_PARAM_STORE_EVTCHN. They can be read 156 * with the HYPERVISOR_hvm_op sub-op HVMOP_get_param. 157 * 158 * - The paravirtualized console is initialized by using the two 159 * hvm_params HVM_PARAM_CONSOLE_PFN and HVM_PARAM_CONSOLE_EVTCHN. They 160 * can be read with the HYPERVISOR_hvm_op sub-op HVMOP_get_param. 161 * 162 * - Event channel notifications are delivered using the percpu GIC 163 * interrupt specified under the Xen compatible hypervisor node on 164 * device tree. 165 * 166 * - The device tree Xen compatible node is fully described under Linux 167 * at Documentation/devicetree/bindings/arm/xen.txt. 168 */ 169 170 #define XEN_HYPERCALL_TAG 0XEA1 171 172 #define int64_aligned_t int64_t __aligned(8) 173 #define uint64_aligned_t uint64_t __aligned(8) 174 175 #ifndef __ASSEMBLY__ 176 #define ___DEFINE_XEN_GUEST_HANDLE(name, type) \ 177 typedef union { type *p; unsigned long q; } \ 178 __guest_handle_ ## name; \ 179 typedef union { type *p; uint64_aligned_t q; } \ 180 __guest_handle_64_ ## name 181 182 /* 183 * XEN_GUEST_HANDLE represents a guest pointer, when passed as a field 184 * in a struct in memory. On ARM is always 8 bytes sizes and 8 bytes 185 * aligned. 186 * XEN_GUEST_HANDLE_PARAM represents a guest pointer, when passed as an 187 * hypercall argument. It is 4 bytes on aarch32 and 8 bytes on aarch64. 188 */ 189 #define __DEFINE_XEN_GUEST_HANDLE(name, type) \ 190 ___DEFINE_XEN_GUEST_HANDLE(name, type); \ 191 ___DEFINE_XEN_GUEST_HANDLE(const_##name, const type) 192 #define DEFINE_XEN_GUEST_HANDLE(name) __DEFINE_XEN_GUEST_HANDLE(name, name) 193 #define __XEN_GUEST_HANDLE(name) __guest_handle_64_ ## name 194 #define XEN_GUEST_HANDLE(name) __XEN_GUEST_HANDLE(name) 195 #define XEN_GUEST_HANDLE_PARAM(name) __guest_handle_ ## name 196 #define set_xen_guest_handle_raw(hnd, val) \ 197 do { \ 198 __typeof__(&(hnd)) _sxghr_tmp = &(hnd); \ 199 _sxghr_tmp->q = 0; \ 200 _sxghr_tmp->p = val; \ 201 } while (0) 202 #define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val) 203 204 typedef uint64_t xen_pfn_t; 205 #define PRI_xen_pfn PRIx64 206 #define PRIu_xen_pfn PRIu64 207 208 /* 209 * Maximum number of virtual CPUs in legacy multi-processor guests. 210 * Only one. All other VCPUS must use VCPUOP_register_vcpu_info. 211 */ 212 #define XEN_LEGACY_MAX_VCPUS 1 213 214 typedef uint64_t xen_ulong_t; 215 #define PRI_xen_ulong PRIx64 216 217 #ifdef CONFIG_XEN_DOM0 218 #if defined(__GNUC__) && !defined(__STRICT_ANSI__) 219 /* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */ 220 # define __DECL_REG(n64, n32) union { \ 221 uint64_t n64; \ 222 uint32_t n32; \ 223 } 224 #else 225 /* Non-gcc sources must always use the proper 64-bit name (e.g., x0). */ 226 #define __DECL_REG(n64, n32) uint64_t n64 227 #endif 228 229 struct vcpu_guest_core_regs { 230 /* Aarch64 Aarch32 */ 231 __DECL_REG(x0, r0_usr); 232 __DECL_REG(x1, r1_usr); 233 __DECL_REG(x2, r2_usr); 234 __DECL_REG(x3, r3_usr); 235 __DECL_REG(x4, r4_usr); 236 __DECL_REG(x5, r5_usr); 237 __DECL_REG(x6, r6_usr); 238 __DECL_REG(x7, r7_usr); 239 __DECL_REG(x8, r8_usr); 240 __DECL_REG(x9, r9_usr); 241 __DECL_REG(x10, r10_usr); 242 __DECL_REG(x11, r11_usr); 243 __DECL_REG(x12, r12_usr); 244 245 __DECL_REG(x13, sp_usr); 246 __DECL_REG(x14, lr_usr); 247 248 __DECL_REG(x15, __unused_sp_hyp); 249 250 __DECL_REG(x16, lr_irq); 251 __DECL_REG(x17, sp_irq); 252 253 __DECL_REG(x18, lr_svc); 254 __DECL_REG(x19, sp_svc); 255 256 __DECL_REG(x20, lr_abt); 257 __DECL_REG(x21, sp_abt); 258 259 __DECL_REG(x22, lr_und); 260 __DECL_REG(x23, sp_und); 261 262 __DECL_REG(x24, r8_fiq); 263 __DECL_REG(x25, r9_fiq); 264 __DECL_REG(x26, r10_fiq); 265 __DECL_REG(x27, r11_fiq); 266 __DECL_REG(x28, r12_fiq); 267 268 __DECL_REG(x29, sp_fiq); 269 __DECL_REG(x30, lr_fiq); 270 271 /* Return address and mode */ 272 __DECL_REG(pc64, pc32); /* ELR_EL2 */ 273 uint32_t cpsr; /* SPSR_EL2 */ 274 275 union { 276 uint32_t spsr_el1; /* AArch64 */ 277 uint32_t spsr_svc; /* AArch32 */ 278 }; 279 280 /* AArch32 guests only */ 281 uint32_t spsr_fiq, spsr_irq, spsr_und, spsr_abt; 282 283 /* AArch64 guests only */ 284 uint64_t sp_el0; 285 uint64_t sp_el1, elr_el1; 286 }; 287 typedef struct vcpu_guest_core_regs vcpu_guest_core_regs_t; 288 DEFINE_XEN_GUEST_HANDLE(vcpu_guest_core_regs_t); 289 290 #undef __DECL_REG 291 292 struct vcpu_guest_context { 293 #define _VGCF_online 0 294 #define VGCF_online (1 << _VGCF_online) 295 uint32_t flags; /* VGCF_* */ 296 297 struct vcpu_guest_core_regs user_regs; /* Core CPU registers */ 298 299 uint64_t sctlr; 300 uint64_t ttbcr, ttbr0, ttbr1; 301 }; 302 typedef struct vcpu_guest_context vcpu_guest_context_t; 303 DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); 304 305 /* 306 * struct xen_arch_domainconfig's ABI is covered by 307 * XEN_DOMCTL_INTERFACE_VERSION. 308 */ 309 #define XEN_DOMCTL_CONFIG_GIC_NATIVE 0 310 #define XEN_DOMCTL_CONFIG_GIC_V2 1 311 #define XEN_DOMCTL_CONFIG_GIC_V3 2 312 313 #define XEN_DOMCTL_CONFIG_TEE_NONE 0 314 #define XEN_DOMCTL_CONFIG_TEE_OPTEE 1 315 316 struct xen_arch_domainconfig { 317 /* IN/OUT */ 318 uint8_t gic_version; 319 /* IN */ 320 uint16_t tee_type; 321 /* IN */ 322 uint32_t nr_spis; 323 /* 324 * OUT 325 * Based on the property clock-frequency in the DT timer node. 326 * The property may be present when the bootloader/firmware doesn't 327 * set correctly CNTFRQ which hold the timer frequency. 328 * 329 * As it's not possible to trap this register, we have to replicate 330 * the value in the guest DT. 331 * 332 * = 0 => property not present 333 * > 0 => Value of the property 334 * 335 */ 336 uint32_t clock_frequency; 337 }; 338 #endif /* CONFIG_XEN_DOM0 */ 339 340 struct arch_vcpu_info { 341 }; 342 typedef struct arch_vcpu_info arch_vcpu_info_t; 343 344 struct arch_shared_info { 345 }; 346 typedef struct arch_shared_info arch_shared_info_t; 347 typedef uint64_t xen_callback_t; 348 349 #endif /* __ASSEMBLY__ */ 350 351 #ifdef CONFIG_XEN_DOM0 352 353 /* PSR bits (CPSR, SPSR) */ 354 #define PSR_THUMB (1 << 5) /* Thumb Mode enable */ 355 #define PSR_FIQ_MASK (1 << 6) /* Fast Interrupt mask */ 356 #define PSR_IRQ_MASK (1 << 7) /* Interrupt mask */ 357 #define PSR_ABT_MASK (1 << 8) /* Asynchronous Abort mask */ 358 #define PSR_BIG_ENDIAN (1 << 9) /* arm32: Big Endian Mode */ 359 #define PSR_DBG_MASK (1 << 9) /* arm64: Debug Exception mask */ 360 #define PSR_IT_MASK (0x0600fc00) /* Thumb If-Then Mask */ 361 #define PSR_JAZELLE (1<<24) /* Jazelle Mode */ 362 363 /* 32 bit modes */ 364 #define PSR_MODE_USR 0x10 365 #define PSR_MODE_FIQ 0x11 366 #define PSR_MODE_IRQ 0x12 367 #define PSR_MODE_SVC 0x13 368 #define PSR_MODE_MON 0x16 369 #define PSR_MODE_ABT 0x17 370 #define PSR_MODE_HYP 0x1a 371 #define PSR_MODE_UND 0x1b 372 #define PSR_MODE_SYS 0x1f 373 374 /* 64 bit modes */ 375 #define PSR_MODE_BIT 0x10 /* Set iff AArch32 */ 376 #define PSR_MODE_EL3h 0x0d 377 #define PSR_MODE_EL3t 0x0c 378 #define PSR_MODE_EL2h 0x09 379 #define PSR_MODE_EL2t 0x08 380 #define PSR_MODE_EL1h 0x05 381 #define PSR_MODE_EL1t 0x04 382 #define PSR_MODE_EL0t 0x00 383 384 #define PSR_GUEST32_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC) 385 #define PSR_GUEST64_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_EL1h) 386 387 #define SCTLR_GUEST_INIT xen_mk_ullong(0x00c50078) 388 389 /* 390 * Virtual machine platform (memory layout, interrupts) 391 * 392 * These are defined for consistency between the tools and the 393 * hypervisor. Guests must not rely on these hardcoded values but 394 * should instead use the FDT. 395 */ 396 397 /* Physical Address Space */ 398 399 /* 400 * vGIC mappings: Only one set of mapping is used by the guest. 401 * Therefore they can overlap. 402 */ 403 404 /* vGIC v2 mappings */ 405 #define GUEST_GICD_BASE xen_mk_ullong(0x03001000) 406 #define GUEST_GICD_SIZE xen_mk_ullong(0x00001000) 407 #define GUEST_GICC_BASE xen_mk_ullong(0x03002000) 408 #define GUEST_GICC_SIZE xen_mk_ullong(0x00002000) 409 410 /* vGIC v3 mappings */ 411 #define GUEST_GICV3_GICD_BASE xen_mk_ullong(0x03001000) 412 #define GUEST_GICV3_GICD_SIZE xen_mk_ullong(0x00010000) 413 414 #define GUEST_GICV3_RDIST_REGIONS 1 415 416 #define GUEST_GICV3_GICR0_BASE xen_mk_ullong(0x03020000) /* vCPU0..127 */ 417 #define GUEST_GICV3_GICR0_SIZE xen_mk_ullong(0x01000000) 418 419 /* ACPI tables physical address */ 420 #define GUEST_ACPI_BASE xen_mk_ullong(0x20000000) 421 #define GUEST_ACPI_SIZE xen_mk_ullong(0x02000000) 422 423 /* PL011 mappings */ 424 #define GUEST_PL011_BASE xen_mk_ullong(0x22000000) 425 #define GUEST_PL011_SIZE xen_mk_ullong(0x00001000) 426 427 /* 428 * 16MB == 4096 pages reserved for guest to use as a region to map its 429 * grant table in. 430 */ 431 #define GUEST_GNTTAB_BASE xen_mk_ullong(0x38000000) 432 #define GUEST_GNTTAB_SIZE xen_mk_ullong(0x01000000) 433 434 #define GUEST_MAGIC_BASE xen_mk_ullong(0x39000000) 435 #define GUEST_MAGIC_SIZE xen_mk_ullong(0x01000000) 436 437 #define GUEST_RAM_BANKS 2 438 439 #define GUEST_RAM0_BASE xen_mk_ullong(0x40000000) /* 3GB of low RAM @ 1GB */ 440 #define GUEST_RAM0_SIZE xen_mk_ullong(0xc0000000) 441 442 #define GUEST_RAM1_BASE xen_mk_ullong(0x0200000000) /* 1016GB of RAM @ 8GB */ 443 #define GUEST_RAM1_SIZE xen_mk_ullong(0xfe00000000) 444 445 #define GUEST_RAM_BASE GUEST_RAM0_BASE /* Lowest RAM address */ 446 /* Largest amount of actual RAM, not including holes */ 447 #define GUEST_RAM_MAX (GUEST_RAM0_SIZE + GUEST_RAM1_SIZE) 448 /* Suitable for e.g. const uint64_t ramfoo[] = GUEST_RAM_BANK_FOOS; */ 449 #define GUEST_RAM_BANK_BASES { GUEST_RAM0_BASE, GUEST_RAM1_BASE } 450 #define GUEST_RAM_BANK_SIZES { GUEST_RAM0_SIZE, GUEST_RAM1_SIZE } 451 452 /* Current supported guest VCPUs */ 453 #define GUEST_MAX_VCPUS 128 454 455 /* Interrupts */ 456 #define GUEST_TIMER_VIRT_PPI 27 457 #define GUEST_TIMER_PHYS_S_PPI 29 458 #define GUEST_TIMER_PHYS_NS_PPI 30 459 #define GUEST_EVTCHN_PPI 31 460 461 #define GUEST_VPL011_SPI 32 462 463 /* PSCI functions */ 464 #define PSCI_cpu_suspend 0 465 #define PSCI_cpu_off 1 466 #define PSCI_cpu_on 2 467 #define PSCI_migrate 3 468 469 #endif /* CONFIG_XEN_DOM0 */ 470 471 #ifndef __ASSEMBLY__ 472 /* Stub definition of PMU structure */ 473 typedef struct xen_pmu_arch { uint8_t dummy; } xen_pmu_arch_t; 474 #endif /* __ASSEMBLY__ */ 475 476 #endif /* __XEN_PUBLIC_ARCH_ARM_H__ */ 477
