1 /* 2 * Copyright 2016-2017 NXP 3 * 4 * Redistribution and use in source and binary forms, with or without modification, 5 * are permitted provided that the following conditions are met: 6 * 7 * o Redistributions of source code must retain the above copyright notice, this list 8 * of conditions and the following disclaimer. 9 * 10 * o Redistributions in binary form must reproduce the above copyright notice, this 11 * list of conditions and the following disclaimer in the documentation and/or 12 * other materials provided with the distribution. 13 * 14 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 15 * contributors may be used to endorse or promote products derived from this 16 * software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include "fsl_xcvr.h" 31 32 /******************************************************************************* 33 * Definitions 34 ******************************************************************************/ 35 36 /******************************************************************************* 37 * Prototypes 38 ******************************************************************************/ 39 40 /******************************************************************************* 41 * Variables 42 ******************************************************************************/ 43 44 /******************************************************************************* 45 * Code 46 ******************************************************************************/ 47 /* MODE only configuration */ 48 const xcvr_mode_config_t msk_mode_config = 49 { 50 .radio_mode = MSK, 51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, 52 53 /* XCVR_MISC configs */ 54 .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | 55 XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | 56 XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, 57 .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(9) | 58 XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(4) | 59 XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), 60 61 /* XCVR_PHY configs */ 62 .phy_pre_ref0_init = 0x79CDEB38, 63 .phy_pre_ref1_init = 0xCE77DFF7, 64 .phy_pre_ref2_init = 0x0000CEB7, 65 66 .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | 67 XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 68 XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | 69 XCVR_PHY_CFG1_BSM_EN_BLE(0) | 70 XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | 71 XCVR_PHY_CFG1_CTS_THRESH(208U) | 72 XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), 73 74 .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) 75 #if !RADIO_IS_GEN_2P1 76 | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) 77 #endif /* !RADIO_IS_GEN_2P1 */ 78 , 79 80 /* XCVR_RX_DIG configs */ 81 .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ 82 XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ 83 XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), 84 85 .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ 86 XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ 87 88 .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), 89 90 /* XCVR_TSM configs */ 91 #if (DATA_PADDING_EN) 92 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), 93 #else 94 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), 95 #endif /* (DATA_PADDING_EN) */ 96 97 /* XCVR_TX_DIG configs */ 98 .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | 99 XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | 100 XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | 101 XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | 102 XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | 103 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | 104 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | 105 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | 106 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), 107 .tx_gfsk_coeff1_26mhz = 0, 108 .tx_gfsk_coeff2_26mhz = 0, 109 .tx_gfsk_coeff1_32mhz = 0, 110 .tx_gfsk_coeff2_32mhz = 0, 111 }; 112 113 /* MODE & DATA RATE combined configuration */ 114 const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config = 115 { 116 .radio_mode = MSK, 117 .data_rate = DR_1MBPS, 118 119 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, 120 .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ 121 .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, 122 .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ 123 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, 124 .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ 125 126 .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | 127 XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , 128 129 /* AGC configs */ 130 .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | 131 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 132 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 133 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 134 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 135 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 136 .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | 137 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 138 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 139 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 140 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 141 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 142 143 /* All constant values are represented as 16 bits, register writes will remove unused bits */ 144 /* MSK 1MBPS channel filter @ 26MHz RF OSC */ 145 .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, 146 .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002, 147 .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000, 148 .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9, 149 .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0, 150 .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA, 151 .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, 152 .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC, 153 .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B, 154 .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042, 155 .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066, 156 .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C, 157 158 /* MSK 1MBPS channel filter @ 32MHz RF OSC */ 159 .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, 160 .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, 161 .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002, 162 .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC, 163 .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, 164 .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, 165 .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9, 166 .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7, 167 .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016, 168 .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040, 169 .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, 170 .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082, 171 172 .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | 173 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | 174 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | 175 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | 176 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | 177 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | 178 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | 179 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , 180 .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | 181 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | 182 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | 183 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | 184 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | 185 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , 186 187 .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), 188 .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), 189 }; 190 191 const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config = 192 { 193 .radio_mode = MSK, 194 .data_rate = DR_500KBPS, 195 196 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, 197 .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ 198 .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, 199 .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 200 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, 201 .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 202 203 .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | 204 XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xa) , 205 206 /* AGC configs */ 207 .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | 208 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 209 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 210 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 211 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 212 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 213 .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | 214 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 215 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 216 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 217 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 218 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 219 220 /* All constant values are represented as 16 bits, register writes will remove unused bits */ 221 /* MSK 500KBPS channel filter @ 26MHz RF OSC */ 222 .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, 223 .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, 224 .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, 225 .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, 226 .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFC, 227 .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, 228 .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, 229 .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE7, 230 .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, 231 .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0038, 232 .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, 233 .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0092, 234 235 /* MSK 500KBPS channel filter @ 32MHz RF OSC */ 236 .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, 237 .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002, 238 .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0006, 239 .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0009, 240 .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0003, 241 .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF3, 242 .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE2, 243 .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE0, 244 .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, 245 .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0031, 246 .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0071, 247 .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009C, 248 249 .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | 250 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | 251 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | 252 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | 253 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | 254 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | 255 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | 256 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , 257 .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | 258 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | 259 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | 260 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | 261 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | 262 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , 263 264 .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), 265 .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), 266 }; 267 268 const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config = 269 { 270 .radio_mode = MSK, 271 .data_rate = DR_250KBPS, 272 273 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, 274 .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ 275 .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, 276 .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 277 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, 278 .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 279 280 .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | 281 XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , 282 283 /* AGC configs */ 284 .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | 285 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 286 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | 287 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 288 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 289 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 290 .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | 291 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 292 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 293 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 294 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 295 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 296 297 /* All constant values are represented as 16 bits, register writes will remove unused bits */ 298 .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, 299 .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, 300 .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, 301 .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA, 302 .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, 303 .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019, 304 .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009, 305 .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB, 306 .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1, 307 .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6, 308 .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072, 309 .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD, 310 311 /* MSK 250KBPS channel filter @ 32MHz RF OSC */ 312 .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, 313 .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, 314 .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC, 315 .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, 316 .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD, 317 .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016, 318 .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A, 319 .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC, 320 .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC, 321 .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0, 322 .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, 323 .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED, 324 325 .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | 326 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | 327 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | 328 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | 329 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | 330 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | 331 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | 332 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , 333 .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | 334 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | 335 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | 336 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | 337 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | 338 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , 339 340 .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), 341 .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), 342 }; 343 344
