1 /* 2 * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 * Copyright 2016-2017 NXP 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * o Redistributions of source code must retain the above copyright notice, this list 9 * of conditions and the following disclaimer. 10 * 11 * o Redistributions in binary form must reproduce the above copyright notice, this 12 * list of conditions and the following disclaimer in the documentation and/or 13 * other materials provided with the distribution. 14 * 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "fsl_xcvr.h" 32 33 /******************************************************************************* 34 * Definitions 35 ******************************************************************************/ 36 37 /******************************************************************************* 38 * Prototypes 39 ******************************************************************************/ 40 41 /******************************************************************************* 42 * Variables 43 ******************************************************************************/ 44 45 /******************************************************************************* 46 * Code 47 ******************************************************************************/ 48 const xcvr_mode_config_t ble_mode_config = 49 { 50 .radio_mode = BLE_MODE, 51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_BTLL_MASK, 52 53 /* XCVR_MISC configs */ 54 .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | 55 XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | 56 XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, 57 .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(0) | 58 XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | 59 XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), 60 61 /* XCVR_PHY configs */ 62 .phy_pre_ref0_init = RW0PS(0, 0x19) | 63 RW0PS(1, 0x19U) | 64 RW0PS(2, 0x1AU) | 65 RW0PS(3, 0x1BU) | 66 RW0PS(4, 0x1CU) | 67 RW0PS(5, 0x1CU) | 68 RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */ 69 .phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/ 70 RW1PS(7, 0x1EU) | 71 RW1PS(8, 0x1EU) | 72 RW1PS(9, 0x1EU) | 73 RW1PS(10, 0x1DU) | 74 RW1PS(11, 0x1CU) | 75 RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */ 76 .phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/ 77 RW2PS(13, 0x1BU) | 78 RW2PS(14, 0x1AU) | 79 RW2PS(15, 0x19U), 80 81 .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | 82 XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 83 XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | 84 XCVR_PHY_CFG1_BSM_EN_BLE(0) | 85 XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | 86 XCVR_PHY_CFG1_CTS_THRESH(220) | 87 XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), 88 89 .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) /* Per SMB */ 90 #if !RADIO_IS_GEN_2P1 91 | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) 92 #endif /* !RADIO_IS_GEN_2P1 */ 93 , 94 95 /* XCVR_RX_DIG configs */ 96 .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ 97 XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ 98 XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), 99 100 .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ 101 XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ 102 103 .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), 104 /* XCVR_TSM configs */ 105 #if (DATA_PADDING_EN) 106 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), 107 #else 108 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), 109 #endif /* (DATA_PADDING_EN) */ 110 111 /* XCVR_TX_DIG configs */ 112 .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | 113 XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | 114 XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | 115 XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | 116 XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | 117 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | 118 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | 119 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | 120 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), 121 .tx_gfsk_coeff1_26mhz = 0, 122 .tx_gfsk_coeff2_26mhz = 0, 123 .tx_gfsk_coeff1_32mhz = 0, 124 .tx_gfsk_coeff2_32mhz = 0, 125 }; 126 127 /* MODE & DATA RATE combined configuration */ 128 const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config = 129 { 130 .radio_mode = BLE_MODE, 131 .data_rate = DR_1MBPS, 132 133 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, 134 .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ 135 .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, 136 .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ 137 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, 138 .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /* TZA_BW_SEL */ 139 140 .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | 141 XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , 142 143 /* AGC configs */ 144 .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | 145 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 146 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 147 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 148 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 149 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 150 .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | 151 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 152 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 153 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 154 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 155 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 156 157 /* BLE 26MHz Channel Filter */ 158 /* All constant values are represented as 16 bits, register writes will remove unused bits */ 159 .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA, 160 .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6, 161 .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1, 162 .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE, 163 .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF, 164 .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6, 165 .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004, 166 .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017, 167 .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, 168 .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, 169 .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, 170 .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063, 171 172 /* BLE 32MHz Channel Filter */ 173 .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, 174 .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5, 175 .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF, 176 .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB, 177 .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB, 178 .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, 179 .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000, 180 .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, 181 .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030, 182 .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A, 183 .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, 184 .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B, 185 186 .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | 187 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | 188 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | 189 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | 190 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | 191 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | 192 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | 193 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , 194 .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | 195 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | 196 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | 197 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | 198 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | 199 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , 200 }; 201 202
