1 /* 2 * Copyright 2016-2017 NXP 3 * 4 * Redistribution and use in source and binary forms, with or without modification, 5 * are permitted provided that the following conditions are met: 6 * 7 * o Redistributions of source code must retain the above copyright notice, this list 8 * of conditions and the following disclaimer. 9 * 10 * o Redistributions in binary form must reproduce the above copyright notice, this 11 * list of conditions and the following disclaimer in the documentation and/or 12 * other materials provided with the distribution. 13 * 14 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 15 * contributors may be used to endorse or promote products derived from this 16 * software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include "fsl_xcvr.h" 31 32 /******************************************************************************* 33 * Definitions 34 ******************************************************************************/ 35 36 /******************************************************************************* 37 * Prototypes 38 ******************************************************************************/ 39 40 /******************************************************************************* 41 * Variables 42 ******************************************************************************/ 43 44 /******************************************************************************* 45 * Code 46 ******************************************************************************/ 47 /* ========================= DATA RATE ONLY settings ===============*/ 48 /*! 49 * @brief XCVR 1Mbps DATA RATE specific configure structure 50 */ 51 const xcvr_datarate_config_t xcvr_1mbps_config = 52 { 53 .data_rate = DR_1MBPS, 54 .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0xF) | 55 #if !RADIO_IS_GEN_2P1 56 XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | 57 #endif /* !RADIO_IS_GEN_2P1 */ 58 XCVR_PHY_EL_CFG_EL_INTERVAL(0x20) , 59 .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(0) | 60 XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), 61 .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | 62 XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), 63 64 .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(10) | 65 XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), 66 .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(12) | 67 XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), 68 69 .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(10) | 70 XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(21), 71 .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(12) | 72 XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(26), 73 74 .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | 75 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | 76 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(3) | 77 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | 78 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | 79 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | 80 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(3), 81 82 .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | 83 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | 84 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(3) | 85 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | 86 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | 87 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | 88 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(3), 89 90 .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | 91 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | 92 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), 93 .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | 94 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(3) | 95 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), 96 97 .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(33) | 98 XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(6), 99 .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(40) | 100 XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(7), 101 }; 102 103 /*! 104 * @brief XCVR 500K bps DATA RATE specific configure structure 105 */ 106 const xcvr_datarate_config_t xcvr_500kbps_config = 107 { 108 .data_rate = DR_500KBPS, 109 .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x8) | 110 #if !RADIO_IS_GEN_2P1 111 XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | 112 #endif /* !RADIO_IS_GEN_2P1 */ 113 XCVR_PHY_EL_CFG_EL_INTERVAL(0x10), 114 .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | 115 XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), 116 .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) | 117 XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), 118 119 .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(15) | 120 XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), 121 .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(18) | 122 XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), 123 124 .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(13) | 125 XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(29), 126 .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(16) | 127 XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(36), 128 129 .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | 130 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | 131 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | 132 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | 133 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | 134 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | 135 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), 136 137 .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | 138 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | 139 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | 140 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | 141 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | 142 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | 143 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), 144 145 .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | 146 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | 147 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), 148 .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | 149 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | 150 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), 151 152 .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(26) | 153 XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), 154 .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(32) | 155 XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), 156 }; 157 158 /*! 159 * @brief XCVR 250K bps DATA RATE specific configure structure 160 */ 161 const xcvr_datarate_config_t xcvr_250kbps_config = 162 { 163 .data_rate = DR_250KBPS, 164 .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x4) | 165 #if !RADIO_IS_GEN_2P1 166 XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | 167 #endif /* !RADIO_IS_GEN_2P1 */ 168 XCVR_PHY_EL_CFG_EL_INTERVAL(0x8) , 169 .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) | 170 XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), 171 .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(4) | 172 XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), 173 174 .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(18) | 175 XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), 176 .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(22) | 177 XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), 178 179 .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(16) | 180 XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(34), 181 .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(20) | 182 XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(42), 183 184 .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | 185 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | 186 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(1) | 187 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | 188 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | 189 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | 190 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), 191 192 .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | 193 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | 194 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(1) | 195 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | 196 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | 197 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | 198 XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), 199 200 .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(0) | 201 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(1) | 202 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1), 203 .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(0) | 204 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(1) | 205 XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1), 206 207 .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(13) | 208 XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), 209 .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(16) | 210 XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), 211 }; 212 213
