1 /******************************************************************************
2 * @file arm_math_memory.h
3 * @brief Public header file for CMSIS DSP Library
4 * @version V1.9.0
5 * @date 23 April 2021
6 * Target Processor: Cortex-M and Cortex-A cores
7 ******************************************************************************/
8 /*
9 * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
10 *
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the License); you may
14 * not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 */
25
26 #ifndef _ARM_MATH_MEMORY_H_
27
28 #define _ARM_MATH_MEMORY_H_
29
30 #include "arm_math_types.h"
31
32
33 #ifdef __cplusplus
34 extern "C"
35 {
36 #endif
37
38 /**
39 @brief definition to read/write two 16 bit values.
40 @deprecated
41 */
42 #if defined ( __CC_ARM )
43 #define __SIMD32_TYPE int32_t __packed
44 #elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
45 #define __SIMD32_TYPE int32_t
46 #elif defined ( __GNUC__ )
47 #define __SIMD32_TYPE int32_t
48 #elif defined ( __ICCARM__ )
49 #define __SIMD32_TYPE int32_t __packed
50 #elif defined ( __TI_ARM__ )
51 #define __SIMD32_TYPE int32_t
52 #elif defined ( __CSMC__ )
53 #define __SIMD32_TYPE int32_t
54 #elif defined ( __TASKING__ )
55 #define __SIMD32_TYPE __un(aligned) int32_t
56 #elif defined(_MSC_VER )
57 #define __SIMD32_TYPE int32_t
58 #else
59 #error Unknown compiler
60 #endif
61
62 #define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
63 #define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr))
64 #define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr))
65 #define __SIMD64(addr) (*( int64_t **) & (addr))
66
67
68 /* SIMD replacement */
69
70
71 /**
72 @brief Read 2 Q15 from Q15 pointer.
73 @param[in] pQ15 points to input value
74 @return Q31 value
75 */
read_q15x2(q15_t * pQ15)76 __STATIC_FORCEINLINE q31_t read_q15x2 (
77 q15_t * pQ15)
78 {
79 q31_t val;
80
81 #ifdef __ARM_FEATURE_UNALIGNED
82 memcpy (&val, pQ15, 4);
83 #else
84 val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ;
85 #endif
86
87 return (val);
88 }
89
90 /**
91 @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards.
92 @param[in] pQ15 points to input value
93 @return Q31 value
94 */
read_q15x2_ia(q15_t ** pQ15)95 __STATIC_FORCEINLINE q31_t read_q15x2_ia (
96 q15_t ** pQ15)
97 {
98 q31_t val;
99
100 #ifdef __ARM_FEATURE_UNALIGNED
101 memcpy (&val, *pQ15, 4);
102 #else
103 val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF);
104 #endif
105
106 *pQ15 += 2;
107 return (val);
108 }
109
110 /**
111 @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards.
112 @param[in] pQ15 points to input value
113 @return Q31 value
114 */
read_q15x2_da(q15_t ** pQ15)115 __STATIC_FORCEINLINE q31_t read_q15x2_da (
116 q15_t ** pQ15)
117 {
118 q31_t val;
119
120 #ifdef __ARM_FEATURE_UNALIGNED
121 memcpy (&val, *pQ15, 4);
122 #else
123 val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF);
124 #endif
125
126 *pQ15 -= 2;
127 return (val);
128 }
129
130 /**
131 @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards.
132 @param[in] pQ15 points to input value
133 @param[in] value Q31 value
134 @return none
135 */
write_q15x2_ia(q15_t ** pQ15,q31_t value)136 __STATIC_FORCEINLINE void write_q15x2_ia (
137 q15_t ** pQ15,
138 q31_t value)
139 {
140 q31_t val = value;
141 #ifdef __ARM_FEATURE_UNALIGNED
142 memcpy (*pQ15, &val, 4);
143 #else
144 (*pQ15)[0] = (val & 0x0FFFF);
145 (*pQ15)[1] = (val >> 16) & 0x0FFFF;
146 #endif
147
148 *pQ15 += 2;
149 }
150
151 /**
152 @brief Write 2 Q15 to Q15 pointer.
153 @param[in] pQ15 points to input value
154 @param[in] value Q31 value
155 @return none
156 */
write_q15x2(q15_t * pQ15,q31_t value)157 __STATIC_FORCEINLINE void write_q15x2 (
158 q15_t * pQ15,
159 q31_t value)
160 {
161 q31_t val = value;
162
163 #ifdef __ARM_FEATURE_UNALIGNED
164 memcpy (pQ15, &val, 4);
165 #else
166 pQ15[0] = val & 0x0FFFF;
167 pQ15[1] = val >> 16;
168 #endif
169 }
170
171
172 /**
173 @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards.
174 @param[in] pQ7 points to input value
175 @return Q31 value
176 */
read_q7x4_ia(q7_t ** pQ7)177 __STATIC_FORCEINLINE q31_t read_q7x4_ia (
178 q7_t ** pQ7)
179 {
180 q31_t val;
181
182
183 #ifdef __ARM_FEATURE_UNALIGNED
184 memcpy (&val, *pQ7, 4);
185 #else
186 val =(((*pQ7)[3] & 0x0FF) << 24) | (((*pQ7)[2] & 0x0FF) << 16) | (((*pQ7)[1] & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF);
187 #endif
188
189 *pQ7 += 4;
190
191 return (val);
192 }
193
194 /**
195 @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards.
196 @param[in] pQ7 points to input value
197 @return Q31 value
198 */
read_q7x4_da(q7_t ** pQ7)199 __STATIC_FORCEINLINE q31_t read_q7x4_da (
200 q7_t ** pQ7)
201 {
202 q31_t val;
203 #ifdef __ARM_FEATURE_UNALIGNED
204 memcpy (&val, *pQ7, 4);
205 #else
206 val = ((((*pQ7)[3]) & 0x0FF) << 24) | ((((*pQ7)[2]) & 0x0FF) << 16) | ((((*pQ7)[1]) & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF);
207 #endif
208 *pQ7 -= 4;
209
210 return (val);
211 }
212
213 /**
214 @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards.
215 @param[in] pQ7 points to input value
216 @param[in] value Q31 value
217 @return none
218 */
write_q7x4_ia(q7_t ** pQ7,q31_t value)219 __STATIC_FORCEINLINE void write_q7x4_ia (
220 q7_t ** pQ7,
221 q31_t value)
222 {
223 q31_t val = value;
224 #ifdef __ARM_FEATURE_UNALIGNED
225 memcpy (*pQ7, &val, 4);
226 #else
227 (*pQ7)[0] = val & 0x0FF;
228 (*pQ7)[1] = (val >> 8) & 0x0FF;
229 (*pQ7)[2] = (val >> 16) & 0x0FF;
230 (*pQ7)[3] = (val >> 24) & 0x0FF;
231
232 #endif
233 *pQ7 += 4;
234 }
235
236
237 #ifdef __cplusplus
238 }
239 #endif
240
241 #endif /*ifndef _ARM_MATH_MEMORY_H_ */
242
