1 /****************************************************************************** 2 * Copyright (c) 2021-2023 Texas Instruments Incorporated. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * 1) Redistributions of source code must retain the above copyright notice, 8 * this list of conditions and the following disclaimer. 9 * 10 * 2) Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * 3) Neither the name of the copyright holder nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 ****************************************************************************** 30 * \file hw_fcfg.h 31 * 32 * \brief Factory Configuration (FCFG) header file. 33 ******************************************************************************/ 34 #ifndef __HW_FCFG_H__ 35 #define __HW_FCFG_H__ 36 37 #include <stdint.h> 38 #include "hw_device.h" 39 #include "hw_ccfg.h" 40 41 // *** Define datatypes used in FCFG *** 42 43 // \note Struct written to avoid automatic padding. Packing directives not needed 44 // \note Bitfields: lsb->msb, packing of similar base types, no word boundary crossing 45 typedef struct { 46 // Critical Trim (done early in boot sequence or requires special handling) 47 struct { // [0]: length 64 B 48 // SRAM repair information (* hardcoded into ASM to be at offset 0, do not move! *) 49 struct { // length 28B 50 // Value SRAMREP_MAGICWORD tells SRAM repair in ASM that criticalTrim is valid 51 uint32_t magicWord; 52 // Number of bits to shift through SRAM repair chain (first 4b are read back) 53 uint8_t numBits; 54 // Data to shift through SRAM repair chain (MSB first, max 184b) 55 uint8_t data[23]; 56 } sramRepair; 57 // HFOSC trim (CKMD.TRIM0) 58 struct { // length: 4B 59 union { 60 uint16_t val16; 61 struct { 62 uint16_t coarse : 5; 63 uint16_t cap : 4; 64 uint16_t bias : 5; 65 uint16_t res0 : 2; 66 }; 67 } initial; 68 union { 69 uint16_t val16; 70 struct { 71 uint16_t coarse : 5; 72 uint16_t cap : 4; 73 uint16_t bias : 5; 74 uint16_t res0 : 2; 75 }; 76 } final; 77 } hfoscTrim; 78 // Flash trims 79 struct { // length 16 B 80 // Flash 1T wait states (default: 2 WS trimmed) 81 struct { // length: 2B 82 uint8_t initial; 83 uint8_t final; 84 } flws1t; 85 // Flash 2T wait states (default: 5 WS untrimmed, 2 WS trimmed) 86 struct { // length: 2B 87 uint8_t initial; 88 uint8_t final; 89 } flws2t; 90 uint32_t ptrmc0; 91 uint32_t b0trmc1; 92 uint32_t b0trmc0; 93 } flashTrim; 94 // PMU trim: GLDO/BIAS/BGAP/DigLDO 95 struct { // length 8B 96 union { 97 uint32_t val32; 98 struct { 99 uint32_t vref : 4; 100 uint32_t vbg : 6; 101 uint32_t vddsbod : 5; 102 uint32_t bgtrimen : 1; // Latch vddsbod (0 initially, set to 1 in later trim steps) 103 uint32_t iref : 5; 104 uint32_t tsense : 2; 105 uint32_t spare : 1; 106 uint32_t vddrokhyst : 1; 107 uint32_t dissahyst : 1; 108 uint32_t gldocompdis: 1; 109 uint32_t gldodisana : 1; 110 uint32_t res0 : 4; 111 }; 112 } timmute0; 113 union { 114 uint32_t val32; 115 struct { 116 uint32_t vddr : 5; 117 uint32_t vddrsl : 5; 118 uint32_t iptat : 2; 119 uint32_t bod : 4; 120 uint32_t udig : 4; 121 uint32_t dig : 4; 122 uint32_t coarse : 4; 123 uint32_t delta : 3; 124 uint32_t res0 : 1; 125 }; 126 } timmute1; 127 } pmuTrim; 128 // Systick reload value that determines minimum time for each trim step in clock cycles 129 uint8_t sysTickRvrTrimStep; 130 // Flag to control whether BOD reset is disabled during VDDR/BGAP trim stepping 131 uint8_t disableBodDuringTrim : 1; 132 // Settling delay after VDDR/BGAP = enableBodDelaySteps*sysTickRvrTrimStep+1 clock cycles 133 uint8_t enableBodDelaySteps : 5; 134 uint8_t res0 : 2; 135 // Flash verify waitstates 136 uint8_t flashVerifyWaitStates : 4; 137 uint8_t res2 : 4; 138 // Padding to get record size to multiple of 16 B 139 uint8_t res1[1]; 140 // CRC32 integrity check critical trim 141 uint32_t crc32; 142 } criticalTrim; 143 144 // Paperspin options [64]: length 8 B 145 // Defines peripheral/feature availability and accessible memory 146 uint32_t hwOpts[2]; 147 148 149 // Device permissions [72]: length 4 B 150 // This is maximally-restrictive combined with similar field in CCFG 151 struct { 152 #define FCFG_PERMISSION_ALLOW 0xA 153 #define FCFG_PERMISSION_FORBID 0x0 154 // (all other value other than ALLOW are interpreted as FORBID) 155 uint32_t allowReturnToFactory : 4; 156 uint32_t allowFakeStby : 4; 157 uint32_t allowToolsClientMode : 4; 158 uint32_t allowChipErase : 4; 159 uint32_t allowFlashProgram : 4; 160 uint32_t allowFlashVerify : 4; 161 uint32_t allowEnergyTrace : 4; 162 uint32_t allowDebugPort : 4; 163 } permissions; 164 165 166 // Miscellaneous fields 167 // [76]: length 4B 168 struct { 169 // SACI timeout is infinite when 0, else (2^saciTimeoutExp)*64 ms 170 // Ccfg timeout applied instead if CCfg.saciTimeoutOverride==1 171 uint32_t saciTimeoutExp : 3; 172 #define XCFG_MISC_SACITOEXP_8SEC 7 173 #define XCFG_MISC_SACITOEXP_1SEC 4 174 #define XCFG_MISC_SACITOEXP_INFINITE 0 175 uint32_t res0 : 29; 176 } misc; 177 178 179 // Device information 180 struct { // [80]: length 48B 181 // 64b device-unique UUID (non-sequential across parts) 182 uint8_t uuid[8]; 183 // 48b device-unique BLE address 184 uint8_t bleAddr[6]; 185 // Padding 186 uint8_t res0[2]; 187 // 64b device-unique IEEE MAC address 188 uint8_t macAddr[8]; 189 // 128b die identifier (lot #, wafer #, die X/Y, date, etc) 190 uint8_t dieId[16]; 191 // Padding (previously devId but this HW-defined value is now readable through an MMR) 192 uint32_t res1; 193 // 32b PARTID (Part/Variant/majRev/minorRev) 194 union { 195 uint32_t val32; 196 struct { 197 // Random bit pattern to uniquely identify part (with devId) 198 uint32_t part : 16; 199 // Random bit pattern to uniquely identify package/memory variant 200 uint32_t variant : 8; 201 // Minor revision for orderable part (starts at 0) 202 uint32_t minorRev : 4; 203 // Major revision for orderable part: PCB/SW change (starts at 1) 204 uint32_t majorRev : 3; 205 // 0: partId not yet valid; 1: partId valid 206 uint32_t partIdValid : 1; 207 }; 208 } partId; 209 } deviceInfo; 210 211 212 // Flash protection [128]: length 16 B 213 // This is maximally-restrictive combined with similar field in CCFG 214 struct { 215 struct { 216 // Sticky-0 bits written to VIMS.WEPRA (sectors 0-31, 1/bit) 217 uint32_t mainSectors0_31; 218 // Sticky-0 bits written to VIMS.WEPRB(0) (sectors 32-255, 8/bit) 219 uint32_t mainSectors32_255; 220 // Sticky-0 bit written to VIMS.WEPRAUX 221 union { 222 uint32_t auxSectors; 223 struct { 224 uint32_t ccfgSector : 1; 225 uint32_t fcfgSector : 1; 226 uint32_t engrSector : 1; 227 uint32_t res1 : 29; 228 }; 229 }; 230 } writeEraseProt; 231 uint32_t res; 232 } flashProt; 233 234 // ******************************************************* 235 // *** General Trims (copy list format) *** 236 // ******************************************************* 237 // [144]: (152 words in 128b flash, 40 words in 64b flash) 238 uint32_t generalTrims[FCFG_GENERALTRIMS_SIZE]; 239 // Simple macros to assist in initializing copy lists 240 // NOTE: Addresses to CPYLIST_CPY must fulfill (a & 0x0FF00003) == 3. 241 // The memory map ensures this for SRAM and peripherals. 242 // There is no check as ELF only supports {symbol + const offset} 243 #define CPYLST_EOL 0 244 #define CPYLST_NOP 0x10000000 245 #define CPYLST_WAIT(x) ( 0x10000000 + (((x)<<2)&0x000FFFFC) ) 246 #define CPYLST_CPY(a, n) ( ((uint32_t)(a)) + (((n)<<20)&0x0FF00000) ) 247 #define CPYLST_CPYFULLADDR(a) (((uint32_t)(a)) + 1) 248 #define CPYLST_JUMP(a) (((uint32_t)(a)) + 2) 249 #define CPYLST_CALL(a) (((uint32_t)(a)) + 3) 250 251 252 // ******************************************************* 253 // *** Extended Application Trims *** 254 // ******************************************************* 255 // Extended application trims. 256 // [End-272]: length 64B 257 struct appTrimsExt_struct { 258 struct appTrimsExtCc23x0r5_s { // length: 64B 259 // Unused space 260 uint8_t res[40]; 261 struct { // length: 4B 262 // Measured value on 1.8V for ODP core NMOS IDSAT 263 uint16_t odpNmos; 264 // Measured value on 1.8V for ODP core PMOS IDSAT 265 uint16_t odpPmos; 266 } odpVal1p8v; 267 struct { // length: 4B 268 // Measured value on 1.2V for ODP core NMOS IDSAT 269 uint16_t odpNmos; 270 // Measured value on 1.2V for ODP core PMOS IDSAT 271 uint16_t odpPmos; 272 } odpVal1p2v; 273 // Value for the FWT MP production program revision 274 struct { // length: 4B 275 uint32_t revBranch : 4; 276 uint32_t revPatch : 8; 277 uint32_t revMinor : 8; 278 uint32_t revMajor : 6; 279 uint32_t variantCode : 6; 280 } tfwMp; 281 // Value for the FWT FT production program revision 282 struct { // length: 4B 283 uint32_t revBranch : 4; 284 uint32_t revPatch : 8; 285 uint32_t revMinor : 8; 286 uint32_t revMajor : 6; 287 uint32_t variantCode : 6; 288 } tfwFt; 289 // Value for the MP production test program revision 290 struct { // length 4B 291 uint32_t mp1Rev : 8; 292 uint32_t mp2Rev : 8; 293 uint32_t mp3Rev : 8; 294 uint32_t res : 8; 295 } ateMpRev; 296 // Value for the FT production test program revision 297 struct { // length 4B 298 uint32_t ft1Rev : 8; 299 uint32_t ft2Rev : 8; 300 uint32_t ft3Rev : 8; 301 uint32_t trimState : 8; 302 } ateFtRev; 303 } cc23x0r5; 304 } appTrimsExt; 305 306 307 // ******************************************************* 308 // *** Application Trims *** 309 // ******************************************************* 310 // Application trims (individual fields are not referenced 311 // by ROM). Note that the Application Trims section is 312 // copied to SRAM by the SACI command SC_MODE_REQ_TOOLS_CLIENT. 313 // [End-208]: length 128B for non BLE High devices 314 // [End-256]: length 128B for BLE High devices 315 struct appTrims_struct { 316 // Revision of appTrims (defines layout) 317 uint8_t revision; 318 // Offset range to copy to SRAM in tools client mode to appTrims-n*16B. 319 uint8_t nToolsClientOffset; 320 // Pad to 32b alignment 321 uint8_t res[2]; 322 323 // Different device-specific application trim records 324 struct appTrimsCc23x0r5_s { // length: 124B 325 // Trim value for LRFDRFE:PA0.TRIM 326 struct { // length: 2B 327 uint16_t trim : 5; 328 uint16_t zero : 11; 329 } pa0; 330 // Trim value for LRFDRFE:ATSTREFH.IREFTRIM 331 struct { // length: 2B 332 uint16_t zero0 : 10; 333 uint16_t irefTrim : 5; 334 uint16_t zero1 : 1; 335 } atstRefH; 336 // Trim value for LRFDRFE:LNA.TRIM 337 struct { // length: 2B 338 uint16_t zero0 : 4; 339 uint16_t trim : 4; 340 uint16_t zero1 : 8; 341 } lna; 342 // Trim value for LRFDRFE:IFAMPRFLDO.TRIM 343 struct { // length: 2B 344 uint16_t zero : 9; 345 uint16_t trim : 7; 346 } ifampRfLdo; 347 // Trim value for LRFDRFE:DIVLDO.VOUTTRIM 348 struct { // length: 2B 349 uint16_t zero0 : 8; 350 uint16_t voutTrim : 7; 351 uint16_t zero1 : 1; 352 } divLdo; 353 // Trim value for LRFDRFE:TDCLDO.VOUTTRIM 354 struct { // length: 2B 355 uint16_t zero0 : 8; 356 uint16_t voutTrim : 7; 357 uint16_t zero1 : 1; 358 } tdcLdo; 359 // Trim values for LRFDRFE:DCOLDO0 360 struct { // length: 2B 361 uint16_t zero0 : 4; 362 uint16_t firstTrim : 4; 363 uint16_t secondTrim : 6; 364 uint16_t zero1 : 2; 365 } dcoLdo0; 366 // Trim value for LRFDRFE:IFADCALDO.TRIMOUT 367 struct { // length: 2B 368 uint16_t zero0 : 8; 369 uint16_t trimout : 6; 370 uint16_t zero1 : 2; 371 } ifadcAldo; 372 // Trim value for LRFDRFE:IFADCDLDO.TRIMOUT 373 struct { // length: 2B 374 uint16_t zero0 : 8; 375 uint16_t trimout : 6; 376 uint16_t zero1 : 2; 377 } ifadcDldo; 378 // Trim value for LRFDRFE:DCO.TAILRESTRIM 379 struct { // length: 2B 380 uint16_t zero0 : 3; 381 uint16_t tailresTrim : 4; 382 uint16_t zero1 : 9; 383 } dco; 384 // Trim value for LRFDRFE:IFADCQUANT.QUANTTHR 385 struct { // length: 2B 386 uint16_t quantThr : 3; 387 uint16_t zero : 13; 388 } ifadcQuant; 389 // Trim values for LRFDRFE:IFADC0 390 struct { // length: 2B 391 uint16_t zero0 : 2; 392 uint16_t aafcap : 2; 393 uint16_t int2Adj : 4; 394 uint16_t zero1 : 2; 395 uint16_t ditheren : 2; 396 uint16_t dithertrim : 3; 397 uint16_t zero2 : 1; 398 } ifadc0; 399 // Trim value for LRFDRFE:IFADC1.TRIM 400 struct { // length: 2B 401 uint16_t zero0 : 9; 402 uint16_t trim : 6; 403 uint16_t nrz : 1; 404 } ifadc1; 405 // Trim values for LRFDRFE:IFADCLF 406 struct { // length: 2B 407 uint16_t int3 : 4; 408 uint16_t ff1 : 4; 409 uint16_t ff2 : 4; 410 uint16_t ff3 : 4; 411 } ifadclf; 412 // Trim value for LRFDRFE:IFADCQUANT.QUANTTHR high-bandwidth 413 struct { // length: 2B 414 uint16_t quantThr : 3; 415 uint16_t zero : 13; 416 } ifadcQuantWbw; 417 // Trim values for LRFDRFE:IFADC0 high-bandwidth 418 struct { // length: 2B 419 uint16_t zero0 : 2; 420 uint16_t aafcap : 2; 421 uint16_t int2Adj : 4; 422 uint16_t zero1 : 2; 423 uint16_t ditheren : 2; 424 uint16_t dithertrim : 3; 425 uint16_t zero2 : 1; 426 } ifadc0Wbw; 427 // Trim value for LRFDRFE:IFADC1.TRIM high-bandwidth 428 struct { // length: 2B 429 uint16_t zero0 : 9; 430 uint16_t trim : 6; 431 uint16_t nrz : 1; 432 } ifadc1Wbw; 433 // Trim values for LRFDRFE:IFADCLF high-bandwidth 434 struct { // length: 2B 435 uint16_t int3 : 4; 436 uint16_t ff1 : 4; 437 uint16_t ff2 : 4; 438 uint16_t ff3 : 4; 439 } ifadclfWbw; 440 // Trim values for RTRIM, synth LDO and HFXT Peak Detector 441 struct { 442 // RTRIM Min Offset. 443 // Value represents the positive offset in RTRIM at -40 vs 25C. The calculated trim 444 // adjustment will be added to nominal trim when temperature crosses -40 +TTHRL x 2^k. 445 uint32_t rtrimMinOffset : 2; 446 // RTRIM Max Offset. 447 // Value represents the positive offset in RTRIM at 125C vs 25C. The calculated trim adjustment 448 // will be added to nominal trim when temperature crosses 125 - TTHRH x 2^k. 449 uint32_t rtrimMaxOffset : 2; 450 // DIVLDO Min Offset. 451 // Value represents 0, 10 (50mV), 20 (100mV), or 30 (150mV) positive trim LSB offset at -40 as 452 // compared to 25C. The calculated trim adjustment will be added to nominal trim when temperature 453 // crosses -40 + TTHRL x 2^k. 454 uint32_t divLdoMinOffset : 2; 455 // DIVLDO Max Offset. 456 // Value represents 0, 10 (50mV), 20 (100mV), or 30 (150mV) positive trim LSB offset at 125C as 457 // compared to 25C. The calculated trim adjustment will be added to nominal trim when temperature 458 // crosses 125 - TTHRH x 2^k. 459 uint32_t divLdoMaxOffset : 2; 460 // TDCLDO Min Offset. 461 // Value represents 0, 10 (50mV), 20 (100mV), or 30 (150mV) positive trim LSB offset at -40 as 462 // compared to 25C. The calculated trim adjustment will be added to nominal trim when temperature 463 // crosses -40 + TTHRL x 2^k. 464 uint32_t tdcLdoMinOffset : 2; 465 // TDCLDO Max Offset. 466 // Value represents 0, 10 (50mV), 20 (100mV), or 30 (150mV) positive trim LSB offset at 125C as 467 // compared to 25C. The calculated trim adjustment will be added to nominal trim when temperature 468 // crosses 125 - TTHRH x 2^k. 469 uint32_t tdcLdoMaxOffset : 2; 470 // Temperature Threshold Low. 471 // Value sets the temperature threshold for correction as -40C + x * 2^k, where k is TBD. 472 // At temperatures below the threshold, a nominal trim value will be adjusted. 473 uint32_t tThrl : 2; 474 // Temperature Threshold High. 475 // Value sets the temperature threshold for correction as -40C + x * 2^k, where k is TBD. 476 // At temperatures above the threshold, a nominal trim value will be adjusted. 477 uint32_t tThrh : 2; 478 // Peak detector variation measured in production 479 uint32_t hfxtPdError : 8; 480 // Reserved 481 uint32_t res : 8; 482 } lrfdrfeExtTrim1; 483 // Trim values for adjusting AGC and RSSI 484 struct { 485 // RSSI offset temperature compensation. 486 // The COMP is added to RSSIOFFSET before programming RSSI offset to HW register. 487 // Use for all PHYs. 488 // Max compensation at 125C is -6 to +5.5 dB. Max compensation at -40C is -3.5 to 4 dB. 489 // Add to LRFDRFE:RSSIOFFSET. 490 // Formula: COMP = (temp-25)*signed(RSSITCOMP)/128 491 uint32_t rssiTcomp : 4; 492 // AGC magn target temperature compensation. 493 // The COMP is added to MAGN target before programming HW register (SPARE<x>). 494 // Use for PHYs using the generic AGC. 495 // Max compensation at 125C is -6 to +5.5 dB. Max compensation at -40C is -3.5 to 4 dB. 496 // Add to LRFDRFE:SPARE<x>. 497 // Formula: COMP = (temp-25)*signed(magnTcomp)/128 498 uint32_t magnTcomp : 4; 499 // Fab dependent offset to add to AGC magnitude target (SPARE<x>). 500 // Use for PHYs using the generic AGC. Add to LRFDRFE:SPARE<x>. 501 // Formula: COMP = signed(magnOffset) 502 uint32_t magnOffset : 4; 503 // Reserved 504 uint32_t rfu : 4; 505 // AGC threshold temperature compensation. 506 // The COMP is added to AGC threshold before programming HW register (SPARE<x>). 507 // Use for PHYs with fast AGC (high gain / low gain type). 508 // Formula: COMP = (temp-25)*signed(agcThrTcomp)/128 509 uint32_t agcThrTcomp : 4; 510 // Fab dependent offset to add to AGC threshold target. 511 // Use for PHYs with fast AGC (high gain / low gain type). 512 // Add to LRFDRFE:SPARE<x>. 513 // Formula: COMP = signed(agcThrOffset) 514 uint32_t agcThrOffset : 4; 515 // Adjust the low gain setting with this signed number. 516 // Use for PHYs with fast AGC (high gain / low gain type). 517 // Add to LRFDRFE:SPARE0[3:0], check for overflow/underflow. 518 // Formula: COMP = signed(lowGainOffset) 519 uint32_t lowGainOffset : 4; 520 // Adjust the high gain setting with this signed number. 521 // Use for PHYs with fast AGC (high gain / low gain type). 522 // Add to LRFDRFE:SPARE0[7:4], check for overflow/underflow. 523 // Formula: COMP = signed(lowGainOffset) 524 uint32_t highGainOffset : 4; 525 } lrfdrfeExtTrim0; 526 // Trim values for front end 0 527 struct { // length: 2B 528 // RSSI measured for front end 0 in production test. 529 // Value is read by RF Core FW during RF Core initialization 530 uint16_t offset : 8; 531 uint16_t trimCompleteN : 1; 532 uint16_t zero : 7; 533 } fend0Rssi; 534 // Trim values for synth divider 0 535 struct { // length: 2B 536 // Trim value for IQ mismatch compensation. 537 // Value is read by RF Core FW during RF Core initialization 538 uint16_t iqmc : 16; 539 } syntDiv0; 540 // Unused space 541 uint8_t res1[2]; 542 // Trim values for LRFDRFE:IFAMP.AAFCAP 543 struct { // length: 1B 544 uint8_t zero : 4; 545 uint8_t aafcap : 4; 546 } ifamprfldo; 547 // Trim values for LRFDRFE:IFAMP.AAFCAP high-bandwidth 548 struct { // length: 1B 549 uint8_t zero : 4; 550 uint8_t aafcap : 4; 551 } ifamprfldoWbw; 552 // Trim value for AUX Diode voltage at 30C 553 struct { // length: 4B 554 uint16_t auxDiodeGnd; 555 uint16_t auxDiodeVoltage; 556 } auxDiodeCal30C; 557 // Trim value for AUX Diode voltage at 125C 558 struct { // length: 4B 559 uint16_t auxDiodeGnd; 560 uint16_t auxDiodeVoltage; 561 } auxDiodeCal125C; 562 // Values for LFOSC performance 563 struct { // length: 4B 564 uint32_t ppmRtn : 8; 565 uint32_t ppmTempMid : 8; 566 uint32_t ppmTempExt : 8; 567 uint32_t res : 8; 568 } lfOscParams; 569 // Unused space 570 uint8_t res2[16]; 571 // ADC offset for four modes 572 struct { // length: 4B 573 uint32_t adcOffsetVdds : 8; 574 uint32_t adcOffsetExtref : 8; 575 uint32_t adcOffsetIntref2P5V : 8; 576 uint32_t adcOffsetIntref1P4V : 8; 577 } adcOffset; 578 // ADC gain for VDDS and Extref modes 579 struct { // length: 4B 580 uint32_t adcGainVdds : 16; 581 uint32_t adcGainExtref : 16; 582 } adcGainWord0; 583 // ADC gain for Intref 2.5V and Intref 1.4V modes 584 struct { // length: 4B 585 uint32_t adcGainIntref2P5V : 16; 586 uint32_t adcGainIntref1P4V : 16; 587 } adcGainWord1; 588 // Coefficients for AUX Diode temperature to voltage 589 struct { // length: 8B 590 int16_t coeffP2; 591 int16_t coeffP1; 592 int16_t coeffP0; 593 uint16_t coeffP2Shift :5; 594 uint16_t coeffP1Shift :5; 595 uint16_t coeffP0Shift :5; 596 uint16_t res0 :1; 597 } auxDiodeCoeff; 598 // Unused space 599 uint8_t res3[20]; 600 // Measured I2V resistor error values 601 struct { // length: 4B 602 uint32_t i2v20k : 8; 603 uint32_t i2v50k : 8; 604 uint32_t i2v100k : 8; 605 uint32_t i2v1m : 8; 606 } i2vCompact; 607 } cc23x0r5; 608 } appTrims; 609 610 // Bootloader configuration 611 struct { // [End-80]: length 8B 612 // Pointer to default bootloader VTOR table 613 void *pBldrVtor; 614 #define XCFG_BC_PBLDR_FORBID ((void*)0xFFFFFFFC) 615 #define XCFG_BC_PBLDR_UNDEF ((void*)0xFFFFFFFF) 616 #define FCFG_BC_PBLDR_VALID(x) ((x) < XCFG_BC_PBLDR_FORBID) 617 // Parameter passed to bootloader 618 union { 619 uint32_t val32; 620 // Serial ROM bootloader parameters (defined in CCFG.h) 621 serialRomBldrParam_t params; 622 } bldrParam; 623 } bootCfg; 624 625 626 // Reserved/padding to get 16 B alignment 627 // [End-72] length: 4B 628 uint32_t res1; 629 630 631 // CRC across hwOpts through res1 (after criticalTrim to here) 632 // [End-68]: length 4B 633 uint32_t crc32; 634 635 // Lifecycle management 636 struct { // [End-64]: length 16B 637 // 128b field updated incrementally (32b at a time) as lifecycle increments 638 uint32_t states[4]; 639 // SET => 32b word has a value within a Hamming distance <=1 of (FCFG_SET32) 640 // UNSET => all others (2T erased state is random) 641 #define FCFG_SET32 0x41008002 642 #define FCFG_UNSET32 0x41FFFFFF 643 // Lifecycle BDAY1ST: FA unlock key integrity check fails 644 // Other lifecycles: FA unlock key integrity check OK + states words as below 645 #define FCFG_LC_TESTPT {FCFG_UNSET32, FCFG_UNSET32, FCFG_UNSET32, FCFG_UNSET32} 646 #define FCFG_LC_TESTFT {FCFG_SET32, FCFG_UNSET32, FCFG_UNSET32, FCFG_UNSET32} 647 #define FCFG_LC_ENGRDEV {FCFG_SET32, FCFG_SET32, FCFG_UNSET32, FCFG_UNSET32} 648 #define FCFG_LC_PRODDEV {FCFG_SET32, FCFG_SET32, FCFG_SET32, FCFG_UNSET32} 649 #define FCFG_LC_RETEST {FCFG_SET32, FCFG_SET32, FCFG_SET32, FCFG_SET32} 650 } lifecycle; 651 } fcfg_t; 652 653 /* \brief Define to access FCFG struct pointer from application code. 654 * This definition can be used to access member elements with the `->` 655 * operator. 656 */ 657 #define fcfg ((const fcfg_t *)FCFG_BASE) 658 659 /* Define type used by hw_device.h */ 660 typedef struct appTrims_struct fcfg_appTrims_t; 661 662 #endif // __HW_FCFG_H__ 663
