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/loramac-node-3.4.0/src/boards/mcu/saml21/cmsis/
Dcore_cmInstr.h129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) in __REV16()
144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) in __REVSH()
171 #define __BKPT(value) __breakpoint(value) argument
225 #define __STREXB(value, ptr) __strex(value, ptr) argument
237 #define __STREXH(value, ptr) __strex(value, ptr) argument
249 #define __STREXW(value, ptr) __strex(value, ptr) argument
300 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) in __RRX()
345 #define __STRBT(value, ptr) __strt(value, ptr) argument
355 #define __STRHT(value, ptr) __strt(value, ptr) argument
365 #define __STRT(value, ptr) __strt(value, ptr) argument
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/loramac-node-3.4.0/src/boards/mcu/saml21/saml21b/include/component/
Dtal.h266 #define TAL_BRKSTATUS_CM0P(value) (TAL_BRKSTATUS_CM0P_Msk & ((value) << TAL_BRKSTATUS_CM0P_Pos)) argument
269 #define TAL_BRKSTATUS_PPP(value) (TAL_BRKSTATUS_PPP_Msk & ((value) << TAL_BRKSTATUS_PPP_Pos)) argument
272 #define TAL_BRKSTATUS_EVBRK(value) (TAL_BRKSTATUS_EVBRK_Msk & ((value) << TAL_BRKSTATUS_EVBRK_Pos)) argument
275 #define TAL_BRKSTATUS_EXTBRK(value) (TAL_BRKSTATUS_EXTBRK_Msk & ((value) << TAL_BRKSTATUS_EXTBRK_Po… argument
295 #define TAL_CTICTRLA_ACTION(value) (TAL_CTICTRLA_ACTION_Msk & ((value) << TAL_CTICTRLA_ACTION_Pos)) argument
374 #define TAL_INTSTATUS_IRQ(value) (TAL_INTSTATUS_IRQ_Msk & ((value) << TAL_INTSTATUS_IRQ_Pos)) argument
423 #define TAL_DMACPUSEL0_CH0(value) (TAL_DMACPUSEL0_CH0_Msk & ((value) << TAL_DMACPUSEL0_CH0_Pos)) argument
426 #define TAL_DMACPUSEL0_CH1(value) (TAL_DMACPUSEL0_CH1_Msk & ((value) << TAL_DMACPUSEL0_CH1_Pos)) argument
429 #define TAL_DMACPUSEL0_CH2(value) (TAL_DMACPUSEL0_CH2_Msk & ((value) << TAL_DMACPUSEL0_CH2_Pos)) argument
432 #define TAL_DMACPUSEL0_CH3(value) (TAL_DMACPUSEL0_CH3_Msk & ((value) << TAL_DMACPUSEL0_CH3_Pos)) argument
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Dnvmctrl.h58 #define NVMCTRL_CTRLA_CMD(value) (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos)) argument
91 #define NVMCTRL_CTRLA_CMDEX(value) (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos)) argument
121 #define NVMCTRL_CTRLB_RWS(value) (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos)) argument
132 #define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEP… argument
143 #define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READM… argument
172 #define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos)) argument
175 #define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos)) argument
194 #define NVMCTRL_PARAM_RWWEEP(value) (NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Po… argument
310 #define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos)) argument
327 #define NVMCTRL_LOCK_LOCK(value) (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos)) argument
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Dport.h56 #define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos)) argument
74 #define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos)) argument
92 #define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos)) argument
110 #define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos)) argument
128 #define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos)) argument
146 #define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos)) argument
164 #define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos)) argument
182 #define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos)) argument
200 #define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos)) argument
218 #define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)) argument
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Ddsu.h138 #define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)) argument
159 #define DSU_ADDR_AMOD(value) (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos)) argument
162 #define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)) argument
181 #define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)) argument
199 #define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)) argument
217 #define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)) argument
240 #define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)) argument
243 #define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)) argument
246 #define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)) argument
249 #define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)) argument
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Dtcc.h81 #define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Po… argument
92 #define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos)) argument
113 #define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos)) argument
136 #define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos)) argument
164 #define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos)) argument
175 #define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos)) argument
215 #define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos)) argument
226 #define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos)) argument
297 #define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos)) argument
327 #define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos)) argument
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Dac.h87 #define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) argument
129 #define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) argument
134 #define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) argument
141 #define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) argument
148 #define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) argument
180 #define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) argument
185 #define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) argument
217 #define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) argument
222 #define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) argument
254 #define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) argument
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Ddac.h81 #define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) argument
123 #define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) argument
130 #define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) argument
137 #define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) argument
168 #define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN… argument
175 #define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) argument
206 #define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN… argument
213 #define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) argument
244 #define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Po… argument
251 #define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) argument
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Drtc.h67 #define RTC_MODE0_CTRLA_MODE(value) (RTC_MODE0_CTRLA_MODE_Msk & ((value) << RTC_MODE0_CTRLA_MODE_Po… argument
78 #define RTC_MODE0_CTRLA_PRESCALER(value) (RTC_MODE0_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE0_CTR… argument
132 #define RTC_MODE1_CTRLA_MODE(value) (RTC_MODE1_CTRLA_MODE_Msk & ((value) << RTC_MODE1_CTRLA_MODE_Po… argument
141 #define RTC_MODE1_CTRLA_PRESCALER(value) (RTC_MODE1_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE1_CTR… argument
197 #define RTC_MODE2_CTRLA_MODE(value) (RTC_MODE2_CTRLA_MODE_Msk & ((value) << RTC_MODE2_CTRLA_MODE_Po… argument
210 #define RTC_MODE2_CTRLA_PRESCALER(value) (RTC_MODE2_CTRLA_PRESCALER_Msk & ((value) << RTC_MODE2_CTR… argument
286 #define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PE… argument
291 #define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CM… argument
344 #define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PE… argument
351 #define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CM… argument
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Deic.h84 #define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Po… argument
158 #define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos)) argument
177 #define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos)) argument
196 #define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos)) argument
215 #define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos)) argument
234 #define EIC_ASYNCH_ASYNCH(value) (EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_ASYNCH_ASYNCH_Pos)) argument
267 #define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos)) argument
284 #define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos)) argument
301 #define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos)) argument
318 #define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos)) argument
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Dtc.h81 #define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos)) argument
90 #define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos)) argument
103 #define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos)) argument
128 #define TC_CTRLA_CAPTEN(value) (TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos)) argument
135 #define TC_CTRLA_COPEN(value) (TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos)) argument
163 #define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos)) argument
203 #define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos)) argument
247 #define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos)) argument
276 #define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)) argument
312 #define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)) argument
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Dpm.h76 #define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE… argument
104 #define PM_PLCFG_PLSEL(value) (PM_PLCFG_PLSEL_Msk & ((value) << PM_PLCFG_PLSEL_Pos)) argument
192 #define PM_STDBYCFG_PDCFG(value) (PM_STDBYCFG_PDCFG_Msk & ((value) << PM_STDBYCFG_PDCFG_Pos)) argument
207 #define PM_STDBYCFG_VREGSMOD(value) (PM_STDBYCFG_VREGSMOD_Msk & ((value) << PM_STDBYCFG_VREGSMOD_Po… argument
216 #define PM_STDBYCFG_LINKPD(value) (PM_STDBYCFG_LINKPD_Msk & ((value) << PM_STDBYCFG_LINKPD_Pos)) argument
227 #define PM_STDBYCFG_BBIASHS(value) (PM_STDBYCFG_BBIASHS_Msk & ((value) << PM_STDBYCFG_BBIASHS_Pos)) argument
230 #define PM_STDBYCFG_BBIASLP(value) (PM_STDBYCFG_BBIASLP_Msk & ((value) << PM_STDBYCFG_BBIASLP_Pos)) argument
233 #define PM_STDBYCFG_BBIASPP(value) (PM_STDBYCFG_BBIASPP_Msk & ((value) << PM_STDBYCFG_BBIASPP_Pos)) argument
252 #define PM_PWSAKDLY_DLYVAL(value) (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos)) argument
Dusb.h110 #define USB_QOSCTRL_CQOS(value) (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos)) argument
113 #define USB_QOSCTRL_DQOS(value) (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos)) argument
145 #define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRL… argument
168 #define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRL… argument
207 #define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDC… argument
244 #define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Po… argument
266 #define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Po… argument
289 #define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS… argument
298 #define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVIC… argument
325 #define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED… argument
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Dsercom.h76 #define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_M… argument
83 #define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_C… argument
90 #define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA… argument
95 #define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM… argument
135 #define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_M… argument
142 #define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_C… argument
147 #define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA… argument
188 #define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE… argument
195 #define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO… argument
198 #define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO… argument
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Ddmac.h83 #define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) argument
105 #define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CR… argument
114 #define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Po… argument
121 #define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) argument
143 #define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_… argument
161 #define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_… argument
221 #define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)) argument
232 #define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)) argument
243 #define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)) argument
321 #define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWT… argument
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Dopamp.h93 #define OPAMP_STATUS_READY(value) (OPAMP_STATUS_READY_Msk & ((value) << OPAMP_STATUS_READY_Pos)) argument
130 #define OPAMP_OPAMPCTRL_BIAS(value) (OPAMP_OPAMPCTRL_BIAS_Msk & ((value) << OPAMP_OPAMPCTRL_BIAS_Po… argument
143 #define OPAMP_OPAMPCTRL_RES1MUX(value) (OPAMP_OPAMPCTRL_RES1MUX_Msk & ((value) << OPAMP_OPAMPCTRL_R… argument
146 #define OPAMP_OPAMPCTRL_POTMUX(value) (OPAMP_OPAMPCTRL_POTMUX_Msk & ((value) << OPAMP_OPAMPCTRL_POT… argument
149 #define OPAMP_OPAMPCTRL_MUXPOS(value) (OPAMP_OPAMPCTRL_MUXPOS_Msk & ((value) << OPAMP_OPAMPCTRL_MUX… argument
152 #define OPAMP_OPAMPCTRL_MUXNEG(value) (OPAMP_OPAMPCTRL_MUXNEG_Msk & ((value) << OPAMP_OPAMPCTRL_MUX… argument
/loramac-node-3.4.0/src/boards/mcu/stm32/cmsis/
Dcmsis_armcc.h388 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) in __REV16()
402 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) in __REVSH()
427 #define __BKPT(value) __breakpoint(value) argument
439 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) in __RBIT()
516 #define __STREXB(value, ptr) __strex(value, ptr) argument
518 …#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) … argument
531 #define __STREXH(value, ptr) __strex(value, ptr) argument
533 …#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) … argument
546 #define __STREXW(value, ptr) __strex(value, ptr) argument
548 …#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) … argument
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/loramac-node-3.4.0/src/boards/mcu/saml21/hri/
Dhri_mclk_l21.h85 static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) in hri_mclk_write_INTEN_CKRDY_bit()
489 static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value) in hri_mclk_write_AHBMASK_HPB0_bit()
529 static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value) in hri_mclk_write_AHBMASK_HPB1_bit()
569 static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value) in hri_mclk_write_AHBMASK_HPB2_bit()
609 static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value) in hri_mclk_write_AHBMASK_HPB3_bit()
649 static inline void hri_mclk_write_AHBMASK_HPB4_bit(const void *const hw, bool value) in hri_mclk_write_AHBMASK_HPB4_bit()
689 static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value) in hri_mclk_write_AHBMASK_DSU_bit()
729 static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) in hri_mclk_write_AHBMASK_NVMCTRL_bit()
769 static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value) in hri_mclk_write_AHBMASK_HSRAM_bit()
809 static inline void hri_mclk_write_AHBMASK_LPRAM_bit(const void *const hw, bool value) in hri_mclk_write_AHBMASK_LPRAM_bit()
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Dhri_tal_l21.h95 static inline void hri_tal_write_INTEN_BRK_bit(const void *const hw, bool value) in hri_tal_write_INTEN_BRK_bit()
220 static inline void hri_tal_write_CTRLA_ENABLE_bit(const void *const hw, bool value) in hri_tal_write_CTRLA_ENABLE_bit()
342 static inline void hri_tal_write_EXTCTRL_ENABLE_bit(const void *const hw, bool value) in hri_tal_write_EXTCTRL_ENABLE_bit()
382 static inline void hri_tal_write_EXTCTRL_INV_bit(const void *const hw, bool value) in hri_tal_write_EXTCTRL_INV_bit()
463 static inline void hri_tal_write_EVCTRL_BRKEI_bit(const void *const hw, bool value) in hri_tal_write_EVCTRL_BRKEI_bit()
503 static inline void hri_tal_write_EVCTRL_BRKEO_bit(const void *const hw, bool value) in hri_tal_write_EVCTRL_BRKEO_bit()
584 static inline void hri_tal_write_GLOBMASK_CM0P_bit(const void *const hw, bool value) in hri_tal_write_GLOBMASK_CM0P_bit()
624 static inline void hri_tal_write_GLOBMASK_PPP_bit(const void *const hw, bool value) in hri_tal_write_GLOBMASK_PPP_bit()
664 static inline void hri_tal_write_GLOBMASK_EVBRK_bit(const void *const hw, bool value) in hri_tal_write_GLOBMASK_EVBRK_bit()
704 static inline void hri_tal_write_GLOBMASK_EXTBRK_bit(const void *const hw, bool value) in hri_tal_write_GLOBMASK_EXTBRK_bit()
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Dhri_evsys_l21.h80 static inline void hri_evsys_write_INTEN_OVR0_bit(const void *const hw, bool value) in hri_evsys_write_INTEN_OVR0_bit()
104 static inline void hri_evsys_write_INTEN_OVR1_bit(const void *const hw, bool value) in hri_evsys_write_INTEN_OVR1_bit()
128 static inline void hri_evsys_write_INTEN_OVR2_bit(const void *const hw, bool value) in hri_evsys_write_INTEN_OVR2_bit()
152 static inline void hri_evsys_write_INTEN_OVR3_bit(const void *const hw, bool value) in hri_evsys_write_INTEN_OVR3_bit()
176 static inline void hri_evsys_write_INTEN_OVR4_bit(const void *const hw, bool value) in hri_evsys_write_INTEN_OVR4_bit()
200 static inline void hri_evsys_write_INTEN_OVR5_bit(const void *const hw, bool value) in hri_evsys_write_INTEN_OVR5_bit()
224 static inline void hri_evsys_write_INTEN_OVR6_bit(const void *const hw, bool value) in hri_evsys_write_INTEN_OVR6_bit()
248 static inline void hri_evsys_write_INTEN_OVR7_bit(const void *const hw, bool value) in hri_evsys_write_INTEN_OVR7_bit()
272 static inline void hri_evsys_write_INTEN_OVR8_bit(const void *const hw, bool value) in hri_evsys_write_INTEN_OVR8_bit()
296 static inline void hri_evsys_write_INTEN_OVR9_bit(const void *const hw, bool value) in hri_evsys_write_INTEN_OVR9_bit()
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Dhri_tcc_l21.h2479 static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) in hri_tcc_write_CTRLB_DIR_bit()
2503 static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) in hri_tcc_write_CTRLB_LUPD_bit()
2527 static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) in hri_tcc_write_CTRLB_ONESHOT_bit()
2644 static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) in hri_tcc_write_INTEN_OVF_bit()
2668 static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) in hri_tcc_write_INTEN_TRG_bit()
2692 static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) in hri_tcc_write_INTEN_CNT_bit()
2716 static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) in hri_tcc_write_INTEN_ERR_bit()
2740 static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value) in hri_tcc_write_INTEN_UFS_bit()
2764 static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) in hri_tcc_write_INTEN_DFS_bit()
2788 static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) in hri_tcc_write_INTEN_FAULTA_bit()
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Dhri_osc32kctrl_l21.h80 static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) in hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit()
104 static inline void hri_osc32kctrl_write_INTEN_OSC32KRDY_bit(const void *const hw, bool value) in hri_osc32kctrl_write_INTEN_OSC32KRDY_bit()
313 static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) in hri_osc32kctrl_write_XOSC32K_ENABLE_bit()
353 static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) in hri_osc32kctrl_write_XOSC32K_XTALEN_bit()
393 static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) in hri_osc32kctrl_write_XOSC32K_EN32K_bit()
433 static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) in hri_osc32kctrl_write_XOSC32K_EN1K_bit()
473 static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) in hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit()
513 static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) in hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit()
553 static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) in hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit()
684 static inline void hri_osc32kctrl_write_OSC32K_ENABLE_bit(const void *const hw, bool value) in hri_osc32kctrl_write_OSC32K_ENABLE_bit()
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Dhri_oscctrl_l21.h88 static inline void hri_oscctrl_write_INTEN_XOSCRDY_bit(const void *const hw, bool value) in hri_oscctrl_write_INTEN_XOSCRDY_bit()
112 static inline void hri_oscctrl_write_INTEN_OSC16MRDY_bit(const void *const hw, bool value) in hri_oscctrl_write_INTEN_OSC16MRDY_bit()
136 static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) in hri_oscctrl_write_INTEN_DFLLRDY_bit()
160 static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) in hri_oscctrl_write_INTEN_DFLLOOB_bit()
184 static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) in hri_oscctrl_write_INTEN_DFLLLCKF_bit()
208 static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) in hri_oscctrl_write_INTEN_DFLLLCKC_bit()
232 static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) in hri_oscctrl_write_INTEN_DFLLRCS_bit()
256 static inline void hri_oscctrl_write_INTEN_DPLLLCKR_bit(const void *const hw, bool value) in hri_oscctrl_write_INTEN_DPLLLCKR_bit()
280 static inline void hri_oscctrl_write_INTEN_DPLLLCKF_bit(const void *const hw, bool value) in hri_oscctrl_write_INTEN_DPLLLCKF_bit()
304 static inline void hri_oscctrl_write_INTEN_DPLLLTO_bit(const void *const hw, bool value) in hri_oscctrl_write_INTEN_DPLLLTO_bit()
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Dhri_supc_l21.h83 static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) in hri_supc_write_INTEN_BOD33RDY_bit()
107 static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value) in hri_supc_write_INTEN_BOD33DET_bit()
131 static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value) in hri_supc_write_INTEN_B33SRDY_bit()
155 static inline void hri_supc_write_INTEN_BOD12RDY_bit(const void *const hw, bool value) in hri_supc_write_INTEN_BOD12RDY_bit()
179 static inline void hri_supc_write_INTEN_BOD12DET_bit(const void *const hw, bool value) in hri_supc_write_INTEN_BOD12DET_bit()
203 static inline void hri_supc_write_INTEN_B12SRDY_bit(const void *const hw, bool value) in hri_supc_write_INTEN_B12SRDY_bit()
227 static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value) in hri_supc_write_INTEN_VREGRDY_bit()
251 static inline void hri_supc_write_INTEN_APWSRDY_bit(const void *const hw, bool value) in hri_supc_write_INTEN_APWSRDY_bit()
275 static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value) in hri_supc_write_INTEN_VCORERDY_bit()
531 static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value) in hri_supc_write_BOD33_ENABLE_bit()
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/loramac-node-3.4.0/src/apps/LoRaMac/common/
DCayenneLpp.c59 uint8_t CayenneLppAddDigitalInput( uint8_t channel, uint8_t value ) in CayenneLppAddDigitalInput()
72 uint8_t CayenneLppAddDigitalOutput( uint8_t channel, uint8_t value ) in CayenneLppAddDigitalOutput()
86 uint8_t CayenneLppAddAnalogInput( uint8_t channel, float value ) in CayenneLppAddAnalogInput()
102 uint8_t CayenneLppAddAnalogOutput( uint8_t channel, float value ) in CayenneLppAddAnalogOutput()
132 uint8_t CayenneLppAddPresence( uint8_t channel, uint8_t value ) in CayenneLppAddPresence()

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