1 /*! 2 \file gd32e50x_usart.h 3 \brief definitions for the USART 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50x 6 \version 2020-08-26, V1.1.0, firmware for GD32E50x 7 \version 2020-12-21, V1.1.1, firmware for GD32E50x 8 \version 2021-03-23, V1.2.0, firmware for GD32E50x 9 */ 10 11 /* 12 Copyright (c) 2021, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32E50X_USART_H 39 #define GD32E50X_USART_H 40 41 #include "gd32e50x.h" 42 43 /* USARTx(x=0,1,2,5)/UARTx(x=3,4) definitions */ 44 #define USART1 USART_BASE /*!< USART1 base address */ 45 #define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */ 46 #define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */ 47 #define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */ 48 #define USART0 (USART_BASE+0x0000F400U) /*!< USART0 base address */ 49 #define USART5 (USART_BASE+0x00012C00U) /*!< USART5 base address */ 50 51 /* USART registers definitions */ 52 /* USARTx(x=0,1,2)/UARTx(x=3,4)registers definitions */ 53 #define USART_STAT0(usartx) REG32((usartx) + 0x000000000U) /*!< USART status register 0 */ 54 #define USART_DATA(usartx) REG32((usartx) + 0x000000004U) /*!< USART data register */ 55 #define USART_BAUD(usartx) REG32((usartx) + 0x000000008U) /*!< USART baud rate register */ 56 #define USART_CTL0(usartx) REG32((usartx) + 0x00000000CU) /*!< USART control register 0 */ 57 #define USART_CTL1(usartx) REG32((usartx) + 0x000000010U) /*!< USART control register 1 */ 58 #define USART_CTL2(usartx) REG32((usartx) + 0x000000014U) /*!< USART control register 2 */ 59 #define USART_GP(usartx) REG32((usartx) + 0x000000018U) /*!< USART guard time and prescaler register */ 60 #define USART_CTL3(usartx) REG32((usartx) + 0x000000080U) /*!< USART control register 3 */ 61 #define USART_RT(usartx) REG32((usartx) + 0x000000084U) /*!< USART receiver timeout register */ 62 #define USART_STAT1(usartx) REG32((usartx) + 0x000000088U) /*!< USART status register 1 */ 63 #define USART_GDCTL(usartx) REG32((usartx) + 0x0000000D0U) /*!< USART GD control register */ 64 65 /* USART5 registers definitions */ 66 #define USART5_CTL0(usartx) REG32((usartx) + 0x000000000U) /*!< USART5 control register 0 */ 67 #define USART5_CTL1(usartx) REG32((usartx) + 0x000000004U) /*!< USART5 control register 1 */ 68 #define USART5_CTL2(usartx) REG32((usartx) + 0x000000008U) /*!< USART5 control register 2 */ 69 #define USART5_BAUD(usartx) REG32((usartx) + 0x00000000CU) /*!< USART5 baud rate register */ 70 #define USART5_GP(usartx) REG32((usartx) + 0x000000010U) /*!< USART5 guard time and prescaler register */ 71 #define USART5_RT(usartx) REG32((usartx) + 0x000000014U) /*!< USART5 receiver timeout register */ 72 #define USART5_CMD(usartx) REG32((usartx) + 0x000000018U) /*!< USART5 command register */ 73 #define USART5_STAT(usartx) REG32((usartx) + 0x00000001CU) /*!< USART5 status register */ 74 #define USART5_INTC(usartx) REG32((usartx) + 0x000000020U) /*!< USART5 interrupt status clear register */ 75 #define USART5_RDATA(usartx) REG32((usartx) + 0x000000024U) /*!< USART5 receive data register */ 76 #define USART5_TDATA(usartx) REG32((usartx) + 0x000000028U) /*!< USART5 transmit data register */ 77 #define USART5_CHC(usartx) REG32((usartx) + 0x0000000C0U) /*!< USART5 coherence control register */ 78 #define USART5_RFCS(usartx) REG32((usartx) + 0x0000000D0U) /*!< USART5 receive FIFO control and status register */ 79 80 /* USART bits definitions */ 81 /* USARTx(x=0,1,2)/UARTx(x=3,4) bits definitions */ 82 /* USARTx_STAT0 */ 83 #define USART_STAT0_PERR BIT(0) /*!< parity error flag */ 84 #define USART_STAT0_FERR BIT(1) /*!< frame error flag */ 85 #define USART_STAT0_NERR BIT(2) /*!< noise error flag */ 86 #define USART_STAT0_ORERR BIT(3) /*!< overrun error */ 87 #define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ 88 #define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ 89 #define USART_STAT0_TC BIT(6) /*!< transmission complete */ 90 #define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ 91 #define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ 92 #define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ 93 94 /* USARTx_DATA */ 95 #define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ 96 97 /* USARTx_BAUD */ 98 #define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ 99 #define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ 100 101 /* USARTx_CTL0 */ 102 #define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ 103 #define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ 104 #define USART_CTL0_REN BIT(2) /*!< receiver enable */ 105 #define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ 106 #define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ 107 #define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ 108 #define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ 109 #define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ 110 #define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ 111 #define USART_CTL0_PM BIT(9) /*!< parity mode */ 112 #define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ 113 #define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ 114 #define USART_CTL0_WL BIT(12) /*!< word length */ 115 #define USART_CTL0_UEN BIT(13) /*!< USART enable */ 116 #define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ 117 118 /* USARTx_CTL1 */ 119 #define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ 120 #define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ 121 #define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ 122 #define USART_CTL1_CLEN BIT(8) /*!< CK length */ 123 #define USART_CTL1_CPH BIT(9) /*!< CK phase */ 124 #define USART_CTL1_CPL BIT(10) /*!< CK polarity */ 125 #define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ 126 #define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ 127 #define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ 128 129 /* USARTx_CTL2 */ 130 #define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ 131 #define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ 132 #define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ 133 #define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ 134 #define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ 135 #define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ 136 #define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ 137 #define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ 138 #define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ 139 #define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ 140 #define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ 141 #define USART_CTL2_OSB BIT(11) /*!< one sample bit method */ 142 143 /* USARTx_GP */ 144 #define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ 145 #define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ 146 147 /* USARTx_CTL3 */ 148 #define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ 149 #define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ 150 #define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ 151 #define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ 152 #define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ 153 #define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ 154 #define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ 155 #define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ 156 157 /* USARTx_RT */ 158 #define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ 159 #define USART_RT_BL BITS(24,31) /*!< block length */ 160 161 /* USARTx_STAT1 */ 162 #define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ 163 #define USART_STAT1_EBF BIT(12) /*!< end of block flag */ 164 #define USART_STAT1_BSY BIT(16) /*!< busy flag */ 165 166 /* USARTx_GDCR */ 167 #define USART_GDCTL_CDEN BIT(1) /*!< collision detection enable */ 168 #define USART_GDCTL_CD BIT(8) /*!< collision detected status */ 169 #define USART_GDCTL_CDIE BIT(16) /*!< collision detected interrupt enable */ 170 171 /* USART5 bits definitions */ 172 /* USART5_CTL0 */ 173 #define USART5_CTL0_UEN BIT(0) /*!< USART5 enable */ 174 #define USART5_CTL0_UESM BIT(1) /*!< USART5 enable in Deep-sleep mode */ 175 #define USART5_CTL0_REN BIT(2) /*!< receiver enable */ 176 #define USART5_CTL0_TEN BIT(3) /*!< transmitter enable */ 177 #define USART5_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ 178 #define USART5_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ 179 #define USART5_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ 180 #define USART5_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ 181 #define USART5_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ 182 #define USART5_CTL0_PM BIT(9) /*!< parity mode */ 183 #define USART5_CTL0_PCEN BIT(10) /*!< parity check function enable */ 184 #define USART5_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ 185 #define USART5_CTL0_WL BIT(12) /*!< word length */ 186 #define USART5_CTL0_MEN BIT(13) /*!< mute mode enable */ 187 #define USART5_CTL0_AMIE BIT(14) /*!< ADDR match interrupt enable */ 188 #define USART5_CTL0_OVSMOD BIT(15) /*!< oversample mode */ 189 #define USART5_CTL0_RTIE BIT(26) /*!< receiver timeout interrupt enable */ 190 #define USART5_CTL0_EBIE BIT(27) /*!< End of Block interrupt enable */ 191 192 /* USART5_CTL1 */ 193 #define USART5_CTL1_ADDM BIT(4) /*!< address detection mode */ 194 #define USART5_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ 195 #define USART5_CTL1_LBDIE BIT(6) /*!< LIN break detection interrupt enable */ 196 #define USART5_CTL1_CLEN BIT(8) /*!< last bit clock pulse */ 197 #define USART5_CTL1_CPH BIT(9) /*!< clock phase */ 198 #define USART5_CTL1_CPL BIT(10) /*!< clock polarity */ 199 #define USART5_CTL1_CKEN BIT(11) /*!< ck pin enable */ 200 #define USART5_CTL1_STB BITS(12,13) /*!< stop bits length */ 201 #define USART5_CTL1_LMEN BIT(14) /*!< LIN mode enable */ 202 #define USART5_CTL1_STRP BIT(15) /*!< swap TX/RX pins */ 203 #define USART5_CTL1_RINV BIT(16) /*!< RX pin level inversion */ 204 #define USART5_CTL1_TINV BIT(17) /*!< TX pin level inversion */ 205 #define USART5_CTL1_DINV BIT(18) /*!< data bit level inversion */ 206 #define USART5_CTL1_MSBF BIT(19) /*!< most significant bit first */ 207 #define USART5_CTL1_ABDEN BIT(20) /*!< auto baud rate enable */ 208 #define USART5_CTL1_ABDM BITS(21,22) /*!< auto baud rate mode */ 209 #define USART5_CTL1_RTEN BIT(23) /*!< receiver timeout enable */ 210 #define USART5_CTL1_ADDR BITS(24,31) /*!< address of the USART terminal */ 211 212 /* USART5_CTL2 */ 213 #define USART5_CTL2_ERRIE BIT(0) /*!< error interrupt enable in multibuffer communication */ 214 #define USART5_CTL2_IREN BIT(1) /*!< IrDA mode enable */ 215 #define USART5_CTL2_IRLP BIT(2) /*!< IrDA low-power */ 216 #define USART5_CTL2_HDEN BIT(3) /*!< half-duplex enable */ 217 #define USART5_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ 218 #define USART5_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ 219 #define USART5_CTL2_DENR BIT(6) /*!< DMA enable for reception */ 220 #define USART5_CTL2_DENT BIT(7) /*!< DMA enable for transmission */ 221 #define USART5_CTL2_OSB BIT(11) /*!< one sample bit mode */ 222 #define USART5_CTL2_OVRD BIT(12) /*!< overrun disable */ 223 #define USART5_CTL2_DDRE BIT(13) /*!< disable DMA on reception error */ 224 #define USART5_CTL2_SCRTNUM BITS(17,19) /*!< smartcard auto-retry number */ 225 #define USART5_CTL2_WUM BITS(20,21) /*!< wakeup mode from deep-sleep mode */ 226 #define USART5_CTL2_WUIE BIT(22) /*!< wakeup from deep-sleep mode interrupt enable */ 227 228 /* USART5_BAUD */ 229 #define USART5_BAUD_FRADIV BITS(0,3) /*!< fraction of baud-rate divider */ 230 #define USART5_BAUD_INTDIV BITS(4,15) /*!< integer of baud-rate divider */ 231 232 /* USART5_GP */ 233 #define USART5_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ 234 #define USART5_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ 235 236 /* USART5_RT */ 237 #define USART5_RT_RT BITS(0,23) /*!< receiver timeout threshold */ 238 #define USART5_RT_BL BITS(24,31) /*!< block length */ 239 240 /* USART5_CMD */ 241 #define USART5_CMD_ABDCMD BIT(0) /*!< auto baudrate detection command */ 242 #define USART5_CMD_SBKCMD BIT(1) /*!< send break command */ 243 #define USART5_CMD_MMCMD BIT(2) /*!< mute mode command */ 244 #define USART5_CMD_RXFCMD BIT(3) /*!< receive data flush command */ 245 #define USART5_CMD_TXFCMD BIT(4) /*!< transmit data flush request */ 246 247 /* USART5_STAT */ 248 #define USART5_STAT_PERR BIT(0) /*!< parity error flag */ 249 #define USART5_STAT_FERR BIT(1) /*!< frame error flag */ 250 #define USART5_STAT_NERR BIT(2) /*!< noise error flag */ 251 #define USART5_STAT_ORERR BIT(3) /*!< overrun error */ 252 #define USART5_STAT_IDLEF BIT(4) /*!< idle line detected flag */ 253 #define USART5_STAT_RBNE BIT(5) /*!< read data buffer not empty */ 254 #define USART5_STAT_TC BIT(6) /*!< transmission completed */ 255 #define USART5_STAT_TBE BIT(7) /*!< transmit data register empty */ 256 #define USART5_STAT_LBDF BIT(8) /*!< LIN break detected flag */ 257 #define USART5_STAT_RTF BIT(11) /*!< receiver timeout flag */ 258 #define USART5_STAT_EBF BIT(12) /*!< end of block flag */ 259 #define USART5_STAT_ABDE BIT(14) /*!< auto baudrate detection error */ 260 #define USART5_STAT_ABDF BIT(15) /*!< auto baudrate detection flag */ 261 #define USART5_STAT_BSY BIT(16) /*!< busy flag */ 262 #define USART5_STAT_AMF BIT(17) /*!< address match flag */ 263 #define USART5_STAT_SBF BIT(18) /*!< send break flag */ 264 #define USART5_STAT_RWU BIT(19) /*!< receiver wakeup from mute mode */ 265 #define USART5_STAT_WUF BIT(20) /*!< wakeup from deep-sleep mode flag */ 266 #define USART5_STAT_TEA BIT(21) /*!< transmit enable acknowledge flag */ 267 #define USART5_STAT_REA BIT(22) /*!< receive enable acknowledge flag */ 268 269 /* USART5_INTC */ 270 #define USART5_INTC_PEC BIT(0) /*!< parity error clear */ 271 #define USART5_INTC_FEC BIT(1) /*!< frame error flag clear */ 272 #define USART5_INTC_NEC BIT(2) /*!< noise detected clear */ 273 #define USART5_INTC_OREC BIT(3) /*!< overrun error clear */ 274 #define USART5_INTC_IDLEC BIT(4) /*!< idle line detected clear */ 275 #define USART5_INTC_TCC BIT(6) /*!< transmission complete clear */ 276 #define USART5_INTC_LBDC BIT(8) /*!< LIN break detected clear */ 277 #define USART5_INTC_RTC BIT(11) /*!< receiver timeout clear */ 278 #define USART5_INTC_EBC BIT(12) /*!< end of timeout clear */ 279 #define USART5_INTC_AMC BIT(17) /*!< address match clear */ 280 #define USART5_INTC_WUC BIT(20) /*!< wakeup from deep-sleep mode clear */ 281 282 /* USART5_RDATA */ 283 #define USART5_RDATA_RDATA BITS(0,8) /*!< receive data value */ 284 285 /* USART5_TDATA */ 286 #define USART5_TDATA_TDATA BITS(0,8) /*!< transmit data value */ 287 288 /* USART5_CHC */ 289 #define USART5_CHC_EPERR BIT(8) /*!< early parity error flag */ 290 291 /* USART5_RFCS */ 292 #define USART5_RFCS_ELNACK BIT(0) /*!< early NACK */ 293 #define USART5_RFCS_RFEN BIT(8) /*!< receive FIFO enable */ 294 #define USART5_RFCS_RFFIE BIT(9) /*!< receive FIFO full interrupt enable */ 295 #define USART5_RFCS_RFE BIT(10) /*!< receive FIFO empty flag */ 296 #define USART5_RFCS_RFF BIT(11) /*!< receive FIFO full flag */ 297 #define USART5_RFCS_RFCNT BITS(12,14) /*!< receive FIFO counter number */ 298 #define USART5_RFCS_RFFINT BIT(15) /*!< receive FIFO full interrupt flag */ 299 300 /* USARTx(x=0,1,2,5)/UARTx(x=3,4) constants definitions */ 301 /* define the USART bit position and its register index offset */ 302 #define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 303 #define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) 304 #define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 305 #define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ 306 | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) 307 #define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) 308 #define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) 309 310 /* USART register offset */ 311 /* USARTx(x=0,1,2)/UARTx(x=3,4) register offset */ 312 #define USART_STAT0_REG_OFFSET 0x00000000U /*!< STAT0 register offset */ 313 #define USART_STAT1_REG_OFFSET 0x00000088U /*!< STAT1 register offset */ 314 #define USART_CTL0_REG_OFFSET 0x0000000CU /*!< CTL0 register offset */ 315 #define USART_CTL1_REG_OFFSET 0x00000010U /*!< CTL1 register offset */ 316 #define USART_CTL2_REG_OFFSET 0x00000014U /*!< CTL2 register offset */ 317 #define USART_CTL3_REG_OFFSET 0x00000080U /*!< CTL3 register offset */ 318 #define USART_GDCTL_REG_OFFSET 0x000000D0U /*!< GDCTL register offset */ 319 320 /* USART5 register offset */ 321 #define USART5_CTL0_REG_OFFSET 0x00000000U /*!< CTL0 register offset */ 322 #define USART5_CTL1_REG_OFFSET 0x00000004U /*!< CTL1 register offset */ 323 #define USART5_CTL2_REG_OFFSET 0x00000008U /*!< CTL2 register offset */ 324 #define USART5_STAT_REG_OFFSET 0x0000001CU /*!< STAT register offset */ 325 #define USART5_CHC_REG_OFFSET 0x000000C0U /*!< CHC register offset */ 326 #define USART5_RFCS_REG_OFFSET 0x000000D0U /*!< RFCS register offset */ 327 328 /* USART flag definitions */ 329 /* USARTx(x=0,1,2)/UARTx(x=3,4) flags */ 330 typedef enum 331 { 332 /* flags in STAT0 register */ 333 USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ 334 USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ 335 USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ 336 USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */ 337 USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ 338 USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ 339 USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error flag*/ 340 USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */ 341 USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */ 342 USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */ 343 /* flags in STAT1 register */ 344 USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ 345 USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ 346 USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ 347 /* flags in GDCTL register */ 348 USART_FLAG_CD = USART_REGIDX_BIT(USART_GDCTL_REG_OFFSET, 8U), /*!< collision detected flag */ 349 }usart_flag_enum; 350 351 /* USART5 flags */ 352 typedef enum 353 { 354 /* flags in STAT register */ 355 USART5_FLAG_REA = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 22U), /*!< receive enable acknowledge flag */ 356 USART5_FLAG_TEA = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 21U), /*!< transmit enable acknowledge flag */ 357 USART5_FLAG_WU = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 20U), /*!< wakeup from Deep-sleep mode flag */ 358 USART5_FLAG_RWU = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 19U), /*!< receiver wakeup from mute mode */ 359 USART5_FLAG_SB = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 18U), /*!< send break flag */ 360 USART5_FLAG_AM = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 17U), /*!< ADDR match flag */ 361 USART5_FLAG_BSY = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 16U), /*!< busy flag */ 362 USART5_FLAG_ABD = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 15U), /*!< auto baudrate detection flag */ 363 USART5_FLAG_ABDE = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 14U), /*!< auto baudrate detection error */ 364 USART5_FLAG_EB = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 12U), /*!< end of block flag */ 365 USART5_FLAG_RT = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 11U), /*!< receiver timeout flag */ 366 USART5_FLAG_LBD = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ 367 USART5_FLAG_TBE = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ 368 USART5_FLAG_TC = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 6U), /*!< transmission complete */ 369 USART5_FLAG_RBNE = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ 370 USART5_FLAG_IDLE = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 4U), /*!< IDLE line detected flag */ 371 USART5_FLAG_ORERR = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 3U), /*!< overrun error */ 372 USART5_FLAG_NERR = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 2U), /*!< noise error flag */ 373 USART5_FLAG_FERR = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 1U), /*!< frame error flag */ 374 USART5_FLAG_PERR = USART_REGIDX_BIT(USART5_STAT_REG_OFFSET, 0U), /*!< parity error flag */ 375 /* flags in CHC register */ 376 USART5_FLAG_EPERR = USART_REGIDX_BIT(USART5_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ 377 /* flags in RFCS register */ 378 USART5_FLAG_RFFINT = USART_REGIDX_BIT(USART5_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt flag */ 379 USART5_FLAG_RFF = USART_REGIDX_BIT(USART5_RFCS_REG_OFFSET, 11U), /*!< receive FIFO full flag */ 380 USART5_FLAG_RFE = USART_REGIDX_BIT(USART5_RFCS_REG_OFFSET, 10U), /*!< receive FIFO empty flag */ 381 }usart5_flag_enum; 382 383 /* USART interrupt flags */ 384 /* USARTx(x=0,1,2)/UARTx(x=3,4) interrupt flags */ 385 typedef enum 386 { 387 /* interrupt flags in CTL0 register */ 388 USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ 389 USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ 390 USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ 391 USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ 392 USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ 393 USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ 394 /* interrupt flags in CTL1 register */ 395 USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ 396 /* interrupt flags in CTL2 register */ 397 USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ 398 USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ 399 USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ 400 USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ 401 /* interrupt flags in CTL3 register */ 402 USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ 403 USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ 404 /* interrupt flags in GDCTL register */ 405 USART_INT_FLAG_CD = USART_REGIDX_BIT2(USART_GDCTL_REG_OFFSET, 16U, USART_GDCTL_REG_OFFSET, 8U), /*!< collision detected interrupt and flag */ 406 }usart_interrupt_flag_enum; 407 408 /* USART5 interrupt flags */ 409 typedef enum 410 { 411 /* interrupt flags in CTL0 register */ 412 USART5_INT_FLAG_EB = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 27U, USART5_STAT_REG_OFFSET, 12U), /*!< end of block interrupt and flag */ 413 USART5_INT_FLAG_RT = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 26U, USART5_STAT_REG_OFFSET, 11U), /*!< receiver timeout interrupt and flag */ 414 USART5_INT_FLAG_AM = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 14U, USART5_STAT_REG_OFFSET, 17U), /*!< address match interrupt and flag */ 415 USART5_INT_FLAG_PERR = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 8U, USART5_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ 416 USART5_INT_FLAG_TBE = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 7U, USART5_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ 417 USART5_INT_FLAG_TC = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 6U, USART5_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ 418 USART5_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 5U, USART5_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ 419 USART5_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 5U, USART5_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ 420 USART5_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART5_CTL0_REG_OFFSET, 4U, USART5_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ 421 /* interrupt flags in CTL1 register */ 422 USART5_INT_FLAG_LBD = USART_REGIDX_BIT2(USART5_CTL1_REG_OFFSET, 6U, USART5_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ 423 /* interrupt flags in CTL2 register */ 424 USART5_INT_FLAG_WU = USART_REGIDX_BIT2(USART5_CTL2_REG_OFFSET, 22U, USART5_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode interrupt and flag */ 425 USART5_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART5_CTL2_REG_OFFSET, 0U, USART5_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ 426 USART5_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART5_CTL2_REG_OFFSET, 0U, USART5_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error flag */ 427 USART5_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART5_CTL2_REG_OFFSET, 0U, USART5_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ 428 /* interrupt flags in RFCS register */ 429 USART5_INT_FLAG_RFF = USART_REGIDX_BIT2(USART5_RFCS_REG_OFFSET, 9U, USART5_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt and flag */ 430 }usart5_interrupt_flag_enum; 431 432 /* USART interrupt enable or disable */ 433 /* USARTx(x=0,1,2)/UARTx(x=3,4) interrupt enable or disable */ 434 typedef enum 435 { 436 /* interrupt in CTL0 register */ 437 USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ 438 USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ 439 USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ 440 USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ 441 USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ 442 /* interrupt in CTL1 register */ 443 USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ 444 /* interrupt in CTL2 register */ 445 USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ 446 USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ 447 /* interrupt in CTL3 register */ 448 USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< interrupt enable bit of end of block event */ 449 USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */ 450 /* interrupt in GDCTL register */ 451 USART_INT_CD = USART_REGIDX_BIT(USART_GDCTL_REG_OFFSET, 16U), /*!< collision detected interrupt */ 452 }usart_interrupt_enum; 453 454 /* USART5 interrupt enable or disable */ 455 typedef enum 456 { 457 /* interrupt in CTL0 register */ 458 USART5_INT_EB = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 27U), /*!< end of block interrupt */ 459 USART5_INT_RT = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 26U), /*!< receiver timeout interrupt */ 460 USART5_INT_AM = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 14U), /*!< address match interrupt */ 461 USART5_INT_PERR = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ 462 USART5_INT_TBE = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ 463 USART5_INT_TC = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ 464 USART5_INT_RBNE = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ 465 USART5_INT_IDLE = USART_REGIDX_BIT(USART5_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ 466 /* interrupt in CTL1 register */ 467 USART5_INT_LBD = USART_REGIDX_BIT(USART5_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ 468 /* interrupt in CTL2 register */ 469 USART5_INT_WU = USART_REGIDX_BIT(USART5_CTL2_REG_OFFSET, 22U), /*!< wakeup from deep-sleep mode interrupt */ 470 USART5_INT_ERR = USART_REGIDX_BIT(USART5_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ 471 /* interrupt in RFCS register */ 472 USART5_INT_RFF = USART_REGIDX_BIT(USART5_RFCS_REG_OFFSET, 9U), /*!< receive FIFO full interrupt */ 473 }usart5_interrupt_enum; 474 475 /* USART invert configure */ 476 /* USARTx(x=0,1,2)/UARTx(x=3,4) invert configure */ 477 typedef enum 478 { 479 /* data bit level inversion */ 480 USART_DINV_ENABLE, /*!< data bit level inversion */ 481 USART_DINV_DISABLE, /*!< data bit level not inversion */ 482 /* TX pin level inversion */ 483 USART_TXPIN_ENABLE, /*!< TX pin level inversion */ 484 USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ 485 /* RX pin level inversion */ 486 USART_RXPIN_ENABLE, /*!< RX pin level inversion */ 487 USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ 488 }usart_invert_enum; 489 490 /* USART5 invert configure */ 491 typedef enum 492 { 493 /* data bit level inversion */ 494 USART5_DINV_ENABLE, /*!< data bit level inversion */ 495 USART5_DINV_DISABLE, /*!< data bit level not inversion */ 496 /* TX pin level inversion */ 497 USART5_TXPIN_ENABLE, /*!< TX pin level inversion */ 498 USART5_TXPIN_DISABLE, /*!< TX pin level not inversion */ 499 /* RX pin level inversion */ 500 USART5_RXPIN_ENABLE, /*!< RX pin level inversion */ 501 USART5_RXPIN_DISABLE, /*!< RX pin level not inversion */ 502 /* swap TX/RX pins */ 503 USART5_SWAP_ENABLE, /*!< swap TX/RX pins */ 504 USART5_SWAP_DISABLE, /*!< not swap TX/RX pins */ 505 }usart5_invert_enum; 506 507 /* USART bits configure */ 508 /* USARTx(x=1,2,5)/UARTx(X=3,4) bits configure*/ 509 /* USART receiver configure */ 510 #define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) 511 #define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ 512 #define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ 513 514 /* USART transmitter configure */ 515 #define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) 516 #define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ 517 #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ 518 519 /* USART parity bits definitions */ 520 #define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) 521 #define USART_PM_NONE CTL0_PM(0) /*!< no parity */ 522 #define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ 523 #define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ 524 525 /* USART wakeup method in mute mode */ 526 #define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) 527 #define USART_WM_IDLE CTL0_WM(0) /*!< idle Line */ 528 #define USART_WM_ADDR CTL0_WM(1) /*!< address mask */ 529 530 /* USART word length definitions */ 531 #define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) 532 #define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ 533 #define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ 534 535 /* USART oversampling mode definitions */ 536 #define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15)) 537 #define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< 16 bits */ 538 #define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< 8 bits */ 539 540 /* USART LIN break frame length */ 541 #define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) 542 #define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ 543 #define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ 544 545 /* USART CK length */ 546 #define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) 547 #define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ 548 #define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ 549 550 /* USART clock phase */ 551 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) 552 #define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ 553 #define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ 554 555 /* USART clock polarity */ 556 #define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) 557 #define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ 558 #define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ 559 560 /* USART stop bits definitions */ 561 #define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) 562 #define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ 563 #define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ 564 #define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ 565 #define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ 566 567 /* USART IrDA low-power enable */ 568 #define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) 569 #define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ 570 #define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ 571 572 /* USART DMA request for receive configure */ 573 #define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) 574 #define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ 575 #define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ 576 577 /* USART DMA request for transmission configure */ 578 #define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) 579 #define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ 580 #define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ 581 582 /* USART RTS configure */ 583 #define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) 584 #define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ 585 #define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ 586 587 /* USART CTS configure */ 588 #define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) 589 #define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ 590 #define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ 591 592 /* USART one sample bit method configure */ 593 #define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) 594 #define USART_OSB_1bit CTL2_OSB(1) /*!< 1 bit */ 595 #define USART_OSB_3bit CTL2_OSB(0) /*!< 3 bits */ 596 597 /* USARTx(x=0,1,2)/UARTx(x=3,4) bits configure*/ 598 /* USART data is transmitted/received with the LSB/MSB first */ 599 #define CTL3_MSBF(regval) (BIT(11) & ((uint32_t)(regval) << 11)) 600 #define USART_MSBF_LSB CTL3_MSBF(0) /*!< LSB first */ 601 #define USART_MSBF_MSB CTL3_MSBF(1) /*!< MSB first */ 602 603 /* USART collision detection enable */ 604 #define GDCR_CDEN(regval) (BIT(1) & ((uint32_t)(regval) << 1)) 605 #define USART_CDEN_ENABLE GDCR_CDEN(1) /*!< collision detection enable */ 606 #define USART_CDEN_DISABLE GDCR_CDEN(0) /*!< collision detection disable */ 607 608 /* USART collision detected interrupt enable */ 609 #define GDCR_CDIE(regval) (BIT(16) & ((uint32_t)(regval) << 16)) 610 #define USART_CDIE_ENABLE GDCR_CDIE(1) /*!< collision detected interrupt ensable */ 611 #define USART_CDIE_DISABLE GDCR_CDIE(0) /*!< collision detected interrupt disable */ 612 613 /* USART5 bits configure */ 614 /* USART5 address detection mode */ 615 #define CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4)) 616 #define USART5_ADDM_4BIT CTL1_ADDM(0) /*!< 4-bit address detection */ 617 #define USART5_ADDM_FULLBIT CTL1_ADDM(1) /*!< full-bit address detection */ 618 619 /* USART5 data is transmitted/received with the LSB/MSB first */ 620 #define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19)) 621 #define USART5_MSBF_LSB CTL1_MSBF(0) /*!< LSB first */ 622 #define USART5_MSBF_MSB CTL1_MSBF(1) /*!< MSB first */ 623 624 /* USART5 auto baud rate detection mode bits definitions */ 625 #define CTL1_ABDM(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) 626 #define USART5_ABDM_FTOR CTL1_ABDM(0) /*!< falling edge to rising edge measurement */ 627 #define USART5_ABDM_FTOF CTL1_ABDM(1) /*!< falling edge to falling edge measurement */ 628 629 /* USART5 wakeup mode from deep-sleep mode */ 630 #define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) 631 #define USART5_WUM_ADDR CTL2_WUM(0) /*!< WUF active on address match */ 632 #define USART5_WUM_STARTB CTL2_WUM(2) /*!< WUF active on start bit */ 633 #define USART5_WUM_RBNE CTL2_WUM(3) /*!< WUF active on RBNE */ 634 635 636 /* USARTx(x=0,1,2,5)/UARTx(x=3,4) function declarations */ 637 /* initialization functions */ 638 /* reset USART */ 639 void usart_deinit(uint32_t usart_periph); 640 /* configure usart baud rate value */ 641 void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); 642 /* configure usart parity function */ 643 void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); 644 /* configure usart word length */ 645 void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); 646 /* configure usart stop bit length */ 647 void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); 648 /* enable usart */ 649 void usart_enable(uint32_t usart_periph); 650 /* disable usart */ 651 void usart_disable(uint32_t usart_periph); 652 /* configure USART transmitter */ 653 void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); 654 /* configure USART receiver */ 655 void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); 656 657 /* normal mode communication */ 658 /* configure the USART oversample mode */ 659 void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp); 660 /* configure sample bit method */ 661 void usart_sample_bit_config(uint32_t usart_periph, uint32_t obsm); 662 /* enable receiver timeout */ 663 void usart_receiver_timeout_enable(uint32_t usart_periph); 664 /* disable receiver timeout */ 665 void usart_receiver_timeout_disable(uint32_t usart_periph); 666 /* configure receiver timeout threshold */ 667 void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); 668 /* USART transmit data function */ 669 void usart_data_transmit(uint32_t usart_periph, uint32_t data); 670 /* USART receive data function */ 671 uint16_t usart_data_receive(uint32_t usart_periph); 672 673 /* multi-processor communication */ 674 /* enable mute mode */ 675 void usart_mute_mode_enable(uint32_t usart_periph); 676 /* disable mute mode */ 677 void usart_mute_mode_disable(uint32_t usart_periph); 678 /* configure wakeup method in mute mode */ 679 void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); 680 681 /* LIN mode communication */ 682 /* enable LIN mode */ 683 void usart_lin_mode_enable(uint32_t usart_periph); 684 /* disable LIN mode */ 685 void usart_lin_mode_disable(uint32_t usart_periph); 686 /* LIN break detection length */ 687 void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); 688 689 /* half-duplex communication */ 690 /* enable half-duplex mode */ 691 void usart_halfduplex_enable(uint32_t usart_periph); 692 /* disable half-duplex mode */ 693 void usart_halfduplex_disable(uint32_t usart_periph); 694 695 /* synchronous communication */ 696 /* enable CK pin in synchronous mode */ 697 void usart_synchronous_clock_enable(uint32_t usart_periph); 698 /* disable CK pin in synchronous mode */ 699 void usart_synchronous_clock_disable(uint32_t usart_periph); 700 /* configure usart synchronous mode parameters */ 701 void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); 702 703 /* smartcard communication */ 704 /* configure guard time value in smartcard mode */ 705 void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); 706 /* enable smartcard mode */ 707 void usart_smartcard_mode_enable(uint32_t usart_periph); 708 /* disable smartcard mode */ 709 void usart_smartcard_mode_disable(uint32_t usart_periph); 710 /* enable NACK in smartcard mode */ 711 void usart_smartcard_mode_nack_enable(uint32_t usart_periph); 712 /* disable NACK in smartcard mode */ 713 void usart_smartcard_mode_nack_disable(uint32_t usart_periph); 714 /* configure smartcard auto-retry number */ 715 void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); 716 /* configure block length */ 717 void usart_block_length_config(uint32_t usart_periph, uint32_t bl); 718 719 /* IrDA communication */ 720 /* enable IrDA mode */ 721 void usart_irda_mode_enable(uint32_t usart_periph); 722 /* disable IrDA mode */ 723 void usart_irda_mode_disable(uint32_t usart_periph); 724 /* configure the peripheral clock prescaler */ 725 void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); 726 /* configure IrDA low-power */ 727 void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); 728 729 /* DMA communication */ 730 /* configure USART DMA for reception */ 731 void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); 732 /* configure USART DMA for transmission */ 733 void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); 734 735 /* USARTx(x=0,1,2)/UARTx(x=3,4) function declarations */ 736 737 /* hardware flow communication */ 738 /* configure hardware flow control RTS */ 739 void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); 740 /* configure hardware flow control CTS */ 741 void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); 742 743 /* normal mode communication */ 744 /* data is transmitted/received with the LSB/MSB first */ 745 void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); 746 /* configure USART inverted */ 747 void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); 748 749 /* multi-processor communication */ 750 /* configure address of the USART */ 751 void usart_address_config(uint32_t usart_periph, uint8_t addr); 752 753 /* LIN mode communication */ 754 /* send break frame */ 755 void usart_send_break(uint32_t usart_periph); 756 757 /* collision detected control */ 758 /* enable collision detected interrupt */ 759 void usart_collision_detected_interrupt_enable(uint32_t usart_periph); 760 /* disable collision detected interrupt */ 761 void usart_collision_detected_interrupt_disable(uint32_t usart_periph); 762 /* enable collision detection */ 763 void usart_collision_detection_enable(uint32_t usart_periph); 764 /* disable collision detection */ 765 void usart_collision_detection_disable(uint32_t usart_periph); 766 767 /* flag & interrupt functions */ 768 /* get flag in STAT0/STAT1 register */ 769 FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); 770 /* clear flag in STAT0/STAT1 register */ 771 void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); 772 /* enable USART interrupt */ 773 void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); 774 /* disable USART interrupt */ 775 void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); 776 /* get USART interrupt and flag status */ 777 FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); 778 /* clear interrupt flag in STAT0/STAT1 register */ 779 void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); 780 781 /* USART5 function declarations */ 782 /* normal mode communication */ 783 /* data is transmitted/received with the LSB/MSB first */ 784 void usart5_data_first_config(uint32_t usart_periph, uint32_t msbf); 785 /* configure USART5 inverted */ 786 void usart5_invert_config(uint32_t usart_periph, usart5_invert_enum invertpara); 787 /* enable the USART5 overrun function */ 788 void usart5_overrun_enable(uint32_t usart_periph); 789 /* disable the USART5 overrun function */ 790 void usart5_overrun_disable(uint32_t usart_periph); 791 792 /* auto baud rate detection */ 793 /* enable auto baud rate detection */ 794 void usart5_autobaud_detection_enable(uint32_t usart_periph); 795 /* disable auto baud rate detection */ 796 void usart5_autobaud_detection_disable(uint32_t usart_periph); 797 /* configure auto baud rate detection mode */ 798 void usart5_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod); 799 800 /* multi-processor communication */ 801 /* configure address of the USART5 */ 802 void usart5_address_config(uint32_t usart_periph, uint8_t addr); 803 /* configure address detection mode */ 804 void usart5_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod); 805 806 /* smartcard communication */ 807 /* enable early NACK in smartcard mode */ 808 void usart5_smartcard_mode_early_nack_enable(uint32_t usart_periph); 809 /* disable early NACK in smartcard mode */ 810 void usart5_smartcard_mode_early_nack_disable(uint32_t usart_periph); 811 812 /* DMA communication */ 813 /* enable DMA on reception error */ 814 void usart5_reception_error_dma_enable(uint32_t usart_periph); 815 /* disable DMA on reception error */ 816 void usart5_reception_error_dma_disable(uint32_t usart_periph); 817 818 /* enable USART to wakeup the mcu from deep-sleep mode */ 819 void usart5_wakeup_enable(uint32_t usart_periph); 820 /* disable USART to wakeup the mcu from deep-sleep mode */ 821 void usart5_wakeup_disable(uint32_t usart_periph); 822 /* configure the USART wakeup mode from deep-sleep mode */ 823 void usart5_wakeup_mode_config(uint32_t usart_periph, uint32_t wum); 824 825 /* USART5 receive FIFO */ 826 /* enable receive FIFO */ 827 void usart5_receive_fifo_enable(uint32_t usart_periph); 828 /* disable receive FIFO */ 829 void usart5_receive_fifo_disable(uint32_t usart_periph); 830 /* read receive FIFO counter number */ 831 uint8_t usart5_receive_fifo_counter_number(uint32_t usart_periph); 832 833 /* flag & interrupt functions */ 834 /* get flag in STAT/RFCS register */ 835 FlagStatus usart5_flag_get(uint32_t usart_periph, usart5_flag_enum flag); 836 /* clear USART status */ 837 void usart5_flag_clear(uint32_t usart_periph, usart5_flag_enum flag); 838 /* enable USART interrupt */ 839 void usart5_interrupt_enable(uint32_t usart_periph, usart5_interrupt_enum interrupt); 840 /* disable USART interrupt */ 841 void usart5_interrupt_disable(uint32_t usart_periph, usart5_interrupt_enum interrupt); 842 /* enable USART command */ 843 void usart5_command_enable(uint32_t usart_periph, uint32_t cmdtype); 844 /* get USART interrupt and flag status */ 845 FlagStatus usart5_interrupt_flag_get(uint32_t usart_periph, usart5_interrupt_flag_enum int_flag); 846 /* clear USART interrupt flag */ 847 void usart5_interrupt_flag_clear(uint32_t usart_periph, usart5_interrupt_flag_enum int_flag); 848 849 #endif /* GD32E50X_USART_H */ 850
