1 /** Copyright 2021 Espressif Systems (Shanghai) PTE LTD 2 * 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #pragma once 16 17 #include <stdint.h> 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 /** Group: FIFO Configuration */ 23 /** Type of fifo register 24 * FIFO data register 25 */ 26 typedef union { 27 struct { 28 /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0; 29 * UART $n accesses FIFO via this register. 30 * Must be a unit32_t not a bitfield as to avoid 31 * a read->write operation during writing. Reading 32 * during writing would impact RX fifo 33 */ 34 uint32_t rxfifo_rd_byte; 35 }; 36 uint32_t val; 37 } uart_fifo_reg_t; 38 39 /** Type of mem_conf register 40 * UART threshold and allocation configuration 41 */ 42 typedef union { 43 struct { 44 uint32_t reserved_0:1; 45 /** rx_size : R/W; bitpos: [3:1]; default: 1; 46 * This register is used to configure the amount of mem allocated for receive-FIFO. 47 * The default number is 128 bytes. 48 */ 49 uint32_t rx_size:3; 50 /** tx_size : R/W; bitpos: [6:4]; default: 1; 51 * This register is used to configure the amount of mem allocated for transmit-FIFO. 52 * The default number is 128 bytes. 53 */ 54 uint32_t tx_size:3; 55 /** rx_flow_thrhd : R/W; bitpos: [16:7]; default: 0; 56 * This register is used to configure the maximum amount of data that can be received 57 * when hardware flow control works. 58 */ 59 uint32_t rx_flow_thrhd:10; 60 /** rx_tout_thrhd : R/W; bitpos: [26:17]; default: 10; 61 * This register is used to configure the threshold time that receiver takes to 62 * receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver 63 * takes more time to receive one byte with rx_tout_en set to 1. 64 */ 65 uint32_t rx_tout_thrhd:10; 66 /** mem_force_pd : R/W; bitpos: [27]; default: 0; 67 * Set this bit to force power down UART memory. 68 */ 69 uint32_t mem_force_pd:1; 70 /** mem_force_pu : R/W; bitpos: [28]; default: 0; 71 * Set this bit to force power up UART memory. 72 */ 73 uint32_t mem_force_pu:1; 74 uint32_t reserved_29:3; 75 }; 76 uint32_t val; 77 } uart_mem_conf_reg_t; 78 79 80 /** Group: Interrupt Register */ 81 /** Type of int_raw register 82 * Raw interrupt status 83 */ 84 typedef union { 85 struct { 86 /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0; 87 * This interrupt raw bit turns to high level when receiver receives more data than 88 * what rxfifo_full_thrhd specifies. 89 */ 90 uint32_t rxfifo_full_int_raw:1; 91 /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1; 92 * This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is 93 * less than what txfifo_empty_thrhd specifies . 94 */ 95 uint32_t txfifo_empty_int_raw:1; 96 /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0; 97 * This interrupt raw bit turns to high level when receiver detects a parity error in 98 * the data. 99 */ 100 uint32_t parity_err_int_raw:1; 101 /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0; 102 * This interrupt raw bit turns to high level when receiver detects a data frame error 103 * . 104 */ 105 uint32_t frm_err_int_raw:1; 106 /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; 107 * This interrupt raw bit turns to high level when receiver receives more data than 108 * the FIFO can store. 109 */ 110 uint32_t rxfifo_ovf_int_raw:1; 111 /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0; 112 * This interrupt raw bit turns to high level when receiver detects the edge change of 113 * DSRn signal. 114 */ 115 uint32_t dsr_chg_int_raw:1; 116 /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0; 117 * This interrupt raw bit turns to high level when receiver detects the edge change of 118 * CTSn signal. 119 */ 120 uint32_t cts_chg_int_raw:1; 121 /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0; 122 * This interrupt raw bit turns to high level when receiver detects a 0 after the stop 123 * bit. 124 */ 125 uint32_t brk_det_int_raw:1; 126 /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0; 127 * This interrupt raw bit turns to high level when receiver takes more time than 128 * rx_tout_thrhd to receive a byte. 129 */ 130 uint32_t rxfifo_tout_int_raw:1; 131 /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0; 132 * This interrupt raw bit turns to high level when receiver recevies Xon char when 133 * uart_sw_flow_con_en is set to 1. 134 */ 135 uint32_t sw_xon_int_raw:1; 136 /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0; 137 * This interrupt raw bit turns to high level when receiver receives Xoff char when 138 * uart_sw_flow_con_en is set to 1. 139 */ 140 uint32_t sw_xoff_int_raw:1; 141 /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0; 142 * This interrupt raw bit turns to high level when receiver detects a glitch in the 143 * middle of a start bit. 144 */ 145 uint32_t glitch_det_int_raw:1; 146 /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; 147 * This interrupt raw bit turns to high level when transmitter completes sending 148 * NULL characters, after all data in Tx-FIFO are sent. 149 */ 150 uint32_t tx_brk_done_int_raw:1; 151 /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; 152 * This interrupt raw bit turns to high level when transmitter has kept the shortest 153 * duration after sending the last data. 154 */ 155 uint32_t tx_brk_idle_done_int_raw:1; 156 /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; 157 * This interrupt raw bit turns to high level when transmitter has send out all data 158 * in FIFO. 159 */ 160 uint32_t tx_done_int_raw:1; 161 /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; 162 * This interrupt raw bit turns to high level when receiver detects a parity error 163 * from the echo of transmitter in rs485 mode. 164 */ 165 uint32_t rs485_parity_err_int_raw:1; 166 /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; 167 * This interrupt raw bit turns to high level when receiver detects a data frame error 168 * from the echo of transmitter in rs485 mode. 169 */ 170 uint32_t rs485_frm_err_int_raw:1; 171 /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0; 172 * This interrupt raw bit turns to high level when detects a clash between transmitter 173 * and receiver in rs485 mode. 174 */ 175 uint32_t rs485_clash_int_raw:1; 176 /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0; 177 * This interrupt raw bit turns to high level when receiver detects the configured 178 * at_cmd char. 179 */ 180 uint32_t at_cmd_char_det_int_raw:1; 181 /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0; 182 * This interrupt raw bit turns to high level when input rxd edge changes more times 183 * than what reg_active_threshold specifies in light sleeping mode. 184 */ 185 uint32_t wakeup_int_raw:1; 186 uint32_t reserved_20:12; 187 }; 188 uint32_t val; 189 } uart_int_raw_reg_t; 190 191 /** Type of int_st register 192 * Masked interrupt status 193 */ 194 typedef union { 195 struct { 196 /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0; 197 * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. 198 */ 199 uint32_t rxfifo_full_int_st:1; 200 /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0; 201 * This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set 202 * to 1. 203 */ 204 uint32_t txfifo_empty_int_st:1; 205 /** parity_err_int_st : RO; bitpos: [2]; default: 0; 206 * This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. 207 */ 208 uint32_t parity_err_int_st:1; 209 /** frm_err_int_st : RO; bitpos: [3]; default: 0; 210 * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. 211 */ 212 uint32_t frm_err_int_st:1; 213 /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0; 214 * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. 215 */ 216 uint32_t rxfifo_ovf_int_st:1; 217 /** dsr_chg_int_st : RO; bitpos: [5]; default: 0; 218 * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. 219 */ 220 uint32_t dsr_chg_int_st:1; 221 /** cts_chg_int_st : RO; bitpos: [6]; default: 0; 222 * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. 223 */ 224 uint32_t cts_chg_int_st:1; 225 /** brk_det_int_st : RO; bitpos: [7]; default: 0; 226 * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. 227 */ 228 uint32_t brk_det_int_st:1; 229 /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0; 230 * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. 231 */ 232 uint32_t rxfifo_tout_int_st:1; 233 /** sw_xon_int_st : RO; bitpos: [9]; default: 0; 234 * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. 235 */ 236 uint32_t sw_xon_int_st:1; 237 /** sw_xoff_int_st : RO; bitpos: [10]; default: 0; 238 * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. 239 */ 240 uint32_t sw_xoff_int_st:1; 241 /** glitch_det_int_st : RO; bitpos: [11]; default: 0; 242 * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. 243 */ 244 uint32_t glitch_det_int_st:1; 245 /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0; 246 * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. 247 */ 248 uint32_t tx_brk_done_int_st:1; 249 /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0; 250 * This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena 251 * is set to 1. 252 */ 253 uint32_t tx_brk_idle_done_int_st:1; 254 /** tx_done_int_st : RO; bitpos: [14]; default: 0; 255 * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. 256 */ 257 uint32_t tx_done_int_st:1; 258 /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0; 259 * This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is 260 * set to 1. 261 */ 262 uint32_t rs485_parity_err_int_st:1; 263 /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0; 264 * This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set 265 * to 1. 266 */ 267 uint32_t rs485_frm_err_int_st:1; 268 /** rs485_clash_int_st : RO; bitpos: [17]; default: 0; 269 * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. 270 */ 271 uint32_t rs485_clash_int_st:1; 272 /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0; 273 * This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set 274 * to 1. 275 */ 276 uint32_t at_cmd_char_det_int_st:1; 277 /** wakeup_int_st : RO; bitpos: [19]; default: 0; 278 * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. 279 */ 280 uint32_t wakeup_int_st:1; 281 uint32_t reserved_20:12; 282 }; 283 uint32_t val; 284 } uart_int_st_reg_t; 285 286 /** Type of int_ena register 287 * Interrupt enable bits 288 */ 289 typedef union { 290 struct { 291 /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0; 292 * This is the enable bit for rxfifo_full_int_st register. 293 */ 294 uint32_t rxfifo_full_int_ena:1; 295 /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0; 296 * This is the enable bit for txfifo_empty_int_st register. 297 */ 298 uint32_t txfifo_empty_int_ena:1; 299 /** parity_err_int_ena : R/W; bitpos: [2]; default: 0; 300 * This is the enable bit for parity_err_int_st register. 301 */ 302 uint32_t parity_err_int_ena:1; 303 /** frm_err_int_ena : R/W; bitpos: [3]; default: 0; 304 * This is the enable bit for frm_err_int_st register. 305 */ 306 uint32_t frm_err_int_ena:1; 307 /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; 308 * This is the enable bit for rxfifo_ovf_int_st register. 309 */ 310 uint32_t rxfifo_ovf_int_ena:1; 311 /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0; 312 * This is the enable bit for dsr_chg_int_st register. 313 */ 314 uint32_t dsr_chg_int_ena:1; 315 /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0; 316 * This is the enable bit for cts_chg_int_st register. 317 */ 318 uint32_t cts_chg_int_ena:1; 319 /** brk_det_int_ena : R/W; bitpos: [7]; default: 0; 320 * This is the enable bit for brk_det_int_st register. 321 */ 322 uint32_t brk_det_int_ena:1; 323 /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0; 324 * This is the enable bit for rxfifo_tout_int_st register. 325 */ 326 uint32_t rxfifo_tout_int_ena:1; 327 /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0; 328 * This is the enable bit for sw_xon_int_st register. 329 */ 330 uint32_t sw_xon_int_ena:1; 331 /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0; 332 * This is the enable bit for sw_xoff_int_st register. 333 */ 334 uint32_t sw_xoff_int_ena:1; 335 /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0; 336 * This is the enable bit for glitch_det_int_st register. 337 */ 338 uint32_t glitch_det_int_ena:1; 339 /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0; 340 * This is the enable bit for tx_brk_done_int_st register. 341 */ 342 uint32_t tx_brk_done_int_ena:1; 343 /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0; 344 * This is the enable bit for tx_brk_idle_done_int_st register. 345 */ 346 uint32_t tx_brk_idle_done_int_ena:1; 347 /** tx_done_int_ena : R/W; bitpos: [14]; default: 0; 348 * This is the enable bit for tx_done_int_st register. 349 */ 350 uint32_t tx_done_int_ena:1; 351 /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0; 352 * This is the enable bit for rs485_parity_err_int_st register. 353 */ 354 uint32_t rs485_parity_err_int_ena:1; 355 /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0; 356 * This is the enable bit for rs485_parity_err_int_st register. 357 */ 358 uint32_t rs485_frm_err_int_ena:1; 359 /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0; 360 * This is the enable bit for rs485_clash_int_st register. 361 */ 362 uint32_t rs485_clash_int_ena:1; 363 /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0; 364 * This is the enable bit for at_cmd_char_det_int_st register. 365 */ 366 uint32_t at_cmd_char_det_int_ena:1; 367 /** wakeup_int_ena : R/W; bitpos: [19]; default: 0; 368 * This is the enable bit for uart_wakeup_int_st register. 369 */ 370 uint32_t wakeup_int_ena:1; 371 uint32_t reserved_20:12; 372 }; 373 uint32_t val; 374 } uart_int_ena_reg_t; 375 376 /** Type of int_clr register 377 * Interrupt clear bits 378 */ 379 typedef union { 380 struct { 381 /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0; 382 * Set this bit to clear the rxfifo_full_int_raw interrupt. 383 */ 384 uint32_t rxfifo_full_int_clr:1; 385 /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0; 386 * Set this bit to clear txfifo_empty_int_raw interrupt. 387 */ 388 uint32_t txfifo_empty_int_clr:1; 389 /** parity_err_int_clr : WT; bitpos: [2]; default: 0; 390 * Set this bit to clear parity_err_int_raw interrupt. 391 */ 392 uint32_t parity_err_int_clr:1; 393 /** frm_err_int_clr : WT; bitpos: [3]; default: 0; 394 * Set this bit to clear frm_err_int_raw interrupt. 395 */ 396 uint32_t frm_err_int_clr:1; 397 /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0; 398 * Set this bit to clear rxfifo_ovf_int_raw interrupt. 399 */ 400 uint32_t rxfifo_ovf_int_clr:1; 401 /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0; 402 * Set this bit to clear the dsr_chg_int_raw interrupt. 403 */ 404 uint32_t dsr_chg_int_clr:1; 405 /** cts_chg_int_clr : WT; bitpos: [6]; default: 0; 406 * Set this bit to clear the cts_chg_int_raw interrupt. 407 */ 408 uint32_t cts_chg_int_clr:1; 409 /** brk_det_int_clr : WT; bitpos: [7]; default: 0; 410 * Set this bit to clear the brk_det_int_raw interrupt. 411 */ 412 uint32_t brk_det_int_clr:1; 413 /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0; 414 * Set this bit to clear the rxfifo_tout_int_raw interrupt. 415 */ 416 uint32_t rxfifo_tout_int_clr:1; 417 /** sw_xon_int_clr : WT; bitpos: [9]; default: 0; 418 * Set this bit to clear the sw_xon_int_raw interrupt. 419 */ 420 uint32_t sw_xon_int_clr:1; 421 /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0; 422 * Set this bit to clear the sw_xoff_int_raw interrupt. 423 */ 424 uint32_t sw_xoff_int_clr:1; 425 /** glitch_det_int_clr : WT; bitpos: [11]; default: 0; 426 * Set this bit to clear the glitch_det_int_raw interrupt. 427 */ 428 uint32_t glitch_det_int_clr:1; 429 /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0; 430 * Set this bit to clear the tx_brk_done_int_raw interrupt.. 431 */ 432 uint32_t tx_brk_done_int_clr:1; 433 /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0; 434 * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. 435 */ 436 uint32_t tx_brk_idle_done_int_clr:1; 437 /** tx_done_int_clr : WT; bitpos: [14]; default: 0; 438 * Set this bit to clear the tx_done_int_raw interrupt. 439 */ 440 uint32_t tx_done_int_clr:1; 441 /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0; 442 * Set this bit to clear the rs485_parity_err_int_raw interrupt. 443 */ 444 uint32_t rs485_parity_err_int_clr:1; 445 /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0; 446 * Set this bit to clear the rs485_frm_err_int_raw interrupt. 447 */ 448 uint32_t rs485_frm_err_int_clr:1; 449 /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0; 450 * Set this bit to clear the rs485_clash_int_raw interrupt. 451 */ 452 uint32_t rs485_clash_int_clr:1; 453 /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0; 454 * Set this bit to clear the at_cmd_char_det_int_raw interrupt. 455 */ 456 uint32_t at_cmd_char_det_int_clr:1; 457 /** wakeup_int_clr : WT; bitpos: [19]; default: 0; 458 * Set this bit to clear the uart_wakeup_int_raw interrupt. 459 */ 460 uint32_t wakeup_int_clr:1; 461 uint32_t reserved_20:12; 462 }; 463 uint32_t val; 464 } uart_int_clr_reg_t; 465 466 467 /** Group: Configuration Register */ 468 /** Type of clkdiv register 469 * Clock divider configuration 470 */ 471 typedef union { 472 struct { 473 /** clkdiv : R/W; bitpos: [11:0]; default: 694; 474 * The integral part of the frequency divider factor. 475 */ 476 uint32_t clkdiv:12; 477 uint32_t reserved_12:8; 478 /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0; 479 * The decimal part of the frequency divider factor. 480 */ 481 uint32_t clkdiv_frag:4; 482 uint32_t reserved_24:8; 483 }; 484 uint32_t val; 485 } uart_clkdiv_reg_t; 486 487 /** Type of rx_filt register 488 * Rx Filter configuration 489 */ 490 typedef union { 491 struct { 492 /** glitch_filt : R/W; bitpos: [7:0]; default: 8; 493 * when input pulse width is lower than this value, the pulse is ignored. 494 */ 495 uint32_t glitch_filt:8; 496 /** glitch_filt_en : R/W; bitpos: [8]; default: 0; 497 * Set this bit to enable Rx signal filter. 498 */ 499 uint32_t glitch_filt_en:1; 500 uint32_t reserved_9:23; 501 }; 502 uint32_t val; 503 } uart_rx_filt_reg_t; 504 505 /** Type of conf0 register 506 * a 507 */ 508 typedef union { 509 struct { 510 /** parity : R/W; bitpos: [0]; default: 0; 511 * This register is used to configure the parity check mode. 512 */ 513 uint32_t parity:1; 514 /** parity_en : R/W; bitpos: [1]; default: 0; 515 * Set this bit to enable uart parity check. 516 */ 517 uint32_t parity_en:1; 518 /** bit_num : R/W; bitpos: [3:2]; default: 3; 519 * This register is used to set the length of data. 520 */ 521 uint32_t bit_num:2; 522 /** stop_bit_num : R/W; bitpos: [5:4]; default: 1; 523 * This register is used to set the length of stop bit. 524 */ 525 uint32_t stop_bit_num:2; 526 /** sw_rts : R/W; bitpos: [6]; default: 0; 527 * This register is used to configure the software rts signal which is used in 528 * software flow control. 529 */ 530 uint32_t sw_rts:1; 531 /** sw_dtr : R/W; bitpos: [7]; default: 0; 532 * This register is used to configure the software dtr signal which is used in 533 * software flow control. 534 */ 535 uint32_t sw_dtr:1; 536 /** txd_brk : R/W; bitpos: [8]; default: 0; 537 * Set this bit to enbale transmitter to send NULL when the process of sending data 538 * is done. 539 */ 540 uint32_t txd_brk:1; 541 /** irda_dplx : R/W; bitpos: [9]; default: 0; 542 * Set this bit to enable IrDA loopback mode. 543 */ 544 uint32_t irda_dplx:1; 545 /** irda_tx_en : R/W; bitpos: [10]; default: 0; 546 * This is the start enable bit for IrDA transmitter. 547 */ 548 uint32_t irda_tx_en:1; 549 /** irda_wctl : R/W; bitpos: [11]; default: 0; 550 * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA 551 * transmitter's 11th bit to 0. 552 */ 553 uint32_t irda_wctl:1; 554 /** irda_tx_inv : R/W; bitpos: [12]; default: 0; 555 * Set this bit to invert the level of IrDA transmitter. 556 */ 557 uint32_t irda_tx_inv:1; 558 /** irda_rx_inv : R/W; bitpos: [13]; default: 0; 559 * Set this bit to invert the level of IrDA receiver. 560 */ 561 uint32_t irda_rx_inv:1; 562 /** loopback : R/W; bitpos: [14]; default: 0; 563 * Set this bit to enable uart loopback test mode. 564 */ 565 uint32_t loopback:1; 566 /** tx_flow_en : R/W; bitpos: [15]; default: 0; 567 * Set this bit to enable flow control function for transmitter. 568 */ 569 uint32_t tx_flow_en:1; 570 /** irda_en : R/W; bitpos: [16]; default: 0; 571 * Set this bit to enable IrDA protocol. 572 */ 573 uint32_t irda_en:1; 574 /** rxfifo_rst : R/W; bitpos: [17]; default: 0; 575 * Set this bit to reset the uart receive-FIFO. 576 */ 577 uint32_t rxfifo_rst:1; 578 /** txfifo_rst : R/W; bitpos: [18]; default: 0; 579 * Set this bit to reset the uart transmit-FIFO. 580 */ 581 uint32_t txfifo_rst:1; 582 /** rxd_inv : R/W; bitpos: [19]; default: 0; 583 * Set this bit to inverse the level value of uart rxd signal. 584 */ 585 uint32_t rxd_inv:1; 586 /** cts_inv : R/W; bitpos: [20]; default: 0; 587 * Set this bit to inverse the level value of uart cts signal. 588 */ 589 uint32_t cts_inv:1; 590 /** dsr_inv : R/W; bitpos: [21]; default: 0; 591 * Set this bit to inverse the level value of uart dsr signal. 592 */ 593 uint32_t dsr_inv:1; 594 /** txd_inv : R/W; bitpos: [22]; default: 0; 595 * Set this bit to inverse the level value of uart txd signal. 596 */ 597 uint32_t txd_inv:1; 598 /** rts_inv : R/W; bitpos: [23]; default: 0; 599 * Set this bit to inverse the level value of uart rts signal. 600 */ 601 uint32_t rts_inv:1; 602 /** dtr_inv : R/W; bitpos: [24]; default: 0; 603 * Set this bit to inverse the level value of uart dtr signal. 604 */ 605 uint32_t dtr_inv:1; 606 /** clk_en : R/W; bitpos: [25]; default: 0; 607 * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes 608 * registers. 609 */ 610 uint32_t clk_en:1; 611 /** err_wr_mask : R/W; bitpos: [26]; default: 0; 612 * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver 613 * stores the data even if the received data is wrong. 614 */ 615 uint32_t err_wr_mask:1; 616 /** autobaud_en : R/W; bitpos: [27]; default: 0; 617 * This is the enable bit for detecting baudrate. 618 */ 619 uint32_t autobaud_en:1; 620 /** mem_clk_en : R/W; bitpos: [28]; default: 1; 621 * UART memory clock gate enable signal. 622 */ 623 uint32_t mem_clk_en:1; 624 uint32_t reserved_29:3; 625 }; 626 uint32_t val; 627 } uart_conf0_reg_t; 628 629 /** Type of conf1 register 630 * Configuration register 1 631 */ 632 typedef union { 633 struct { 634 /** rxfifo_full_thrhd : R/W; bitpos: [9:0]; default: 96; 635 * It will produce rxfifo_full_int interrupt when receiver receives more data than 636 * this register value. 637 */ 638 uint32_t rxfifo_full_thrhd:10; 639 /** txfifo_empty_thrhd : R/W; bitpos: [19:10]; default: 96; 640 * It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less 641 * than this register value. 642 */ 643 uint32_t txfifo_empty_thrhd:10; 644 /** dis_rx_dat_ovf : R/W; bitpos: [20]; default: 0; 645 * Disable UART Rx data overflow detect. 646 */ 647 uint32_t dis_rx_dat_ovf:1; 648 /** rx_tout_flow_dis : R/W; bitpos: [21]; default: 0; 649 * Set this bit to stop accumulating idle_cnt when hardware flow control works. 650 */ 651 uint32_t rx_tout_flow_dis:1; 652 /** rx_flow_en : R/W; bitpos: [22]; default: 0; 653 * This is the flow enable bit for UART receiver. 654 */ 655 uint32_t rx_flow_en:1; 656 /** rx_tout_en : R/W; bitpos: [23]; default: 0; 657 * This is the enble bit for uart receiver's timeout function. 658 */ 659 uint32_t rx_tout_en:1; 660 uint32_t reserved_24:8; 661 }; 662 uint32_t val; 663 } uart_conf1_reg_t; 664 665 /** Type of flow_conf register 666 * Software flow-control configuration 667 */ 668 typedef union { 669 struct { 670 /** sw_flow_con_en : R/W; bitpos: [0]; default: 0; 671 * Set this bit to enable software flow control. It is used with register sw_xon or 672 * sw_xoff. 673 */ 674 uint32_t sw_flow_con_en:1; 675 /** xonoff_del : R/W; bitpos: [1]; default: 0; 676 * Set this bit to remove flow control char from the received data. 677 */ 678 uint32_t xonoff_del:1; 679 /** force_xon : R/W; bitpos: [2]; default: 0; 680 * Set this bit to enable the transmitter to go on sending data. 681 */ 682 uint32_t force_xon:1; 683 /** force_xoff : R/W; bitpos: [3]; default: 0; 684 * Set this bit to stop the transmitter from sending data. 685 */ 686 uint32_t force_xoff:1; 687 /** send_xon : R/W/SS/SC; bitpos: [4]; default: 0; 688 * Set this bit to send Xon char. It is cleared by hardware automatically. 689 */ 690 uint32_t send_xon:1; 691 /** send_xoff : R/W/SS/SC; bitpos: [5]; default: 0; 692 * Set this bit to send Xoff char. It is cleared by hardware automatically. 693 */ 694 uint32_t send_xoff:1; 695 uint32_t reserved_6:26; 696 }; 697 uint32_t val; 698 } uart_flow_conf_reg_t; 699 700 /** Type of sleep_conf register 701 * Sleep-mode configuration 702 */ 703 typedef union { 704 struct { 705 /** active_threshold : R/W; bitpos: [9:0]; default: 240; 706 * The uart is activated from light sleeping mode when the input rxd edge changes more 707 * times than this register value. 708 */ 709 uint32_t active_threshold:10; 710 uint32_t reserved_10:22; 711 }; 712 uint32_t val; 713 } uart_sleep_conf_reg_t; 714 715 /** Type of swfc_conf0 register 716 * Software flow-control character configuration 717 */ 718 typedef union { 719 struct { 720 /** xoff_threshold : R/W; bitpos: [9:0]; default: 224; 721 * When the data amount in Rx-FIFO is more than this register value with 722 * uart_sw_flow_con_en set to 1, it will send a Xoff char. 723 */ 724 uint32_t xoff_threshold:10; 725 /** xoff_char : R/W; bitpos: [17:10]; default: 19; 726 * This register stores the Xoff flow control char. 727 */ 728 uint32_t xoff_char:8; 729 uint32_t reserved_18:14; 730 }; 731 uint32_t val; 732 } uart_swfc_conf0_reg_t; 733 734 /** Type of swfc_conf1 register 735 * Software flow-control character configuration 736 */ 737 typedef union { 738 struct { 739 /** xon_threshold : R/W; bitpos: [9:0]; default: 0; 740 * When the data amount in Rx-FIFO is less than this register value with 741 * uart_sw_flow_con_en set to 1, it will send a Xon char. 742 */ 743 uint32_t xon_threshold:10; 744 /** xon_char : R/W; bitpos: [17:10]; default: 17; 745 * This register stores the Xon flow control char. 746 */ 747 uint32_t xon_char:8; 748 uint32_t reserved_18:14; 749 }; 750 uint32_t val; 751 } uart_swfc_conf1_reg_t; 752 753 /** Type of txbrk_conf register 754 * Tx Break character configuration 755 */ 756 typedef union { 757 struct { 758 /** tx_brk_num : R/W; bitpos: [7:0]; default: 10; 759 * This register is used to configure the number of 0 to be sent after the process of 760 * sending data is done. It is active when txd_brk is set to 1. 761 */ 762 uint32_t tx_brk_num:8; 763 uint32_t reserved_8:24; 764 }; 765 uint32_t val; 766 } uart_txbrk_conf_reg_t; 767 768 /** Type of idle_conf register 769 * Frame-end idle configuration 770 */ 771 typedef union { 772 struct { 773 /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256; 774 * It will produce frame end signal when receiver takes more time to receive one byte 775 * data than this register value. 776 */ 777 uint32_t rx_idle_thrhd:10; 778 /** tx_idle_num : R/W; bitpos: [19:10]; default: 256; 779 * This register is used to configure the duration time between transfers. 780 */ 781 uint32_t tx_idle_num:10; 782 uint32_t reserved_20:12; 783 }; 784 uint32_t val; 785 } uart_idle_conf_reg_t; 786 787 /** Type of rs485_conf register 788 * RS485 mode configuration 789 */ 790 typedef union { 791 struct { 792 /** rs485_en : R/W; bitpos: [0]; default: 0; 793 * Set this bit to choose the rs485 mode. 794 */ 795 uint32_t rs485_en:1; 796 /** dl0_en : R/W; bitpos: [1]; default: 0; 797 * Set this bit to delay the stop bit by 1 bit. 798 */ 799 uint32_t dl0_en:1; 800 /** dl1_en : R/W; bitpos: [2]; default: 0; 801 * Set this bit to delay the stop bit by 1 bit. 802 */ 803 uint32_t dl1_en:1; 804 /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0; 805 * Set this bit to enable receiver could receive data when the transmitter is 806 * transmitting data in rs485 mode. 807 */ 808 uint32_t rs485tx_rx_en:1; 809 /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0; 810 * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. 811 */ 812 uint32_t rs485rxby_tx_en:1; 813 /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0; 814 * This register is used to delay the receiver's internal data signal. 815 */ 816 uint32_t rs485_rx_dly_num:1; 817 /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0; 818 * This register is used to delay the transmitter's internal data signal. 819 */ 820 uint32_t rs485_tx_dly_num:4; 821 uint32_t reserved_10:22; 822 }; 823 uint32_t val; 824 } uart_rs485_conf_reg_t; 825 826 /** Type of clk_conf register 827 * UART core clock configuration 828 */ 829 typedef union { 830 struct { 831 /** sclk_div_b : R/W; bitpos: [5:0]; default: 0; 832 * The denominator of the frequency divider factor. 833 */ 834 uint32_t sclk_div_b:6; 835 /** sclk_div_a : R/W; bitpos: [11:6]; default: 0; 836 * The numerator of the frequency divider factor. 837 */ 838 uint32_t sclk_div_a:6; 839 /** sclk_div_num : R/W; bitpos: [19:12]; default: 1; 840 * The integral part of the frequency divider factor. 841 */ 842 uint32_t sclk_div_num:8; 843 /** sclk_sel : R/W; bitpos: [21:20]; default: 3; 844 * UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL. 845 */ 846 uint32_t sclk_sel:2; 847 /** sclk_en : R/W; bitpos: [22]; default: 1; 848 * Set this bit to enable UART Tx/Rx clock. 849 */ 850 uint32_t sclk_en:1; 851 /** rst_core : R/W; bitpos: [23]; default: 0; 852 * Write 1 then write 0 to this bit, reset UART Tx/Rx. 853 */ 854 uint32_t rst_core:1; 855 /** tx_sclk_en : R/W; bitpos: [24]; default: 1; 856 * Set this bit to enable UART Tx clock. 857 */ 858 uint32_t tx_sclk_en:1; 859 /** rx_sclk_en : R/W; bitpos: [25]; default: 1; 860 * Set this bit to enable UART Rx clock. 861 */ 862 uint32_t rx_sclk_en:1; 863 /** tx_rst_core : R/W; bitpos: [26]; default: 0; 864 * Write 1 then write 0 to this bit, reset UART Tx. 865 */ 866 uint32_t tx_rst_core:1; 867 /** rx_rst_core : R/W; bitpos: [27]; default: 0; 868 * Write 1 then write 0 to this bit, reset UART Rx. 869 */ 870 uint32_t rx_rst_core:1; 871 uint32_t reserved_28:4; 872 }; 873 uint32_t val; 874 } uart_clk_conf_reg_t; 875 876 877 /** Group: Status Register */ 878 /** Type of status register 879 * UART status register 880 */ 881 typedef union { 882 struct { 883 /** rxfifo_cnt : RO; bitpos: [9:0]; default: 0; 884 * Stores the byte number of valid data in Rx-FIFO. 885 */ 886 uint32_t rxfifo_cnt:10; 887 uint32_t reserved_10:3; 888 /** dsrn : RO; bitpos: [13]; default: 0; 889 * The register represent the level value of the internal uart dsr signal. 890 */ 891 uint32_t dsrn:1; 892 /** ctsn : RO; bitpos: [14]; default: 1; 893 * This register represent the level value of the internal uart cts signal. 894 */ 895 uint32_t ctsn:1; 896 /** rxd : RO; bitpos: [15]; default: 1; 897 * This register represent the level value of the internal uart rxd signal. 898 */ 899 uint32_t rxd:1; 900 /** txfifo_cnt : RO; bitpos: [25:16]; default: 0; 901 * Stores the byte number of data in Tx-FIFO. 902 */ 903 uint32_t txfifo_cnt:10; 904 uint32_t reserved_26:3; 905 /** dtrn : RO; bitpos: [29]; default: 1; 906 * This bit represents the level of the internal uart dtr signal. 907 */ 908 uint32_t dtrn:1; 909 /** rtsn : RO; bitpos: [30]; default: 1; 910 * This bit represents the level of the internal uart rts signal. 911 */ 912 uint32_t rtsn:1; 913 /** txd : RO; bitpos: [31]; default: 1; 914 * This bit represents the level of the internal uart txd signal. 915 */ 916 uint32_t txd:1; 917 }; 918 uint32_t val; 919 } uart_status_reg_t; 920 921 /** Type of mem_tx_status register 922 * Tx-FIFO write and read offset address. 923 */ 924 typedef union { 925 struct { 926 /** apb_tx_waddr : RO; bitpos: [9:0]; default: 0; 927 * This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via 928 * APB. 929 */ 930 uint32_t apb_tx_waddr:10; 931 uint32_t reserved_10:1; 932 /** tx_raddr : RO; bitpos: [20:11]; default: 0; 933 * This register stores the offset address in Tx-FIFO when Tx-FSM reads data via 934 * Tx-FIFO_Ctrl. 935 */ 936 uint32_t tx_raddr:10; 937 uint32_t reserved_21:11; 938 }; 939 uint32_t val; 940 } uart_mem_tx_status_reg_t; 941 942 /** Type of mem_rx_status register 943 * Rx-FIFO write and read offset address. 944 */ 945 typedef union { 946 struct { 947 /** apb_rx_raddr : RO; bitpos: [9:0]; default: 512; 948 * This register stores the offset address in RX-FIFO when software reads data from 949 * Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300. 950 */ 951 uint32_t apb_rx_raddr:10; 952 uint32_t reserved_10:1; 953 /** rx_waddr : RO; bitpos: [20:11]; default: 512; 954 * This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes 955 * Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300. 956 */ 957 uint32_t rx_waddr:10; 958 uint32_t reserved_21:11; 959 }; 960 uint32_t val; 961 } uart_mem_rx_status_reg_t; 962 963 /** Type of fsm_status register 964 * UART transmit and receive status. 965 */ 966 typedef union { 967 struct { 968 /** st_urx_out : RO; bitpos: [3:0]; default: 0; 969 * This is the status register of receiver. 970 */ 971 uint32_t st_urx_out:4; 972 /** st_utx_out : RO; bitpos: [7:4]; default: 0; 973 * This is the status register of transmitter. 974 */ 975 uint32_t st_utx_out:4; 976 uint32_t reserved_8:24; 977 }; 978 uint32_t val; 979 } uart_fsm_status_reg_t; 980 981 982 /** Group: Autobaud Register */ 983 /** Type of lowpulse register 984 * Autobaud minimum low pulse duration register 985 */ 986 typedef union { 987 struct { 988 /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; 989 * This register stores the value of the minimum duration time of the low level pulse. 990 * It is used in baud rate-detect process. 991 */ 992 uint32_t lowpulse_min_cnt:12; 993 uint32_t reserved_12:20; 994 }; 995 uint32_t val; 996 } uart_lowpulse_reg_t; 997 998 /** Type of highpulse register 999 * Autobaud minimum high pulse duration register 1000 */ 1001 typedef union { 1002 struct { 1003 /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095; 1004 * This register stores the value of the maxinum duration time for the high level 1005 * pulse. It is used in baud rate-detect process. 1006 */ 1007 uint32_t highpulse_min_cnt:12; 1008 uint32_t reserved_12:20; 1009 }; 1010 uint32_t val; 1011 } uart_highpulse_reg_t; 1012 1013 /** Type of rxd_cnt register 1014 * Autobaud edge change count register 1015 */ 1016 typedef union { 1017 struct { 1018 /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0; 1019 * This register stores the count of rxd edge change. It is used in baud rate-detect 1020 * process. 1021 */ 1022 uint32_t rxd_edge_cnt:10; 1023 uint32_t reserved_10:22; 1024 }; 1025 uint32_t val; 1026 } uart_rxd_cnt_reg_t; 1027 1028 /** Type of pospulse register 1029 * Autobaud high pulse register 1030 */ 1031 typedef union { 1032 struct { 1033 /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095; 1034 * This register stores the minimal input clock count between two positive edges. It 1035 * is used in boudrate-detect process. 1036 */ 1037 uint32_t posedge_min_cnt:12; 1038 uint32_t reserved_12:20; 1039 }; 1040 uint32_t val; 1041 } uart_pospulse_reg_t; 1042 1043 /** Type of negpulse register 1044 * Autobaud low pulse register 1045 */ 1046 typedef union { 1047 struct { 1048 /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095; 1049 * This register stores the minimal input clock count between two negative edges. It 1050 * is used in boudrate-detect process. 1051 */ 1052 uint32_t negedge_min_cnt:12; 1053 uint32_t reserved_12:20; 1054 }; 1055 uint32_t val; 1056 } uart_negpulse_reg_t; 1057 1058 1059 /** Group: AT Escape Sequence Selection Configuration */ 1060 /** Type of at_cmd_precnt register 1061 * Pre-sequence timing configuration 1062 */ 1063 typedef union { 1064 struct { 1065 /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305; 1066 * This register is used to configure the idle duration time before the first at_cmd 1067 * is received by receiver. 1068 */ 1069 uint32_t pre_idle_num:16; 1070 uint32_t reserved_16:16; 1071 }; 1072 uint32_t val; 1073 } uart_at_cmd_precnt_reg_t; 1074 1075 /** Type of at_cmd_postcnt register 1076 * Post-sequence timing configuration 1077 */ 1078 typedef union { 1079 struct { 1080 /** post_idle_num : R/W; bitpos: [15:0]; default: 2305; 1081 * This register is used to configure the duration time between the last at_cmd and 1082 * the next data. 1083 */ 1084 uint32_t post_idle_num:16; 1085 uint32_t reserved_16:16; 1086 }; 1087 uint32_t val; 1088 } uart_at_cmd_postcnt_reg_t; 1089 1090 /** Type of at_cmd_gaptout register 1091 * Timeout configuration 1092 */ 1093 typedef union { 1094 struct { 1095 /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11; 1096 * This register is used to configure the duration time between the at_cmd chars. 1097 */ 1098 uint32_t rx_gap_tout:16; 1099 uint32_t reserved_16:16; 1100 }; 1101 uint32_t val; 1102 } uart_at_cmd_gaptout_reg_t; 1103 1104 /** Type of at_cmd_char register 1105 * AT escape sequence detection configuration 1106 */ 1107 typedef union { 1108 struct { 1109 /** at_cmd_char : R/W; bitpos: [7:0]; default: 43; 1110 * This register is used to configure the content of at_cmd char. 1111 */ 1112 uint32_t at_cmd_char:8; 1113 /** char_num : R/W; bitpos: [15:8]; default: 3; 1114 * This register is used to configure the num of continuous at_cmd chars received by 1115 * receiver. 1116 */ 1117 uint32_t char_num:8; 1118 uint32_t reserved_16:16; 1119 }; 1120 uint32_t val; 1121 } uart_at_cmd_char_reg_t; 1122 1123 1124 /** Group: Version Register */ 1125 /** Type of date register 1126 * UART Version register 1127 */ 1128 typedef union { 1129 struct { 1130 /** date : R/W; bitpos: [31:0]; default: 33587824; 1131 * This is the version register. 1132 */ 1133 uint32_t date:32; 1134 }; 1135 uint32_t val; 1136 } uart_date_reg_t; 1137 1138 /** Type of id register 1139 * UART ID register 1140 */ 1141 typedef union { 1142 struct { 1143 /** id : R/W; bitpos: [29:0]; default: 1280; 1144 * This register is used to configure the uart_id. 1145 */ 1146 uint32_t id:30; 1147 /** high_speed : R/W; bitpos: [30]; default: 1; 1148 * This bit used to select synchronize mode. 1: Registers are auto synchronized into 1149 * UART Core clock and UART core should be keep the same with APB clock. 0: After 1150 * configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize 1151 * registers. 1152 */ 1153 uint32_t high_speed:1; 1154 /** reg_update : R/W/SC; bitpos: [31]; default: 0; 1155 * Software write 1 would synchronize registers into UART Core clock domain and would 1156 * be cleared by hardware after synchronization is done. 1157 */ 1158 uint32_t reg_update:1; 1159 }; 1160 uint32_t val; 1161 } uart_id_reg_t; 1162 1163 1164 typedef struct { 1165 volatile uart_fifo_reg_t fifo; 1166 volatile uart_int_raw_reg_t int_raw; 1167 volatile uart_int_st_reg_t int_st; 1168 volatile uart_int_ena_reg_t int_ena; 1169 volatile uart_int_clr_reg_t int_clr; 1170 volatile uart_clkdiv_reg_t clkdiv; 1171 volatile uart_rx_filt_reg_t rx_filt; 1172 volatile uart_status_reg_t status; 1173 volatile uart_conf0_reg_t conf0; 1174 volatile uart_conf1_reg_t conf1; 1175 volatile uart_lowpulse_reg_t lowpulse; 1176 volatile uart_highpulse_reg_t highpulse; 1177 volatile uart_rxd_cnt_reg_t rxd_cnt; 1178 volatile uart_flow_conf_reg_t flow_conf; 1179 volatile uart_sleep_conf_reg_t sleep_conf; 1180 volatile uart_swfc_conf0_reg_t swfc_conf0; 1181 volatile uart_swfc_conf1_reg_t swfc_conf1; 1182 volatile uart_txbrk_conf_reg_t txbrk_conf; 1183 volatile uart_idle_conf_reg_t idle_conf; 1184 volatile uart_rs485_conf_reg_t rs485_conf; 1185 volatile uart_at_cmd_precnt_reg_t at_cmd_precnt; 1186 volatile uart_at_cmd_postcnt_reg_t at_cmd_postcnt; 1187 volatile uart_at_cmd_gaptout_reg_t at_cmd_gaptout; 1188 volatile uart_at_cmd_char_reg_t at_cmd_char; 1189 volatile uart_mem_conf_reg_t mem_conf; 1190 volatile uart_mem_tx_status_reg_t mem_tx_status; 1191 volatile uart_mem_rx_status_reg_t mem_rx_status; 1192 volatile uart_fsm_status_reg_t fsm_status; 1193 volatile uart_pospulse_reg_t pospulse; 1194 volatile uart_negpulse_reg_t negpulse; 1195 volatile uart_clk_conf_reg_t clk_conf; 1196 volatile uart_date_reg_t date; 1197 volatile uart_id_reg_t id; 1198 } uart_dev_t; 1199 1200 extern uart_dev_t UART0; 1201 extern uart_dev_t UART1; 1202 extern uart_dev_t UART2; 1203 1204 #ifndef __cplusplus 1205 _Static_assert(sizeof(uart_dev_t) == 0x84, "Invalid size of uart_dev_t structure"); 1206 _Static_assert(sizeof(UART0.fifo.rxfifo_rd_byte) == 4, "FIFO, must be a uint32_t, not bitfield!"); 1207 _Static_assert(sizeof(UART1.fifo.rxfifo_rd_byte) == 4, "FIFO, must be a uint32_t, not bitfield!"); 1208 _Static_assert(sizeof(UART2.fifo.rxfifo_rd_byte) == 4, "FIFO, must be a uint32_t, not bitfield!"); 1209 #endif 1210 1211 #ifdef __cplusplus 1212 } 1213 #endif 1214
