1 /**************************************************************************//**
2 * @file dac.c
3 * @version V1.00
4 * @brief DAC driver source file
5 *
6 * @copyright SPDX-License-Identifier: Apache-2.0
7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #include "NuMicro.h"
10
11 /** @addtogroup Standard_Driver Standard Driver
12 @{
13 */
14
15 /** @addtogroup DAC_Driver DAC Driver
16 @{
17 */
18
19 /** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions
20 @{
21 */
22
23 /**
24 * @brief This function make DAC module be ready to convert.
25 * @param[in] dac The pointer of the specified DAC module.
26 * @param[in] u32Ch Specified DAC channel.
27 * @param[in] u32TrgSrc Decides the trigger source. Valid values are:
28 * - \ref DAC_WRITE_DAT_TRIGGER :Write DAC_DAT trigger
29 * - \ref DAC_SOFTWARE_TRIGGER :Software trigger
30 * - \ref DAC_LOW_LEVEL_TRIGGER :STDAC pin low level trigger
31 * - \ref DAC_HIGH_LEVEL_TRIGGER :STDAC pin high level trigger
32 * - \ref DAC_FALLING_EDGE_TRIGGER :STDAC pin falling edge trigger
33 * - \ref DAC_RISING_EDGE_TRIGGER :STDAC pin rising edge trigger
34 * - \ref DAC_TIMER0_TRIGGER :Timer 0 trigger
35 * - \ref DAC_TIMER1_TRIGGER :Timer 1 trigger
36 * - \ref DAC_TIMER2_TRIGGER :Timer 2 trigger
37 * - \ref DAC_TIMER3_TRIGGER :Timer 3 trigger
38 * - \ref DAC_EPWM0_TRIGGER :EPWM0 trigger
39 * - \ref DAC_EPWM1_TRIGGER :EPWM1 trigger
40 * @return None
41 * @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger.
42 * When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register.
43 * When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1,
44 * external STDAC pin, timer event, or EPWM event.
45 */
DAC_Open(DAC_T * dac,uint32_t u32Ch,uint32_t u32TrgSrc)46 void DAC_Open(DAC_T *dac,
47 uint32_t u32Ch,
48 uint32_t u32TrgSrc)
49 {
50 (void)u32Ch;
51 dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk);
52
53 dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk);
54 }
55
56 /**
57 * @brief Disable DAC analog power.
58 * @param[in] dac The pointer of the specified DAC module.
59 * @param[in] u32Ch Specfied DAC channel.
60 * @return None
61 * @details Disable DAC analog power for saving power consumption.
62 */
DAC_Close(DAC_T * dac,uint32_t u32Ch)63 void DAC_Close(DAC_T *dac, uint32_t u32Ch)
64 {
65 (void)u32Ch;
66 dac->CTL &= (~DAC_CTL_DACEN_Msk);
67 }
68
69 /**
70 * @brief Set delay time for DAC to become stable.
71 * @param[in] dac The pointer of the specified DAC module.
72 * @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK1*1000000) micro seconds.
73 * @return Real DAC conversion settling time (micro second).
74 * @details For example, DAC controller clock speed is 64MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0x40.
75 * @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed.
76 */
DAC_SetDelayTime(DAC_T * dac,uint32_t u32Delay)77 uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay)
78 {
79
80 dac->TCTL = ((CLK_GetPCLK1Freq() * u32Delay / 1000000UL) & 0x3FFUL);
81
82 return ((dac->TCTL) * 1000000UL / CLK_GetPCLK1Freq());
83 }
84
85
86
87 /**@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
88
89 /**@}*/ /* end of group DAC_Driver */
90
91 /**@}*/ /* end of group Standard_Driver */
92
