1 /*******************************************************************************
2  * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
3  *
4  * SPDX-License-Identifier: MIT
5  *
6  * MPFS HAL Embedded Software
7  *
8  */
9 
10 /***************************************************************************
11  *
12  * @file mss_seg.h
13  * @author Microchip-FPGA Embedded Systems Solutions
14  * @brief segmentation block defines
15  *
16  * These blocks allow the DDR memory to be allocated to cached, non-cached
17  * regions and trace depending on the amount of DDR memory physically connected.
18  * Conceptually an address offset is added/subtracted from the DDR address
19  * provided by the Core Complex to point at a base address in the DDR memory.
20  *
21  * The AXI bus simply passes through the segmentation block, and the address
22  * is modified.
23  *
24  * There are two segmentation blocks, they are grouped into the same address
25  * ranges as the MPU blocks. Each one has seven 32-segmentation registers, but
26  * only two in SEG0 and five in SEG1 are actually implemented.
27  *
28  * DDRC blocker - blocks writes to DDR before it is set-up
29  * SEG0.CFG[7]
30  * Is cleared at reset. When written to '1' disables the blocker function
31  * Is allowing the L2 cache controller to access the DDRC.
32  * Is Once written to '1' the register cannot be written to 0, only an MSS reset
33  * Is will clear the register
34  *
35  */
36 
37 #ifndef MSS_SEG_H
38 #define MSS_SEG_H
39 
40 #include <stdint.h>
41 
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45 
46 typedef struct {
47     union {
48         struct {
49             volatile int32_t    offset : 15;
50             volatile int32_t    rsrvd  : 16;
51             volatile int32_t    locked : 1;
52         } CFG;
53         uint32_t raw;
54     } u[8u];
55 
56     uint32_t fill[64U-8U];
57 
58 } seg_t;
59 
60 #define SEG ((seg_t*) 0x20005d00)
61 
62 #ifdef __cplusplus
63 }
64 #endif
65 
66 #endif /*MSS_SEG_H*/
67