1 /*!
2 \file gd32f3x0_tsi.c
3 \brief TSI driver
4
5 \version 2017-06-06, V1.0.0, firmware for GD32F3x0
6 \version 2019-06-01, V2.0.0, firmware for GD32F3x0
7 \version 2020-09-30, V2.1.0, firmware for GD32F3x0
8 */
9
10 /*
11 Copyright (c) 2020, GigaDevice Semiconductor Inc.
12
13 Redistribution and use in source and binary forms, with or without modification,
14 are permitted provided that the following conditions are met:
15
16 1. Redistributions of source code must retain the above copyright notice, this
17 list of conditions and the following disclaimer.
18 2. Redistributions in binary form must reproduce the above copyright notice,
19 this list of conditions and the following disclaimer in the documentation
20 and/or other materials provided with the distribution.
21 3. Neither the name of the copyright holder nor the names of its contributors
22 may be used to endorse or promote products derived from this software without
23 specific prior written permission.
24
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
34 OF SUCH DAMAGE.
35 */
36
37 #include "gd32f3x0_tsi.h"
38
39 /*!
40 \brief reset TSI peripheral
41 \param[in] none
42 \param[out] none
43 \retval none
44 */
tsi_deinit(void)45 void tsi_deinit(void)
46 {
47 rcu_periph_reset_enable(RCU_TSIRST);
48 rcu_periph_reset_disable(RCU_TSIRST);
49 }
50
51 /*!
52 \brief initialize TSI plus prescaler,charge plus,transfer plus,max cycle number
53 \param[in] prescaler: CTCLK clock division factor
54 only one parameter can be selected which is shown as below:
55 \arg TSI_CTCDIV_DIV1: fCTCLK = fHCLK
56 \arg TSI_CTCDIV_DIV2: fCTCLK = fHCLK/2
57 \arg TSI_CTCDIV_DIV4: fCTCLK = fHCLK/4
58 \arg TSI_CTCDIV_DIV8: fCTCLK = fHCLK/8
59 \arg TSI_CTCDIV_DIV16: fCTCLK = fHCLK/16
60 \arg TSI_CTCDIV_DIV32: fCTCLK = fHCLK/32
61 \arg TSI_CTCDIV_DIV64: fCTCLK = fHCLK/64
62 \arg TSI_CTCDIV_DIV128: fCTCLK = fHCLK/128
63 \arg TSI_CTCDIV_DIV256: fCTCLK = fHCLK/256
64 \arg TSI_CTCDIV_DIV512: fCTCLK = fHCLK/512
65 \arg TSI_CTCDIV_DIV1024: fCTCLK = fHCLK/1024
66 \arg TSI_CTCDIV_DIV2048: fCTCLK = fHCLK/2048
67 \arg TSI_CTCDIV_DIV4096: fCTCLK = fHCLK/4096
68 \arg TSI_CTCDIV_DIV8192: fCTCLK = fHCLK/8192
69 \arg TSI_CTCDIV_DIV16384: fCTCLK = fHCLK/16384
70 \arg TSI_CTCDIV_DIV32768: fCTCLK = fHCLK/32768
71 \param[in] charge_duration: charge state duration time
72 only one parameter can be selected which is shown as below:
73 \arg TSI_CHARGE_1CTCLK(x=1..16): the duration time of charge state is x CTCLK
74 \param[in] transfer_duration: charge transfer state duration time
75 only one parameter can be selected which is shown as below:
76 \arg TSI_TRANSFER_xCTCLK(x=1..16): the duration time of transfer state is x CTCLK
77 \param[in] max_number: max cycle number
78 only one parameter can be selected which is shown as below:
79 \arg TSI_MAXNUM255: the max cycle number of a sequence is 255
80 \arg TSI_MAXNUM511: the max cycle number of a sequence is 511
81 \arg TSI_MAXNUM1023: the max cycle number of a sequence is 1023
82 \arg TSI_MAXNUM2047: the max cycle number of a sequence is 2047
83 \arg TSI_MAXNUM4095: the max cycle number of a sequence is 4095
84 \arg TSI_MAXNUM8191: the max cycle number of a sequence is 8191
85 \arg TSI_MAXNUM16383: the max cycle number of a sequence is 16383
86 \param[out] none
87 \retval none
88 */
tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number)89 void tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number)
90 {
91 uint32_t ctl0,ctl1;
92 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
93 if(TSI_CTCDIV_DIV256 > prescaler){
94 /* config TSI_CTL0 */
95 ctl0 = TSI_CTL0;
96 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
97 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT|TSI_CTL0_MCN);
98 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration|max_number);
99 TSI_CTL0 = ctl0;
100
101 /* config TSI_CTL1 */
102 ctl1 = TSI_CTL1;
103 ctl1 &= ~TSI_CTL1_CTCDIV;
104 TSI_CTL1 = ctl1;
105 }else{
106 /* config TSI_CTL0 */
107 ctl0 = TSI_CTL0;
108 prescaler &= ~0x08U;
109 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
110 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT|TSI_CTL0_MCN);
111 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration|max_number);
112 TSI_CTL0 = ctl0;
113
114 /* config TSI_CTL1 */
115 ctl1 = TSI_CTL1;
116 ctl1 |= TSI_CTL1_CTCDIV;
117 TSI_CTL1 = ctl1;
118 }
119 }
120 }
121
122 /*!
123 \brief enable TSI module
124 \param[in] none
125 \param[out] none
126 \retval none
127 */
tsi_enable(void)128 void tsi_enable(void)
129 {
130 TSI_CTL0 |= TSI_CTL0_TSIEN;
131 }
132
133 /*!
134 \brief disable TSI module
135 \param[in] none
136 \param[out] none
137 \retval none
138 */
tsi_disable(void)139 void tsi_disable(void)
140 {
141 TSI_CTL0 &= ~TSI_CTL0_TSIEN;
142 }
143
144 /*!
145 \brief enable sample pin
146 \param[in] sample: sample pin
147 one or more parameters can be selected which are shown as below:
148 \arg TSI_SAMPCFG_GxPy( x=0..5,y=0..3):pin y of group x is sample pin
149 \param[out] none
150 \retval none
151 */
tsi_sample_pin_enable(uint32_t sample)152 void tsi_sample_pin_enable(uint32_t sample)
153 {
154 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
155 TSI_SAMPCFG |= sample;
156 }
157 }
158
159 /*!
160 \brief disable sample pin
161 \param[in] sample: sample pin
162 one or more parameters can be selected which are shown as below:
163 \arg TSI_SAMPCFG_GxPy( x=0..5,y=0..3): pin y of group x is sample pin
164 \param[out] none
165 \retval none
166 */
tsi_sample_pin_disable(uint32_t sample)167 void tsi_sample_pin_disable(uint32_t sample)
168 {
169 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
170 TSI_SAMPCFG &= ~sample;
171 }
172 }
173
174 /*!
175 \brief enable channel pin
176 \param[in] channel: channel pin
177 one or more parameters can be selected which are shown as below:
178 \arg TSI_CHCFG_GxPy( x=0..5,y=0..3): pin y of group x
179 \param[out] none
180 \retval none
181 */
tsi_channel_pin_enable(uint32_t channel)182 void tsi_channel_pin_enable(uint32_t channel)
183 {
184 TSI_CHCFG |= channel;
185 }
186
187 /*!
188 \brief disable channel pin
189 \param[in] channel: channel pin
190 one or more parameters can be selected which are shown as below:
191 \arg TSI_CHCFG_GxPy( x=0..5,y=0..3): pin y of group x
192 \param[out] none
193 \retval none
194 */
tsi_channel_pin_disable(uint32_t channel)195 void tsi_channel_pin_disable(uint32_t channel)
196 {
197 TSI_CHCFG &= ~channel;
198 }
199
200 /*!
201 \brief configure TSI triggering by software
202 \param[in] none
203 \param[out] none
204 \retval none
205 */
tsi_sofeware_mode_config(void)206 void tsi_sofeware_mode_config(void)
207 {
208 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
209 TSI_CTL0 &= ~TSI_CTL0_TRGMOD;
210 }
211 }
212
213 /*!
214 \brief start a charge-transfer sequence when TSI is in software trigger mode
215 \param[in] none
216 \param[out] none
217 \retval none
218 */
tsi_software_start(void)219 void tsi_software_start(void)
220 {
221 TSI_CTL0 |= TSI_CTL0_TSIS;
222 }
223
224 /*!
225 \brief stop a charge-transfer sequence when TSI is in software trigger mode
226 \param[in] none
227 \param[out] none
228 \retval none
229 */
tsi_software_stop(void)230 void tsi_software_stop(void)
231 {
232 TSI_CTL0 &= ~TSI_CTL0_TSIS;
233 }
234
235 /*!
236 \brief configure TSI triggering by hardware
237 \param[in] trigger_edge: the edge type in hardware trigger mode
238 only one parameter can be selected which is shown as below:
239 \arg TSI_FALLING_TRIGGER: falling edge trigger TSI charge transfer sequence
240 \arg TSI_RISING_TRIGGER: rising edge trigger TSI charge transfer sequence
241 \param[out] none
242 \retval none
243 */
tsi_hardware_mode_config(uint8_t trigger_edge)244 void tsi_hardware_mode_config(uint8_t trigger_edge)
245 {
246 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
247 /*enable hardware mode*/
248 TSI_CTL0 |= TSI_CTL0_TRGMOD;
249 /*configure the edge type in hardware trigger mode*/
250 if(TSI_FALLING_TRIGGER == trigger_edge){
251 TSI_CTL0 &= ~TSI_CTL0_EGSEL;
252 }else{
253 TSI_CTL0 |= TSI_CTL0_EGSEL;
254 }
255 }
256 }
257
258 /*!
259 \brief configure TSI pin mode when charge-transfer sequence is IDLE
260 \param[in] pin_mode: pin mode when charge-transfer sequence is IDLE
261 only one parameter can be selected which is shown as below:
262 \arg TSI_OUTPUT_LOW: TSI pin will output low when IDLE
263 \arg TSI_INPUT_FLOATING: TSI pin will keep input_floating when IDLE
264 \param[out] none
265 \retval none
266 */
tsi_pin_mode_config(uint8_t pin_mode)267 void tsi_pin_mode_config(uint8_t pin_mode)
268 {
269 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
270 if(TSI_OUTPUT_LOW == pin_mode){
271 TSI_CTL0 &= ~TSI_CTL0_PINMOD;
272 }else{
273 TSI_CTL0 |= TSI_CTL0_PINMOD;
274 }
275 }
276 }
277
278 /*!
279 \brief configure extend charge state
280 \param[in] extend: enable or disable extend charge state
281 only one parameter can be selected which is shown as below:
282 \arg ENABLE: enable extend charge state
283 \arg DISABLE: disable extend charge state
284 \param[in] prescaler: ECCLK clock division factor
285 only one parameter can be selected which is shown as below:
286 \arg TSI_EXTEND_DIV1: fECCLK = fHCLK
287 \arg TSI_EXTEND_DIV2: fECCLK = fHCLK/2
288 \arg TSI_EXTEND_DIV3: fECCLK = fHCLK/3
289 \arg TSI_EXTEND_DIV4: fECCLK = fHCLK/4
290 \arg TSI_EXTEND_DIV5: fECCLK = fHCLK/5
291 \arg TSI_EXTEND_DIV6: fECCLK = fHCLK/6
292 \arg TSI_EXTEND_DIV7: fECCLK = fHCLK/7
293 \arg TSI_EXTEND_DIV8: fECCLK = fHCLK/8
294 \param[in] max_duration: value range 1...128,extend charge state maximum duration time is 1*tECCLK~128*tECCLK
295 \param[out] none
296 \retval none
297 */
tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration)298 void tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration)
299 {
300 uint32_t ctl0,ctl1;
301 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
302 if(DISABLE == extend){
303 /*disable extend charge state*/
304 TSI_CTL0 &= ~TSI_CTL0_ECEN;
305 }else{
306 if(TSI_EXTEND_DIV3 > prescaler){
307 /*configure extend charge state maximum duration time*/
308 ctl0 = TSI_CTL0;
309 ctl0 &= ~TSI_CTL0_ECDT;
310 ctl0 |= TSI_EXTENDMAX((max_duration-1U));
311 TSI_CTL0 = ctl0;
312 /*configure ECCLK clock division factor*/
313 ctl0 = TSI_CTL0;
314 ctl0 &= ~TSI_CTL0_ECDIV;
315 ctl0 |= (uint32_t)prescaler<<15U;
316 TSI_CTL0 = ctl0;
317 /*enable extend charge state*/
318 TSI_CTL0 |= TSI_CTL0_ECEN;
319 }else{
320 /*configure extend charge state maximum duration time*/
321 ctl0 = TSI_CTL0;
322 ctl0 &= ~TSI_CTL0_ECDT;
323 ctl0 |= TSI_EXTENDMAX((max_duration-1U));
324 TSI_CTL0 = ctl0;
325 /*configure ECCLK clock division factor*/
326 ctl0 = TSI_CTL0;
327 ctl0 &= ~TSI_CTL0_ECDIV;
328 ctl0 |= (prescaler & 0x01U)<<15U;
329 TSI_CTL0 = ctl0;
330 ctl1 = TSI_CTL1;
331 ctl1 &= ~TSI_CTL1_ECDIV;
332 ctl1 |= (prescaler & 0x06U)<<28U;
333 TSI_CTL1 = ctl1;
334 /*enable extend charge state*/
335 TSI_CTL0 |= TSI_CTL0_ECEN;
336 }
337 }
338 }
339 }
340
341 /*!
342 \brief configure charge plus and transfer plus
343 \param[in] prescaler: CTCLK clock division factor
344 only one parameter can be selected which is shown as below:
345 \arg TSI_CTCDIV_DIV1: fCTCLK = fHCLK
346 \arg TSI_CTCDIV_DIV2: fCTCLK = fHCLK/2
347 \arg TSI_CTCDIV_DIV4: fCTCLK = fHCLK/4
348 \arg TSI_CTCDIV_DIV8: fCTCLK = fHCLK/8
349 \arg TSI_CTCDIV_DIV16: fCTCLK = fHCLK/16
350 \arg TSI_CTCDIV_DIV32: fCTCLK = fHCLK/32
351 \arg TSI_CTCDIV_DIV64: fCTCLK = fHCLK/64
352 \arg TSI_CTCDIV_DIV128: fCTCLK = fHCLK/128
353 \arg TSI_CTCDIV_DIV256: fCTCLK = fHCLK/256
354 \arg TSI_CTCDIV_DIV512: fCTCLK = fHCLK/512
355 \arg TSI_CTCDIV_DIV1024: fCTCLK = fHCLK/1024
356 \arg TSI_CTCDIV_DIV2048: fCTCLK = fHCLK/2048
357 \arg TSI_CTCDIV_DIV4096: fCTCLK = fHCLK/4096
358 \arg TSI_CTCDIV_DIV8192: fCTCLK = fHCLK/8192
359 \arg TSI_CTCDIV_DIV16384: fCTCLK = fHCLK/16384
360 \arg TSI_CTCDIV_DIV32768: fCTCLK = fHCLK/32768
361 \param[in] charge_duration: charge state duration time
362 only one parameter can be selected which is shown as below:
363 \arg TSI_CHARGE_xCTCLK(x=1..16): the duration time of charge state is x CTCLK
364 \param[in] transfer_duration: charge transfer state duration time
365 only one parameter can be selected which is shown as below:
366 \arg TSI_TRANSFER_xCTCLK(x=1..16): the duration time of transfer state is x CTCLK
367 \param[out] none
368 \retval none
369 */
tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration)370 void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration)
371 {
372 uint32_t ctl0,ctl1;
373 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
374 if(TSI_CTCDIV_DIV256 > prescaler){
375 /* config TSI_CTL0 */
376 ctl0 = TSI_CTL0;
377 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
378 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT);
379 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration);
380 TSI_CTL0 = ctl0;
381
382 /* config TSI_CTL1 */
383 ctl1 = TSI_CTL1;
384 ctl1 &= ~TSI_CTL1_CTCDIV;
385 TSI_CTL1 = ctl1;
386 }else{
387 /* config TSI_CTL */
388 ctl0 = TSI_CTL0;
389 prescaler &= ~0x08U;
390 /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */
391 ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT);
392 ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration);
393 TSI_CTL0 = ctl0;
394
395 /* config TSI_CTL2 */
396 ctl1 = TSI_CTL1;
397 ctl1 |= TSI_CTL1_CTCDIV;
398 TSI_CTL1 = ctl1;
399 }
400 }
401 }
402
403 /*!
404 \brief configure the max cycle number of a charge-transfer sequence
405 \param[in] max_number: max cycle number
406 only one parameter can be selected which is shown as below:
407 \arg TSI_MAXNUM255: the max cycle number of a sequence is 255
408 \arg TSI_MAXNUM511: the max cycle number of a sequence is 511
409 \arg TSI_MAXNUM1023: the max cycle number of a sequence is 1023
410 \arg TSI_MAXNUM2047: the max cycle number of a sequence is 2047
411 \arg TSI_MAXNUM4095: the max cycle number of a sequence is 4095
412 \arg TSI_MAXNUM8191: the max cycle number of a sequence is 8191
413 \arg TSI_MAXNUM16383: the max cycle number of a sequence is 16383
414 \param[out] none
415 \retval none
416 */
tsi_max_number_config(uint32_t max_number)417 void tsi_max_number_config(uint32_t max_number)
418 {
419 if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){
420 uint32_t maxnum;
421 maxnum = TSI_CTL0;
422 /*configure the max cycle number of a charge-transfer sequence*/
423 maxnum &= ~TSI_CTL0_MCN;
424 maxnum |= max_number;
425 TSI_CTL0 = maxnum;
426 }
427 }
428
429 /*!
430 \brief switch on hysteresis pin
431 \param[in] group_pin: select pin which will be switched on hysteresis
432 one or more parameters can be selected which are shown as below:
433 \arg TSI_PHM_GxPy(x=0..5,y=0..3): pin y of group x switch on hysteresis
434 \param[out] none
435 \retval none
436 */
tsi_hysteresis_on(uint32_t group_pin)437 void tsi_hysteresis_on(uint32_t group_pin)
438 {
439 TSI_PHM |= group_pin;
440 }
441
442 /*!
443 \brief switch off hysteresis pin
444 \param[in] group_pin: select pin which will be switched off hysteresis
445 one or more parameters can be selected which are shown as below:
446 \arg TSI_PHM_GxPy(x=0..5,y=0..3): pin y of group x switch off hysteresis
447 \param[out] none
448 \retval none
449 */
tsi_hysteresis_off(uint32_t group_pin)450 void tsi_hysteresis_off(uint32_t group_pin)
451 {
452 TSI_PHM &= ~group_pin;
453 }
454
455 /*!
456 \brief switch on analog pin
457 \param[in] group_pin: select pin which will be switched on analog
458 one or more parameters can be selected which are shown as below:
459 \arg TSI_ASW_GxPy(x=0..5,y=0..3):pin y of group x switch on analog
460 \param[out] none
461 \retval none
462 */
tsi_analog_on(uint32_t group_pin)463 void tsi_analog_on(uint32_t group_pin)
464 {
465 TSI_ASW |= group_pin;
466 }
467
468 /*!
469 \brief switch off analog pin
470 \param[in] group_pin: select pin which will be switched off analog
471 one or more parameters can be selected which are shown as below:
472 \arg TSI_ASW_GxPy(x=0..5,y=0..3):pin y of group x switch off analog
473 \param[out] none
474 \retval none
475 */
tsi_analog_off(uint32_t group_pin)476 void tsi_analog_off(uint32_t group_pin)
477 {
478 TSI_ASW &= ~group_pin;
479 }
480
481 /*!
482 \brief enable TSI interrupt
483 \param[in] source: select interrupt which will be enabled
484 only one parameter can be selected which is shown as below:
485 \arg TSI_INT_CCTCF: charge-transfer complete flag interrupt enable
486 \arg TSI_INT_MNERR: max cycle number error interrupt enable
487 \param[out] none
488 \retval none
489 */
tsi_interrupt_enable(uint32_t source)490 void tsi_interrupt_enable(uint32_t source)
491 {
492 TSI_INTEN |= source;
493 }
494
495 /*!
496 \brief disable TSI interrupt
497 \param[in] source: select interrupt which will be disabled
498 only one parameter can be selected which is shown as below:
499 \arg TSI_INT_CCTCF: charge-transfer complete flag interrupt disable
500 \arg TSI_INT_MNERR: max cycle number error interrupt disable
501 \param[out] none
502 \retval none
503 */
tsi_interrupt_disable(uint32_t source)504 void tsi_interrupt_disable(uint32_t source)
505 {
506 TSI_INTEN &= ~source;
507 }
508
509 /*!
510 \brief clear TSI interrupt flag
511 \param[in] flag: select flag which will be cleared
512 only one parameter can be selected which is shown as below:
513 \arg TSI_INT_FLAG_CTCF: clear charge-transfer complete flag
514 \arg TSI_INT_FLAG_MNERR: clear max cycle number error
515 \param[out] none
516 \retval none
517 */
tsi_interrupt_flag_clear(uint32_t flag)518 void tsi_interrupt_flag_clear(uint32_t flag)
519 {
520 TSI_INTC |= flag;
521 }
522
523 /*!
524 \brief get TSI interrupt flag
525 \param[in] flag:
526 only one parameter can be selected which is shown as below:
527 \arg TSI_INT_FLAG_CTCF: charge-transfer complete flag
528 \arg TSI_INT_FLAG_MNERR: max Cycle Number Error
529 \param[out] none
530 \retval FlagStatus:SET or RESET
531 */
tsi_interrupt_flag_get(uint32_t flag)532 FlagStatus tsi_interrupt_flag_get(uint32_t flag)
533 {
534 uint32_t interrupt_enable = 0U,interrupt_flag = 0U;
535 interrupt_flag = (TSI_INTF & flag);
536 interrupt_enable = (TSI_INTEN & flag);
537 if(interrupt_flag && interrupt_enable){
538 return SET;
539 }else{
540 return RESET;
541 }
542 }
543
544 /*!
545 \brief clear flag
546 \param[in] flag: select flag which will be cleared
547 only one parameter can be selected which is shown as below:
548 \arg TSI_FLAG_CTCF: clear charge-transfer complete flag
549 \arg TSI_FLAG_MNERR: clear max cycle number error
550 \param[out] none
551 \retval none
552 */
tsi_flag_clear(uint32_t flag)553 void tsi_flag_clear(uint32_t flag)
554 {
555 TSI_INTC |= flag;
556 }
557
558 /*!
559 \brief get flag
560 \param[in] flag:
561 only one parameter can be selected which is shown as below:
562 \arg TSI_FLAG_CTCF: charge-transfer complete flag
563 \arg TSI_FLAG_MNERR: max Cycle Number Error
564 \param[out] none
565 \retval FlagStatus:SET or RESET
566 */
tsi_flag_get(uint32_t flag)567 FlagStatus tsi_flag_get(uint32_t flag)
568 {
569 FlagStatus flag_status;
570 if(TSI_INTF & flag){
571 flag_status = SET;
572 }else{
573 flag_status = RESET;
574 }
575 return flag_status;
576 }
577
578 /*!
579 \brief enbale group
580 \param[in] group: select group to be enabled
581 one or more parameters can be selected which are shown as below:
582 \arg TSI_GCTL_GEx(x=0..5): the x group will be enabled
583 \param[out] none
584 \retval none
585 */
tsi_group_enable(uint32_t group)586 void tsi_group_enable(uint32_t group)
587 {
588 TSI_GCTL |= group;
589 }
590
591 /*!
592 \brief disbale group
593 \param[in] group: select group to be disabled
594 one or more parameters can be selected which are shown as below:
595 \arg TSI_GCTL_GEx(x=0..5):the x group will be disabled
596 \param[out] none
597 \retval none
598 */
tsi_group_disable(uint32_t group)599 void tsi_group_disable(uint32_t group)
600 {
601 TSI_GCTL &= ~group;
602 }
603
604 /*!
605 \brief get group complete status
606 \param[in] group: select group
607 only one parameter can be selected which is shown as below:
608 \arg TSI_GCTL_GCx(x=0..5): get the complete status of group x
609 \param[out] none
610 \retval FlagStatus: group complete status,SET or RESET
611 */
tsi_group_status_get(uint32_t group)612 FlagStatus tsi_group_status_get(uint32_t group)
613 {
614 FlagStatus flag_status;
615 if(TSI_GCTL & group){
616 flag_status = SET;
617 }else{
618 flag_status = RESET;
619 }
620 return flag_status;
621 }
622
623 /*!
624 \brief get the cycle number for group0 as soon as a charge-transfer sequence completes
625 \param[in] none
626 \param[out] none
627 \retval group0 cycle number
628 */
tsi_group0_cycle_get(void)629 uint16_t tsi_group0_cycle_get(void)
630 {
631 return (uint16_t)TSI_G0CYCN;
632 }
633
634 /*!
635 \brief get the cycle number for group1 as soon as a charge-transfer sequence completes
636 \param[in] none
637 \param[out] none
638 \retval group1 cycle number
639 */
tsi_group1_cycle_get(void)640 uint16_t tsi_group1_cycle_get(void)
641 {
642 return (uint16_t)TSI_G1CYCN;
643 }
644
645 /*!
646 \brief get the cycle number for group2 as soon as a charge-transfer sequence completes
647 \param[in] none
648 \param[out] none
649 \retval group2 cycle number
650 */
tsi_group2_cycle_get(void)651 uint16_t tsi_group2_cycle_get(void)
652 {
653 return (uint16_t)TSI_G2CYCN;
654 }
655
656 /*!
657 \brief get the cycle number for group3 as soon as a charge-transfer sequence completes
658 \param[in] none
659 \param[out] none
660 \retval group3 cycle number
661 */
tsi_group3_cycle_get(void)662 uint16_t tsi_group3_cycle_get(void)
663 {
664 return (uint16_t)TSI_G3CYCN;
665 }
666
667 /*!
668 \brief get the cycle number for group4 as soon as a charge-transfer sequence completes
669 \param[in] none
670 \param[out] none
671 \retval group4 cycle number
672 */
tsi_group4_cycle_get(void)673 uint16_t tsi_group4_cycle_get(void)
674 {
675 return (uint16_t)TSI_G4CYCN;
676 }
677
678 /*!
679 \brief get the cycle number for group5 as soon as a charge-transfer sequence completes
680 \param[in] none
681 \param[out] none
682 \retval group5 cycle number
683 */
tsi_group5_cycle_get(void)684 uint16_t tsi_group5_cycle_get(void)
685 {
686 return (uint16_t)TSI_G5CYCN;
687 }
688
