1 // Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_SENS_STRUCT_H_ 15 #define _SOC_SENS_STRUCT_H_ 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 typedef volatile struct { 21 union { 22 struct { 23 uint32_t sar1_clk_div: 8; /*clock divider*/ 24 uint32_t reserved8: 10; 25 uint32_t sar1_clk_gated: 1; 26 uint32_t sar1_sample_num: 8; 27 uint32_t reserved27: 1; 28 uint32_t sar1_data_inv: 1; /*Invert SAR ADC1 data*/ 29 uint32_t sar1_int_en: 1; /*enable saradc1 to send out interrupt*/ 30 uint32_t reserved30: 2; 31 }; 32 uint32_t val; 33 } sar_reader1_ctrl; 34 uint32_t sar_reader1_status; /**/ 35 union { 36 struct { 37 uint32_t reserved0: 22; 38 uint32_t rtc_saradc_reset: 1; 39 uint32_t rtc_saradc_clkgate_en: 1; 40 uint32_t force_xpd_amp: 2; 41 uint32_t amp_rst_fb_force: 2; 42 uint32_t amp_short_ref_force: 2; 43 uint32_t amp_short_ref_gnd_force: 2; 44 }; 45 uint32_t val; 46 } sar_meas1_ctrl1; 47 union { 48 struct { 49 uint32_t meas1_data_sar: 16; /*SAR ADC1 data*/ 50 uint32_t meas1_done_sar: 1; /*SAR ADC1 conversion done indication*/ 51 uint32_t meas1_start_sar: 1; /*SAR ADC1 controller (in RTC) starts conversion*/ 52 uint32_t meas1_start_force: 1; /*1: SAR ADC1 controller (in RTC) is started by SW*/ 53 uint32_t sar1_en_pad: 12; /*SAR ADC1 pad enable bitmap*/ 54 uint32_t sar1_en_pad_force: 1; /*1: SAR ADC1 pad enable bitmap is controlled by SW*/ 55 }; 56 uint32_t val; 57 } sar_meas1_ctrl2; 58 union { 59 struct { 60 uint32_t reserved0: 31; 61 uint32_t sar1_dig_force: 1; /*1: SAR ADC1 controlled by DIG ADC1 CTRL*/ 62 }; 63 uint32_t val; 64 } sar_meas1_mux; 65 uint32_t sar_atten1; /*2-bit attenuation for each pad*/ 66 union { 67 struct { 68 uint32_t sar_amp_wait1:16; 69 uint32_t sar_amp_wait2:16; 70 }; 71 uint32_t val; 72 } sar_amp_ctrl1; 73 union { 74 struct { 75 uint32_t sar1_dac_xpd_fsm_idle: 1; 76 uint32_t xpd_sar_amp_fsm_idle: 1; 77 uint32_t amp_rst_fb_fsm_idle: 1; 78 uint32_t amp_short_ref_fsm_idle: 1; 79 uint32_t amp_short_ref_gnd_fsm_idle: 1; 80 uint32_t xpd_sar_fsm_idle: 1; 81 uint32_t sar_rstb_fsm_idle: 1; 82 uint32_t reserved7: 9; 83 uint32_t sar_amp_wait3: 16; 84 }; 85 uint32_t val; 86 } sar_amp_ctrl2; 87 union { 88 struct { 89 uint32_t sar1_dac_xpd_fsm: 4; 90 uint32_t xpd_sar_amp_fsm: 4; 91 uint32_t amp_rst_fb_fsm: 4; 92 uint32_t amp_short_ref_fsm: 4; 93 uint32_t amp_short_ref_gnd_fsm: 4; 94 uint32_t xpd_sar_fsm: 4; 95 uint32_t sar_rstb_fsm: 4; 96 uint32_t reserved28: 4; 97 }; 98 uint32_t val; 99 } sar_amp_ctrl3; 100 union { 101 struct { 102 uint32_t sar2_clk_div: 8; /*clock divider*/ 103 uint32_t reserved8: 8; 104 uint32_t sar2_wait_arb_cycle: 2; /*wait arbit stable after sar_done*/ 105 uint32_t sar2_clk_gated: 1; 106 uint32_t sar2_sample_num: 8; 107 uint32_t reserved27: 2; 108 uint32_t sar2_data_inv: 1; /*Invert SAR ADC2 data*/ 109 uint32_t sar2_int_en: 1; /*enable saradc2 to send out interrupt*/ 110 uint32_t reserved31: 1; 111 }; 112 uint32_t val; 113 } sar_reader2_ctrl; 114 uint32_t sar_reader2_status; /**/ 115 union { 116 struct { 117 uint32_t sar2_cntl_state: 3; /*saradc2_cntl_fsm*/ 118 uint32_t sar2_pwdet_cal_en: 1; /*rtc control pwdet enable*/ 119 uint32_t sar2_pkdet_cal_en: 1; /*rtc control pkdet enable*/ 120 uint32_t sar2_en_test: 1; /*SAR2_EN_TEST*/ 121 uint32_t sar2_rstb_force: 2; 122 uint32_t sar2_standby_wait: 8; 123 uint32_t sar2_rstb_wait: 8; 124 uint32_t sar2_xpd_wait: 8; 125 }; 126 uint32_t val; 127 } sar_meas2_ctrl1; 128 union { 129 struct { 130 uint32_t meas2_data_sar: 16; /*SAR ADC2 data*/ 131 uint32_t meas2_done_sar: 1; /*SAR ADC2 conversion done indication*/ 132 uint32_t meas2_start_sar: 1; /*SAR ADC2 controller (in RTC) starts conversion*/ 133 uint32_t meas2_start_force: 1; /*1: SAR ADC2 controller (in RTC) is started by SW*/ 134 uint32_t sar2_en_pad: 12; /*SAR ADC2 pad enable bitmap*/ 135 uint32_t sar2_en_pad_force: 1; /*1: SAR ADC2 pad enable bitmap is controlled by SW*/ 136 }; 137 uint32_t val; 138 } sar_meas2_ctrl2; 139 union { 140 struct { 141 uint32_t reserved0: 28; 142 uint32_t sar2_pwdet_cct: 3; /*SAR2_PWDET_CCT*/ 143 uint32_t sar2_rtc_force: 1; /*in sleep force to use rtc to control ADC*/ 144 }; 145 uint32_t val; 146 } sar_meas2_mux; 147 uint32_t sar_atten2; /*2-bit attenuation for each pad*/ 148 union { 149 struct { 150 uint32_t reserved0: 29; 151 uint32_t force_xpd_sar: 2; 152 uint32_t sarclk_en: 1; 153 }; 154 uint32_t val; 155 } sar_power_xpd_sar; 156 union { 157 struct { 158 uint32_t i2c_slave_addr1: 11; 159 uint32_t i2c_slave_addr0: 11; 160 uint32_t meas_status: 8; 161 uint32_t reserved30: 2; 162 }; 163 uint32_t val; 164 } sar_slave_addr1; 165 union { 166 struct { 167 uint32_t i2c_slave_addr3:11; 168 uint32_t i2c_slave_addr2:11; 169 uint32_t reserved22: 10; 170 }; 171 uint32_t val; 172 } sar_slave_addr2; 173 union { 174 struct { 175 uint32_t i2c_slave_addr5:11; 176 uint32_t i2c_slave_addr4:11; 177 uint32_t reserved22: 10; 178 }; 179 uint32_t val; 180 } sar_slave_addr3; 181 union { 182 struct { 183 uint32_t i2c_slave_addr7:11; 184 uint32_t i2c_slave_addr6:11; 185 uint32_t reserved22: 10; 186 }; 187 uint32_t val; 188 } sar_slave_addr4; 189 union { 190 struct { 191 uint32_t tsens_out: 8; /*temperature sensor data out*/ 192 uint32_t tsens_ready: 1; /*indicate temperature sensor out ready*/ 193 uint32_t reserved9: 3; 194 uint32_t tsens_int_en: 1; /*enable temperature sensor to send out interrupt*/ 195 uint32_t tsens_in_inv: 1; /*invert temperature sensor data*/ 196 uint32_t tsens_clk_div: 8; /*temperature sensor clock divider*/ 197 uint32_t tsens_power_up: 1; /*temperature sensor power up*/ 198 uint32_t tsens_power_up_force: 1; /*1: dump out & power up controlled by SW*/ 199 uint32_t tsens_dump_out: 1; /*temperature sensor dump out*/ 200 uint32_t reserved25: 7; 201 }; 202 uint32_t val; 203 } sar_tctrl; 204 union { 205 struct { 206 uint32_t tsens_xpd_wait: 12; 207 uint32_t tsens_xpd_force: 2; 208 uint32_t tsens_clk_inv: 1; 209 uint32_t tsens_clkgate_en: 1; /*temperature sensor clock enable*/ 210 uint32_t tsens_reset: 1; /*temperature sensor reset*/ 211 uint32_t reserved17: 15; 212 }; 213 uint32_t val; 214 } sar_tctrl2; 215 union { 216 struct { 217 uint32_t sar_i2c_ctrl: 28; /*I2C control data*/ 218 uint32_t sar_i2c_start: 1; /*start I2C*/ 219 uint32_t sar_i2c_start_force: 1; /*1: I2C started by SW*/ 220 uint32_t reserved30: 2; 221 }; 222 uint32_t val; 223 } sar_i2c_ctrl; 224 union { 225 struct { 226 uint32_t touch_outen: 15; /*touch controller output enable*/ 227 uint32_t touch_status_clr: 1; /*clear all touch active status*/ 228 uint32_t touch_data_sel: 2; /*3: smooth data 2: benchmark 1 0: raw_data*/ 229 uint32_t touch_denoise_end: 1; /*touch_denoise_done*/ 230 uint32_t touch_unit_end: 1; /*touch_unit_done*/ 231 uint32_t touch_approach_pad2: 4; /*indicate which pad is approach pad2*/ 232 uint32_t touch_approach_pad1: 4; /*indicate which pad is approach pad1*/ 233 uint32_t touch_approach_pad0: 4; /*indicate which pad is approach pad0*/ 234 }; 235 uint32_t val; 236 } sar_touch_conf; 237 union { 238 struct { 239 uint32_t thresh: 22; /*Finger threshold for touch pad 1*/ 240 uint32_t reserved22: 10; 241 }; 242 uint32_t val; 243 } touch_thresh[14]; 244 uint32_t reserved_98; 245 uint32_t reserved_9c; 246 uint32_t reserved_a0; 247 uint32_t reserved_a4; 248 uint32_t reserved_a8; 249 uint32_t reserved_ac; 250 uint32_t reserved_b0; 251 uint32_t reserved_b4; 252 uint32_t reserved_b8; 253 uint32_t reserved_bc; 254 uint32_t reserved_c0; 255 uint32_t reserved_c4; 256 uint32_t reserved_c8; 257 uint32_t reserved_cc; 258 uint32_t reserved_d0; 259 union { 260 struct { 261 uint32_t touch_pad_active: 15; /*touch active status*/ 262 uint32_t touch_channel_clr:15; /*Clear touch channel*/ 263 uint32_t reserved30: 1; 264 uint32_t touch_meas_done: 1; 265 }; 266 uint32_t val; 267 } sar_touch_chn_st; 268 union { 269 struct { 270 uint32_t touch_denoise_data:22; /*the counter for touch pad 0*/ 271 uint32_t touch_scan_curr: 4; 272 uint32_t reserved26: 6; 273 }; 274 uint32_t val; 275 } sar_touch_status0; 276 union { 277 struct { 278 uint32_t touch_pad_data: 22; 279 uint32_t reserved22: 7; 280 uint32_t touch_pad_debounce: 3; 281 }; 282 uint32_t val; 283 } sar_touch_status[14]; 284 union { 285 struct { 286 uint32_t touch_slp_data: 22; 287 uint32_t reserved22: 7; 288 uint32_t touch_slp_debounce: 3; 289 }; 290 uint32_t val; 291 } sar_touch_slp_status; 292 union { 293 struct { 294 uint32_t touch_approach_pad2_cnt: 8; 295 uint32_t touch_approach_pad1_cnt: 8; 296 uint32_t touch_approach_pad0_cnt: 8; 297 uint32_t touch_slp_approach_cnt: 8; 298 }; 299 uint32_t val; 300 } sar_touch_appr_status; 301 union { 302 struct { 303 uint32_t sw_fstep: 16; /*frequency step for CW generator*/ 304 uint32_t sw_tone_en: 1; /*1: enable CW generator*/ 305 uint32_t debug_bit_sel: 5; 306 uint32_t dac_dig_force: 1; /*1: DAC1 & DAC2 use DMA*/ 307 uint32_t dac_clk_force_low: 1; /*1: force PDAC_CLK to low*/ 308 uint32_t dac_clk_force_high: 1; /*1: force PDAC_CLK to high*/ 309 uint32_t dac_clk_inv: 1; /*1: invert PDAC_CLK*/ 310 uint32_t dac_reset: 1; 311 uint32_t dac_clkgate_en: 1; 312 uint32_t reserved28: 4; 313 }; 314 uint32_t val; 315 } sar_dac_ctrl1; 316 union { 317 struct { 318 uint32_t dac_dc1: 8; /*DC offset for DAC1 CW generator*/ 319 uint32_t dac_dc2: 8; /*DC offset for DAC2 CW generator*/ 320 uint32_t dac_scale1: 2; /*00: no scale*/ 321 uint32_t dac_scale2: 2; /*00: no scale*/ 322 uint32_t dac_inv1: 2; /*00: do not invert any bits*/ 323 uint32_t dac_inv2: 2; /*00: do not invert any bits*/ 324 uint32_t dac_cw_en1: 1; /*1: to select CW generator as source to PDAC1_DAC[7:0]*/ 325 uint32_t dac_cw_en2: 1; /*1: to select CW generator as source to PDAC2_DAC[7:0]*/ 326 uint32_t reserved26: 6; 327 }; 328 uint32_t val; 329 } sar_dac_ctrl2; 330 union { 331 struct { 332 uint32_t reserved0: 25; 333 uint32_t dbg_trigger: 1; /*trigger cocpu debug registers*/ 334 uint32_t clk_en: 1; /*check cocpu whether clk on*/ 335 uint32_t reset_n: 1; /*check cocpu whether in reset state*/ 336 uint32_t eoi: 1; /*check cocpu whether in interrupt state*/ 337 uint32_t trap: 1; /*check cocpu whether in trap state*/ 338 uint32_t ebreak: 1; /*check cocpu whether in ebreak*/ 339 uint32_t reserved31: 1; 340 }; 341 uint32_t val; 342 } sar_cocpu_state; 343 union { 344 struct { 345 uint32_t touch_done: 1; /*int from touch done*/ 346 uint32_t touch_inactive: 1; /*int from touch inactive*/ 347 uint32_t touch_active: 1; /*int from touch active*/ 348 uint32_t saradc1: 1; /*int from saradc1*/ 349 uint32_t saradc2: 1; /*int from saradc2*/ 350 uint32_t tsens: 1; /*int from tsens*/ 351 uint32_t start: 1; /*int from start*/ 352 uint32_t sw: 1; /*int from software*/ 353 uint32_t swd: 1; /*int from super watch dog*/ 354 uint32_t reserved9: 23; 355 }; 356 uint32_t val; 357 } sar_cocpu_int_raw; 358 union { 359 struct { 360 uint32_t touch_done: 1; 361 uint32_t touch_inactive: 1; 362 uint32_t touch_active: 1; 363 uint32_t saradc1: 1; 364 uint32_t saradc2: 1; 365 uint32_t tsens: 1; 366 uint32_t start: 1; 367 uint32_t sw: 1; /*cocpu int enable*/ 368 uint32_t swd: 1; 369 uint32_t reserved9: 23; 370 }; 371 uint32_t val; 372 } sar_cocpu_int_ena; 373 union { 374 struct { 375 uint32_t touch_done: 1; 376 uint32_t touch_inactive: 1; 377 uint32_t touch_active: 1; 378 uint32_t saradc1: 1; 379 uint32_t saradc2: 1; 380 uint32_t tsens: 1; 381 uint32_t start: 1; 382 uint32_t sw: 1; /*cocpu int status*/ 383 uint32_t swd: 1; 384 uint32_t reserved9: 23; 385 }; 386 uint32_t val; 387 } sar_cocpu_int_st; 388 union { 389 struct { 390 uint32_t touch_done: 1; 391 uint32_t touch_inactive: 1; 392 uint32_t touch_active: 1; 393 uint32_t saradc1: 1; 394 uint32_t saradc2: 1; 395 uint32_t tsens: 1; 396 uint32_t start: 1; 397 uint32_t sw: 1; /*cocpu int clear*/ 398 uint32_t swd: 1; 399 uint32_t reserved9: 23; 400 }; 401 uint32_t val; 402 } sar_cocpu_int_clr; 403 union { 404 struct { 405 uint32_t pc: 13; /*cocpu Program counter*/ 406 uint32_t mem_vld: 1; /*cocpu mem valid output*/ 407 uint32_t mem_rdy: 1; /*cocpu mem ready input*/ 408 uint32_t mem_wen: 4; /*cocpu mem write enable output*/ 409 uint32_t mem_addr: 13; /*cocpu mem address output*/ 410 }; 411 uint32_t val; 412 } sar_cocpu_debug; 413 union { 414 struct { 415 uint32_t reserved0: 28; 416 uint32_t xpd_hall: 1; /*Power on hall sensor and connect to VP and VN*/ 417 uint32_t xpd_hall_force: 1; /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/ 418 uint32_t hall_phase: 1; /*Reverse phase of hall sensor*/ 419 uint32_t hall_phase_force: 1; /*1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor*/ 420 }; 421 uint32_t val; 422 } sar_hall_ctrl; 423 uint32_t sar_nouse; /**/ 424 union { 425 struct { 426 uint32_t reserved0: 30; 427 uint32_t iomux_reset: 1; 428 uint32_t iomux_clk_gate_en: 1; 429 }; 430 uint32_t val; 431 } sar_io_mux_conf; 432 union { 433 struct { 434 uint32_t sar_date: 28; 435 uint32_t reserved28: 4; 436 }; 437 uint32_t val; 438 } sardate; 439 } sens_dev_t; 440 extern sens_dev_t SENS; 441 #ifdef __cplusplus 442 } 443 #endif 444 445 #endif /* _SOC_SENS_STRUCT_H_ */ 446
