1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_TRNG_H 9 #define _HARDWARE_STRUCTS_TRNG_H 10 11 /** 12 * \file rp2350/trng.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/trng.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_trng 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/trng.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 _REG_(TRNG_RNG_IMR_OFFSET) // TRNG_RNG_IMR 28 // Interrupt masking 29 // 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED 30 // 0x00000008 [3] VN_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated 31 // 0x00000004 [2] CRNGT_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated 32 // 0x00000002 [1] AUTOCORR_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated 33 // 0x00000001 [0] EHR_VALID_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated 34 io_rw_32 rng_imr; 35 36 _REG_(TRNG_RNG_ISR_OFFSET) // TRNG_RNG_ISR 37 // RNG status register 38 // 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED 39 // 0x00000008 [3] VN_ERR (0) 1'b1 indicates Von Neuman error 40 // 0x00000004 [2] CRNGT_ERR (0) 1'b1 indicates CRNGT in the RNG test failed 41 // 0x00000002 [1] AUTOCORR_ERR (0) 1'b1 indicates Autocorrelation test failed four times in a row 42 // 0x00000001 [0] EHR_VALID (0) 1'b1 indicates that 192 bits have been collected in the... 43 io_ro_32 rng_isr; 44 45 _REG_(TRNG_RNG_ICR_OFFSET) // TRNG_RNG_ICR 46 // Interrupt/status bit clear Register 47 // 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED 48 // 0x00000008 [3] VN_ERR (0) Write 1'b1 - clear corresponding bit in RNG_ISR 49 // 0x00000004 [2] CRNGT_ERR (0) Write 1'b1 - clear corresponding bit in RNG_ISR 50 // 0x00000002 [1] AUTOCORR_ERR (0) Cannot be cleared by SW! Only RNG reset clears this bit 51 // 0x00000001 [0] EHR_VALID (0) Write 1'b1 - clear corresponding bit in RNG_ISR 52 io_rw_32 rng_icr; 53 54 _REG_(TRNG_TRNG_CONFIG_OFFSET) // TRNG_TRNG_CONFIG 55 // Selecting the inverter-chain length 56 // 0xfffffffc [31:2] RESERVED (0x00000000) RESERVED 57 // 0x00000003 [1:0] RND_SRC_SEL (0x0) Selects the number of inverters (out of four possible... 58 io_rw_32 trng_config; 59 60 _REG_(TRNG_TRNG_VALID_OFFSET) // TRNG_TRNG_VALID 61 // 192 bit collection indication 62 // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED 63 // 0x00000001 [0] EHR_VALID (0) 1'b1 indicates that collection of bits in the RNG is... 64 io_ro_32 trng_valid; 65 66 // (Description copied from array index 0 register TRNG_EHR_DATA0 applies similarly to other array indexes) 67 _REG_(TRNG_EHR_DATA0_OFFSET) // TRNG_EHR_DATA0 68 // RNG collected bits 69 // 0xffffffff [31:0] EHR_DATA0 (0x00000000) Bits [31:0] of Entropy Holding Register (EHR) - RNG... 70 io_ro_32 ehr_data[6]; 71 72 _REG_(TRNG_RND_SOURCE_ENABLE_OFFSET) // TRNG_RND_SOURCE_ENABLE 73 // Enable signal for the random source 74 // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED 75 // 0x00000001 [0] RND_SRC_EN (0) * 1'b1 - entropy source is enabled 76 io_rw_32 rnd_source_enable; 77 78 _REG_(TRNG_SAMPLE_CNT1_OFFSET) // TRNG_SAMPLE_CNT1 79 // Counts clocks between sampling of random bit 80 // 0xffffffff [31:0] SAMPLE_CNTR1 (0x0000ffff) Sets the number of rng_clk cycles between two... 81 io_rw_32 sample_cnt1; 82 83 _REG_(TRNG_AUTOCORR_STATISTIC_OFFSET) // TRNG_AUTOCORR_STATISTIC 84 // Statistic about Autocorrelation test activations 85 // 0xffc00000 [31:22] RESERVED (0x000) RESERVED 86 // 0x003fc000 [21:14] AUTOCORR_FAILS (0x00) Count each time an autocorrelation test fails 87 // 0x00003fff [13:0] AUTOCORR_TRYS (0x0000) Count each time an autocorrelation test starts 88 io_rw_32 autocorr_statistic; 89 90 _REG_(TRNG_TRNG_DEBUG_CONTROL_OFFSET) // TRNG_TRNG_DEBUG_CONTROL 91 // Debug register 92 // 0x00000008 [3] AUTO_CORRELATE_BYPASS (0) When set, the autocorrelation test in the TRNG module is bypassed 93 // 0x00000004 [2] TRNG_CRNGT_BYPASS (0) When set, the CRNGT test in the RNG is bypassed 94 // 0x00000002 [1] VNC_BYPASS (0) When set, the Von-Neuman balancer is bypassed (including... 95 // 0x00000001 [0] RESERVED (0) N/A 96 io_rw_32 trng_debug_control; 97 98 uint32_t _pad0; 99 100 _REG_(TRNG_TRNG_SW_RESET_OFFSET) // TRNG_TRNG_SW_RESET 101 // Generate internal SW reset within the RNG block 102 // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED 103 // 0x00000001 [0] TRNG_SW_RESET (0) Writing 1'b1 to this register causes an internal RNG reset 104 io_rw_32 trng_sw_reset; 105 106 uint32_t _pad1[28]; 107 108 _REG_(TRNG_RNG_DEBUG_EN_INPUT_OFFSET) // TRNG_RNG_DEBUG_EN_INPUT 109 // Enable the RNG debug mode 110 // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED 111 // 0x00000001 [0] RNG_DEBUG_EN (0) * 1'b1 - debug mode is enabled 112 io_rw_32 rng_debug_en_input; 113 114 _REG_(TRNG_TRNG_BUSY_OFFSET) // TRNG_TRNG_BUSY 115 // RNG Busy indication 116 // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED 117 // 0x00000001 [0] TRNG_BUSY (0) Reflects rng_busy status 118 io_ro_32 trng_busy; 119 120 _REG_(TRNG_RST_BITS_COUNTER_OFFSET) // TRNG_RST_BITS_COUNTER 121 // Reset the counter of collected bits in the RNG 122 // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED 123 // 0x00000001 [0] RST_BITS_COUNTER (0) Writing any value to this address will reset the bits... 124 io_rw_32 rst_bits_counter; 125 126 _REG_(TRNG_RNG_VERSION_OFFSET) // TRNG_RNG_VERSION 127 // Displays the version settings of the TRNG 128 // 0xffffff00 [31:8] RESERVED (0x000000) RESERVED 129 // 0x00000080 [7] RNG_USE_5_SBOXES (0) * 1'b1 - 5 SBOX AES 130 // 0x00000040 [6] RESEEDING_EXISTS (0) * 1'b1 - Exists 131 // 0x00000020 [5] KAT_EXISTS (0) * 1'b1 - Exists 132 // 0x00000010 [4] PRNG_EXISTS (0) * 1'b1 - Exists 133 // 0x00000008 [3] TRNG_TESTS_BYPASS_EN (0) * 1'b1 - Exists 134 // 0x00000004 [2] AUTOCORR_EXISTS (0) * 1'b1 - Exists 135 // 0x00000002 [1] CRNGT_EXISTS (0) * 1'b1 - Exists 136 // 0x00000001 [0] EHR_WIDTH_192 (0) * 1'b1 - 192-bit EHR 137 io_ro_32 rng_version; 138 139 uint32_t _pad2[7]; 140 141 // (Description copied from array index 0 register TRNG_RNG_BIST_CNTR_0 applies similarly to other array indexes) 142 _REG_(TRNG_RNG_BIST_CNTR_0_OFFSET) // TRNG_RNG_BIST_CNTR_0 143 // Collected BIST results 144 // 0xffc00000 [31:22] RESERVED (0x000) RESERVED 145 // 0x003fffff [21:0] ROSC_CNTR_VAL (0x000000) Reflects the results of RNG BIST counter 146 io_ro_32 rng_bist_cntr[3]; 147 } trng_hw_t; 148 149 #define trng_hw ((trng_hw_t *)(TRNG_BASE + TRNG_RNG_IMR_OFFSET)) 150 static_assert(sizeof (trng_hw_t) == 0x00ec, ""); 151 152 #endif // _HARDWARE_STRUCTS_TRNG_H 153 154
