1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /*******************************************************************************************************************//** 8 * @addtogroup ADC_C 9 * @{ 10 **********************************************************************************************************************/ 11 12 #ifndef R_ADC_C_H 13 #define R_ADC_C_H 14 15 /*********************************************************************************************************************** 16 * Includes 17 **********************************************************************************************************************/ 18 19 #include "r_adc_c_cfg.h" 20 #include "r_adc_api.h" 21 #include "bsp_api.h" 22 23 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 24 FSP_HEADER 25 26 /*********************************************************************************************************************** 27 * Macro definitions 28 **********************************************************************************************************************/ 29 30 /** For ADC Scan configuration adc_channel_cfg_t::scan_mask. 31 * Use bitwise OR to combine these masks for desired channels. */ 32 typedef enum e_adc_c_mask 33 { 34 ADC_C_MASK_OFF = (0U), ///< No channels selected 35 ADC_C_MASK_CHANNEL_0 = (1U << 0U), ///< Channel 0 mask 36 ADC_C_MASK_CHANNEL_1 = (1U << 1U), ///< Channel 1 mask 37 ADC_C_MASK_CHANNEL_2 = (1U << 2U), ///< Channel 2 mask 38 ADC_C_MASK_CHANNEL_3 = (1U << 3U), ///< Channel 3 mask 39 ADC_C_MASK_CHANNEL_4 = (1U << 4U), ///< Channel 4 mask 40 ADC_C_MASK_CHANNEL_5 = (1U << 5U), ///< Channel 5 mask 41 ADC_C_MASK_CHANNEL_6 = (1U << 6U), ///< Channel 6 mask 42 ADC_C_MASK_CHANNEL_7 = (1U << 7U), ///< Channel 7 mask 43 ADC_C_MASK_CHANNEL_8 = (1U << 8U), ///< Channel 8 mask (Temperature sensor channel mask) 44 } adc_c_mask_t; 45 46 /** ADC trigger mode select */ 47 typedef enum e_adc_c_trigger_mode 48 { 49 ADC_C_TRIGGER_MODE_SOFTWARE = 0U, ///< Software trigger mode 50 ADC_C_TRIGGER_MODE_HARDWARE = 1U, ///< Hardware trigger mode 51 } adc_c_trigger_mode_t; 52 53 /** ADC hardware trigger source select */ 54 typedef enum e_adc_c_active_trigger 55 { 56 ADC_C_ACTIVE_TRIGGER_EXTERNAL = 0U, ///< External trigger input 57 ADC_C_ACTIVE_TRIGGER_TRGA0N = 1U, ///< Compare match with or input capture to MTU0.TGRA 58 ADC_C_ACTIVE_TRIGGER_TRGA1N = 2U, ///< Compare match with or input capture to MTU1.TGRA 59 ADC_C_ACTIVE_TRIGGER_TRGA2N = 3U, ///< Compare match with or input capture to MTU2.TGRA 60 ADC_C_ACTIVE_TRIGGER_TRGA3N = 4U, ///< Compare match with or input capture to MTU3.TGRA 61 ADC_C_ACTIVE_TRIGGER_TRGA4N = 5U, ///< Compare match with or input capture to MTU4.TGRA 62 ADC_C_ACTIVE_TRIGGER_TRGA6N = 6U, ///< Compare match with or input capture to MTU6.TGRA 63 ADC_C_ACTIVE_TRIGGER_TRGA7N = 7U, ///< Compare match with or input capture to MTU7.TGRA 64 ADC_C_ACTIVE_TRIGGER_TRG0N = 8U, ///< Compare match with MTU0.TGRE 65 ADC_C_ACTIVE_TRIGGER_TRG4AN = 9U, ///< Compare match between MTU4.TADCORA and MTU4.TCNT 66 ADC_C_ACTIVE_TRIGGER_TRG4BN = 10U, ///< Compare match between MTU4.TADCORB and MTU4.TCNT 67 ADC_C_ACTIVE_TRIGGER_TRG4AN_BN = 11U, ///< Compare match between MTU4.TADCORA and MTU4.TCNT, or between MTU4.TADCORB and MTU4.TCNT 68 ADC_C_ACTIVE_TRIGGER_TRG4ABN = 12U, ///< Compare match between MTU4.TADCORA and MTU4.TCNT, and between MTU4.TADCORB and MTU4.TCNT (when interrupt skipping function 2 is in use) 69 ADC_C_ACTIVE_TRIGGER_TRG7AN = 13U, ///< Compare match between MTU7.TADCORA and MTU7.TCNT 70 ADC_C_ACTIVE_TRIGGER_TRG7BN = 14U, ///< Compare match between MTU7.TADCORB and MTU7.TCNT 71 ADC_C_ACTIVE_TRIGGER_TRG7AN_BN = 15U, ///< Compare match between MTU7.TADCORA and MTU7.TCNT, or between MTU7.TADCORB and MTU7.TCNT 72 ADC_C_ACTIVE_TRIGGER_TRG7ABN = 16U, ///< Compare match between MTU7.TADCORA and MTU7.TCNT, and between MTU7.TADCORB and MTU7.TCNT 73 ADC_C_ACTIVE_TRIGGER_ADTRGA0 = 17U, ///< Compare match with GPT0.GTADTRA 74 ADC_C_ACTIVE_TRIGGER_ADTRGB0 = 18U, ///< Compare match with GPT0.GTADTRB 75 ADC_C_ACTIVE_TRIGGER_ADTRGA1 = 19U, ///< Compare match with GPT1.GTADTRA 76 ADC_C_ACTIVE_TRIGGER_ADTRGB1 = 20U, ///< Compare match with GPT1.GTADTRB 77 ADC_C_ACTIVE_TRIGGER_ADTRGA2 = 21U, ///< Compare match with GPT2.GTADTRA 78 ADC_C_ACTIVE_TRIGGER_ADTRGB2 = 22U, ///< Compare match with GPT2.GTADTRB 79 ADC_C_ACTIVE_TRIGGER_ADTRGA3 = 23U, ///< Compare match with GPT3.GTADTRA 80 ADC_C_ACTIVE_TRIGGER_ADTRGB3 = 24U, ///< Compare match with GPT3.GTADTRB 81 ADC_C_ACTIVE_TRIGGER_ADTRGA0_B0 = 25U, ///< Compare match with GPT0.GTADTRA or GPT0.GTADTRB 82 ADC_C_ACTIVE_TRIGGER_ADTRGA1_B1 = 26U, ///< Compare match with GPT1.GTADTRA or GPT1.GTADTRB 83 ADC_C_ACTIVE_TRIGGER_ADTRGA2_B2 = 27U, ///< Compare match with GPT2.GTADTRA or GPT2.GTADTRB 84 ADC_C_ACTIVE_TRIGGER_ADTRGA3_B3 = 28U, ///< Compare match with GPT3.GTADTRA or GPT3.GTADTRB 85 } adc_c_active_trigger_t; 86 87 /** valid edge of the trigger select */ 88 typedef enum e_adc_c_trigger_edge 89 { 90 ADC_C_TRIGGER_EDGE_FALLING = 1U, ///< Falling edge 91 ADC_C_TRIGGER_EDGE_RISING = 2U, ///< Rising edge 92 ADC_C_TRIGGER_EDGE_BOTH = 3U, ///< Both edges 93 } adc_c_trigger_edge_t; 94 95 /** ADC trigger input mode select */ 96 typedef enum e_adc_c_input_mode 97 { 98 ADC_C_INPUT_MODE_AUTO = 0U, ///< Auto mode 99 ADC_C_INPUT_MODE_STEP = 1U, ///< Step mode 100 } adc_c_input_mode_t; 101 102 /** ADC operating mode select */ 103 typedef enum e_adc_c_operating_mode 104 { 105 ADC_C_OPERATING_MODE_SCAN = 0U, ///< Scan mode 106 ADC_C_OPERATING_MODE_SELECT = 1U, ///< Select mode 107 } adc_c_operating_mode_t; 108 109 /** ADC buffer mode select */ 110 typedef enum e_adc_c_buffer_mode 111 { 112 ADC_C_BUFFER_MODE_1 = 0U, ///< 1-buffer mode 113 ADC_C_BUFFER_MODE_4 = 1U, ///< 4-buffer mode 114 } adc_c_buffer_mode_t; 115 116 /** Select the number of stages of the AD external trigger pin filter. */ 117 typedef enum e_adc_c_filter_stage_setting_t 118 { 119 ADC_C_FILTER_STAGE_SETTING_DISABLE = 0U, ///< Filter is disabled. 120 ADC_C_FILTER_STAGE_SETTING_4 = 1U, ///< 12.5 ns (80 MHz) x 4 stages 121 ADC_C_FILTER_STAGE_SETTING_8 = 2U, ///< 12.5 ns (80 MHz) x 8 stages 122 ADC_C_FILTER_STAGE_SETTING_12 = 3U, ///< 12.5 ns (80 MHz) x 12 stages 123 ADC_C_FILTER_STAGE_SETTING_16 = 4U, ///< 12.5 ns (80 MHz) x 16 stages 124 } adc_c_filter_stage_setting_t; 125 126 /** Enable or disable the conversion end interrupt of channel */ 127 typedef enum e_adc_c_interrupt_channel_setting 128 { 129 ADC_C_INTERRUPT_CHANNEL_SETTING_DISABLE = 0, ///< Interrupt output is disabled. 130 ADC_C_INTERRUPT_CHANNEL_SETTING_ENABLE = 1, ///< Interrupt output is enabled. 131 } adc_c_interrupt_channel_setting_t; 132 133 /** Extended configuration structure for ADC. */ 134 typedef struct st_adc_c_extended_cfg 135 { 136 adc_c_trigger_mode_t trigger_mode; ///< Trigger mode. 137 adc_c_active_trigger_t trigger_source; ///< Hardware trigger source. 138 adc_c_trigger_edge_t trigger_edge; ///< Valid edge of the trigger source. 139 adc_c_input_mode_t input_mode; ///< Trigger input mode. 140 adc_c_operating_mode_t operating_mode; ///< Operating mode. 141 adc_c_buffer_mode_t buffer_mode; ///< Buffer mode. 142 uint16_t sampling_time; ///< Sampling period. (6~2800) 143 adc_c_filter_stage_setting_t external_trigger_filter; ///< AD external trigger pin filter. 144 } adc_c_extended_cfg_t; 145 146 /** ADC channel(s) configuration */ 147 typedef struct st_adc_c_channel_cfg 148 { 149 uint32_t scan_mask; ///< Channels/bits: bit 0 is ch0; bit 1 is ch1. 150 adc_c_interrupt_channel_setting_t interrupt_setting; ///< Interrupt setting. 151 } adc_c_channel_cfg_t; 152 153 /*********************************************************************************************************************** 154 * Typedef definitions 155 **********************************************************************************************************************/ 156 157 /** ADC instance control block. DO NOT INITIALIZE. Initialized in @ref adc_api_t::open(). */ 158 typedef struct 159 { 160 R_ADC_C_Type * p_reg; // Base register 161 adc_cfg_t const * p_cfg; 162 uint32_t opened; // Boolean to verify that the Unit has been initialized 163 uint32_t initialized; // Initialized status of ADC 164 uint32_t scan_mask; // Scan mask used for Normal scan 165 uint32_t scan_start; 166 uint32_t operating_mode; 167 uint32_t buffer_mode; 168 169 void (* p_callback)(adc_callback_args_t *); // Pointer to callback that is called when an adc_event_t occurs. 170 adc_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. 171 172 /* Pointer to context to be passed into callback function */ 173 void const * p_context; 174 } adc_c_instance_ctrl_t; 175 176 /********************************************************************************************************************** 177 * Exported global variables 178 **********************************************************************************************************************/ 179 180 /** @cond INC_HEADER_DEFS_SEC */ 181 /** Interface Structure for user access */ 182 extern const adc_api_t g_adc_on_adc; 183 184 /** @endcond */ 185 186 /*********************************************************************************************************************** 187 * Public APIs 188 **********************************************************************************************************************/ 189 fsp_err_t R_ADC_C_Open(adc_ctrl_t * p_ctrl, adc_cfg_t const * const p_cfg); 190 fsp_err_t R_ADC_C_ScanCfg(adc_ctrl_t * p_ctrl, void const * const p_channel_cfg); 191 fsp_err_t R_ADC_C_InfoGet(adc_ctrl_t * p_ctrl, adc_info_t * p_adc_info); 192 fsp_err_t R_ADC_C_ScanStart(adc_ctrl_t * p_ctrl); 193 fsp_err_t R_ADC_C_ScanGroupStart(adc_ctrl_t * p_ctrl, adc_group_mask_t group_id); 194 fsp_err_t R_ADC_C_ScanStop(adc_ctrl_t * p_ctrl); 195 fsp_err_t R_ADC_C_StatusGet(adc_ctrl_t * p_ctrl, adc_status_t * p_status); 196 fsp_err_t R_ADC_C_Read(adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data); 197 fsp_err_t R_ADC_C_Read32(adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint32_t * const p_data); 198 fsp_err_t R_ADC_C_SampleStateCountSet(adc_ctrl_t * p_ctrl, uint16_t num_states); 199 fsp_err_t R_ADC_C_Close(adc_ctrl_t * p_ctrl); 200 fsp_err_t R_ADC_C_OffsetSet(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t offset); 201 fsp_err_t R_ADC_C_Calibrate(adc_ctrl_t * const p_ctrl, void const * p_extend); 202 fsp_err_t R_ADC_C_CallbackSet(adc_ctrl_t * const p_api_ctrl, 203 void ( * p_callback)(adc_callback_args_t *), 204 void const * const p_context, 205 adc_callback_args_t * const p_callback_memory); 206 207 /*******************************************************************************************************************//** 208 * @} (end defgroup ADC_C) 209 **********************************************************************************************************************/ 210 211 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 212 FSP_FOOTER 213 214 #endif 215
