1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_SPI_STRUCT_H_ 15 #define _SOC_SPI_STRUCT_H_ 16 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef volatile struct spi_dev_s { 24 union { 25 struct { 26 uint32_t reserved0: 16; /*reserved*/ 27 uint32_t flash_per: 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 28 uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 29 uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 30 uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/ 31 uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/ 32 uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 33 uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 34 uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 35 uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 36 uint32_t flash_pp: 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/ 37 uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 38 uint32_t flash_rdsr: 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/ 39 uint32_t flash_rdid: 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ 40 uint32_t flash_wrdi: 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ 41 uint32_t flash_wren: 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ 42 uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/ 43 }; 44 uint32_t val; 45 } cmd; 46 uint32_t addr; /*addr to slave / from master. SPI transfer from the MSB to the LSB. If length > 32 bits, then address continues from MSB of slv_wr_status.*/ 47 union { 48 struct { 49 uint32_t reserved0: 10; /*reserved*/ 50 uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/ 51 uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ 52 uint32_t wait_flash_idle_en: 1; /*wait flash idle when program flash or erase flash. 1: enable 0: disable.*/ 53 uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable.*/ 54 uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ 55 uint32_t resandres: 1; /*The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable.*/ 56 uint32_t reserved16: 4; /*reserved*/ 57 uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ 58 uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/ 59 uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/ 60 uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/ 61 uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/ 62 uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first*/ 63 uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/ 64 uint32_t reserved27: 5; /*reserved*/ 65 }; 66 uint32_t val; 67 } ctrl; 68 union { 69 struct { 70 uint32_t reserved0: 16; /*reserved*/ 71 uint32_t cs_hold_delay_res:12; /*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/ 72 uint32_t cs_hold_delay: 4; /*SPI cs signal is delayed by spi clock cycles*/ 73 }; 74 uint32_t val; 75 } ctrl1; 76 union { 77 struct { 78 uint32_t status: 16; /*In the slave mode, it is the status for master to read out.*/ 79 uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit.*/ 80 uint32_t status_ext: 8; /*In the slave mode,it is the status for master to read out.*/ 81 }; 82 uint32_t val; 83 } rd_status; 84 union { 85 struct { 86 uint32_t setup_time: 4; /*(cycles-1) of ,prepare, phase by spi clock, this bits combined with spi_cs_setup bit.*/ 87 uint32_t hold_time: 4; /*delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit.*/ 88 uint32_t ck_out_low_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits.*/ 89 uint32_t ck_out_high_mode: 4; /*modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits.*/ 90 uint32_t miso_delay_mode: 2; /*MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ 91 uint32_t miso_delay_num: 3; /*MISO signals are delayed by system clock cycles*/ 92 uint32_t mosi_delay_mode: 2; /*MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ 93 uint32_t mosi_delay_num: 3; /*MOSI signals are delayed by system clock cycles*/ 94 uint32_t cs_delay_mode: 2; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle*/ 95 uint32_t cs_delay_num: 4; /*spi_cs signal is delayed by system clock cycles*/ 96 }; 97 uint32_t val; 98 } ctrl2; 99 union { 100 struct { 101 uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.*/ 102 uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/ 103 uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/ 104 uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk.*/ 105 uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/ 106 }; 107 uint32_t val; 108 } clock; 109 union { 110 struct { 111 uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable.*/ 112 uint32_t reserved1: 3; /*reserved*/ 113 uint32_t cs_hold: 1; /*spi cs keep low when spi is in ,done, phase. 1: enable 0: disable.*/ 114 uint32_t cs_setup: 1; /*spi cs is enable when spi is in ,prepare, phase. 1: enable 0: disable.*/ 115 uint32_t ck_i_edge: 1; /*In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits.*/ 116 uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/ 117 uint32_t reserved8: 2; /*reserved*/ 118 uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_endian*/ 119 uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/ 120 uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/ 121 uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/ 122 uint32_t fwrite_dio: 1; /*In the write operations address phase and read-data phase apply 2 signals.*/ 123 uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/ 124 uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/ 125 uint32_t usr_hold_pol: 1; /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/ 126 uint32_t usr_dout_hold: 1; /*spi is hold at data out state the bit combined with spi_usr_hold_pol bit.*/ 127 uint32_t usr_din_hold: 1; /*spi is hold at data in state the bit combined with spi_usr_hold_pol bit.*/ 128 uint32_t usr_dummy_hold: 1; /*spi is hold at dummy state the bit combined with spi_usr_hold_pol bit.*/ 129 uint32_t usr_addr_hold: 1; /*spi is hold at address state the bit combined with spi_usr_hold_pol bit.*/ 130 uint32_t usr_cmd_hold: 1; /*spi is hold at command state the bit combined with spi_usr_hold_pol bit.*/ 131 uint32_t usr_prep_hold: 1; /*spi is hold at prepare state the bit combined with spi_usr_hold_pol bit.*/ 132 uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/ 133 uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/ 134 uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable.*/ 135 uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/ 136 uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/ 137 uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/ 138 uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/ 139 uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/ 140 }; 141 uint32_t val; 142 } user; 143 union { 144 struct { 145 uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ 146 uint32_t reserved8: 18; /*reserved*/ 147 uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ 148 }; 149 uint32_t val; 150 } user1; 151 union { 152 struct { 153 uint32_t usr_command_value: 16; /*The value of command. Output sequence: bit 7-0 and then 15-8.*/ 154 uint32_t reserved16: 12; /*reserved*/ 155 uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ 156 }; 157 uint32_t val; 158 } user2; 159 union { 160 struct { 161 uint32_t usr_mosi_dbitlen:24; /*The length in bits of write-data. The register value shall be (bit_num-1).*/ 162 uint32_t reserved24: 8; /*reserved*/ 163 }; 164 uint32_t val; 165 } mosi_dlen; 166 union { 167 struct { 168 uint32_t usr_miso_dbitlen:24; /*The length in bits of read-data. The register value shall be (bit_num-1).*/ 169 uint32_t reserved24: 8; /*reserved*/ 170 }; 171 uint32_t val; 172 } miso_dlen; 173 uint32_t slv_wr_status; /*In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition.*/ 174 union { 175 struct { 176 uint32_t cs0_dis: 1; /*SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin*/ 177 uint32_t cs1_dis: 1; /*SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin*/ 178 uint32_t cs2_dis: 1; /*SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin*/ 179 uint32_t reserved3: 2; /*reserved*/ 180 uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable*/ 181 uint32_t master_cs_pol: 3; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.*/ 182 uint32_t reserved9: 2; /*reserved*/ 183 uint32_t master_ck_sel: 3; /*In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.*/ 184 uint32_t reserved14: 15; /*reserved*/ 185 uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/ 186 uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/ 187 uint32_t reserved31: 1; /*reserved*/ 188 }; 189 uint32_t val; 190 } pin; 191 union { 192 struct { 193 uint32_t rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/ 194 uint32_t wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/ 195 uint32_t rd_sta_done: 1; /*The interrupt raw bit for the completion of read-status operation in the slave mode.*/ 196 uint32_t wr_sta_done: 1; /*The interrupt raw bit for the completion of write-status operation in the slave mode.*/ 197 uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/ 198 uint32_t rd_buf_inten: 1; /*The interrupt enable bit for the completion of read-buffer operation in the slave mode.*/ 199 uint32_t wr_buf_inten: 1; /*The interrupt enable bit for the completion of write-buffer operation in the slave mode.*/ 200 uint32_t rd_sta_inten: 1; /*The interrupt enable bit for the completion of read-status operation in the slave mode.*/ 201 uint32_t wr_sta_inten: 1; /*The interrupt enable bit for the completion of write-status operation in the slave mode.*/ 202 uint32_t trans_inten: 1; /*The interrupt enable bit for the completion of any operation in both the master mode and the slave mode.*/ 203 uint32_t cs_i_mode: 2; /*In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.*/ 204 uint32_t reserved12: 5; /*reserved*/ 205 uint32_t last_command: 3; /*In the slave mode it is the value of command.*/ 206 uint32_t last_state: 3; /*In the slave mode it is the state of spi state machine.*/ 207 uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode. 4: read-status*/ 208 uint32_t cmd_define: 1; /*1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.*/ 209 uint32_t wr_rd_sta_en: 1; /*write and read status enable in the slave mode*/ 210 uint32_t wr_rd_buf_en: 1; /*write and read buffer enable in the slave mode*/ 211 uint32_t slave_mode: 1; /*1: slave mode 0: master mode.*/ 212 uint32_t sync_reset: 1; /*Software reset enable, reset the spi clock line cs line and data lines.*/ 213 }; 214 uint32_t val; 215 } slave; 216 union { 217 struct { 218 uint32_t rdbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-buffer operations.*/ 219 uint32_t wrbuf_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-buffer operations.*/ 220 uint32_t rdsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for read-status operations.*/ 221 uint32_t wrsta_dummy_en: 1; /*In the slave mode it is the enable bit of dummy phase for write-status operations.*/ 222 uint32_t wr_addr_bitlen: 6; /*In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1).*/ 223 uint32_t rd_addr_bitlen: 6; /*In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1).*/ 224 uint32_t reserved16: 9; /*reserved*/ 225 uint32_t status_readback: 1; /*In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS.*/ 226 uint32_t status_fast_en: 1; /*In the slave mode enable fast read status.*/ 227 uint32_t status_bitlen: 5; /*In the slave mode it is the length of status bit.*/ 228 }; 229 uint32_t val; 230 } slave1; 231 union { 232 struct { 233 uint32_t rdsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1).*/ 234 uint32_t wrsta_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1).*/ 235 uint32_t rdbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1).*/ 236 uint32_t wrbuf_dummy_cyclelen: 8; /*In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1).*/ 237 }; 238 uint32_t val; 239 } slave2; 240 union { 241 struct { 242 uint32_t rdbuf_cmd_value: 8; /*In the slave mode it is the value of read-buffer command.*/ 243 uint32_t wrbuf_cmd_value: 8; /*In the slave mode it is the value of write-buffer command.*/ 244 uint32_t rdsta_cmd_value: 8; /*In the slave mode it is the value of read-status command.*/ 245 uint32_t wrsta_cmd_value: 8; /*In the slave mode it is the value of write-status command.*/ 246 }; 247 uint32_t val; 248 } slave3; 249 union { 250 struct { 251 uint32_t bit_len: 24; /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/ 252 uint32_t reserved24: 8; /*reserved*/ 253 }; 254 uint32_t val; 255 } slv_wrbuf_dlen; 256 union { 257 struct { 258 uint32_t bit_len: 24; /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/ 259 uint32_t reserved24: 8; /*reserved*/ 260 }; 261 uint32_t val; 262 } slv_rdbuf_dlen; 263 union { 264 struct { 265 uint32_t req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/ 266 uint32_t usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ 267 uint32_t flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/ 268 uint32_t flash_pes_en: 1; /*For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable.*/ 269 uint32_t reserved4: 28; /*reserved*/ 270 }; 271 uint32_t val; 272 } cache_fctrl; 273 union { 274 struct { 275 uint32_t reserved0: 1; /*reserved*/ 276 uint32_t usr_sram_dio: 1; /*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ 277 uint32_t usr_sram_qio: 1; /*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ 278 uint32_t usr_wr_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/ 279 uint32_t usr_rd_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/ 280 uint32_t cache_sram_usr_rcmd: 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/ 281 uint32_t sram_bytes_len: 8; /*For SPI0 In the sram mode it is the byte length of spi read sram data.*/ 282 uint32_t sram_dummy_cyclelen: 8; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ 283 uint32_t sram_addr_bitlen: 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ 284 uint32_t cache_sram_usr_wcmd: 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/ 285 uint32_t reserved29: 3; /*reserved*/ 286 }; 287 uint32_t val; 288 } cache_sctrl; 289 union { 290 struct { 291 uint32_t dio: 1; /*For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ 292 uint32_t qio: 1; /*For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done.*/ 293 uint32_t reserved2: 2; /*For SPI0 SRAM write enable . SRAM write operation will be triggered when the bit is set. The bit will be cleared once the operation done.*/ 294 uint32_t rst_io: 1; /*For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done*/ 295 uint32_t reserved5:27; /*reserved*/ 296 }; 297 uint32_t val; 298 } sram_cmd; 299 union { 300 struct { 301 uint32_t usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for SRAM.*/ 302 uint32_t reserved16: 12; /*reserved*/ 303 uint32_t usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ 304 }; 305 uint32_t val; 306 } sram_drd_cmd; 307 union { 308 struct { 309 uint32_t usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for SRAM.*/ 310 uint32_t reserved16: 12; /*reserved*/ 311 uint32_t usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1).*/ 312 }; 313 uint32_t val; 314 } sram_dwr_cmd; 315 union { 316 struct { 317 uint32_t slv_rdata_bit:24; /*In the slave mode it is the bit length of read data. The value is the length - 1.*/ 318 uint32_t reserved24: 8; /*reserved*/ 319 }; 320 uint32_t val; 321 } slv_rd_bit; 322 uint32_t reserved_68; 323 uint32_t reserved_6c; 324 uint32_t reserved_70; 325 uint32_t reserved_74; 326 uint32_t reserved_78; 327 uint32_t reserved_7c; 328 uint32_t data_buf[16]; /*data buffer*/ 329 uint32_t tx_crc; /*For SPI1 the value of crc32 for 256 bits data.*/ 330 uint32_t reserved_c4; 331 uint32_t reserved_c8; 332 uint32_t reserved_cc; 333 uint32_t reserved_d0; 334 uint32_t reserved_d4; 335 uint32_t reserved_d8; 336 uint32_t reserved_dc; 337 uint32_t reserved_e0; 338 uint32_t reserved_e4; 339 uint32_t reserved_e8; 340 uint32_t reserved_ec; 341 union { 342 struct { 343 uint32_t t_pp_time: 12; /*page program delay time by system clock.*/ 344 uint32_t reserved12: 4; /*reserved*/ 345 uint32_t t_pp_shift: 4; /*page program delay time shift .*/ 346 uint32_t reserved20:11; /*reserved*/ 347 uint32_t t_pp_ena: 1; /*page program delay enable.*/ 348 }; 349 uint32_t val; 350 } ext0; 351 union { 352 struct { 353 uint32_t t_erase_time: 12; /*erase flash delay time by system clock.*/ 354 uint32_t reserved12: 4; /*reserved*/ 355 uint32_t t_erase_shift: 4; /*erase flash delay time shift.*/ 356 uint32_t reserved20: 11; /*reserved*/ 357 uint32_t t_erase_ena: 1; /*erase flash delay enable.*/ 358 }; 359 uint32_t val; 360 } ext1; 361 union { 362 struct { 363 uint32_t st: 3; /*The status of spi state machine .*/ 364 uint32_t reserved3: 29; /*reserved*/ 365 }; 366 uint32_t val; 367 } ext2; 368 union { 369 struct { 370 uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ,idle, phase 2: hold at ,prepare, phase.*/ 371 uint32_t reserved2: 30; /*reserved*/ 372 }; 373 uint32_t val; 374 } ext3; 375 union { 376 struct { 377 uint32_t reserved0: 2; /*reserved*/ 378 uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/ 379 uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/ 380 uint32_t ahbm_fifo_rst: 1; /*reset spi dma ahb master fifo pointer.*/ 381 uint32_t ahbm_rst: 1; /*reset spi dma ahb master.*/ 382 uint32_t in_loop_test: 1; /*Set bit to test in link.*/ 383 uint32_t out_loop_test: 1; /*Set bit to test out link.*/ 384 uint32_t out_auto_wrback: 1; /*when the link is empty jump to next automatically.*/ 385 uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/ 386 uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/ 387 uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/ 388 uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/ 389 uint32_t reserved13: 1; /*reserved*/ 390 uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/ 391 uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/ 392 uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/ 393 uint32_t reserved17: 15; /*reserved*/ 394 }; 395 uint32_t val; 396 } dma_conf; 397 union { 398 struct { 399 uint32_t addr: 20; /*The address of the first outlink descriptor.*/ 400 uint32_t reserved20: 8; /*reserved*/ 401 uint32_t stop: 1; /*Set the bit to stop to use outlink descriptor.*/ 402 uint32_t start: 1; /*Set the bit to start to use outlink descriptor.*/ 403 uint32_t restart: 1; /*Set the bit to mount on new outlink descriptors.*/ 404 uint32_t reserved31: 1; /*reserved*/ 405 }; 406 uint32_t val; 407 } dma_out_link; 408 union { 409 struct { 410 uint32_t addr: 20; /*The address of the first inlink descriptor.*/ 411 uint32_t auto_ret: 1; /*when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong*/ 412 uint32_t reserved21: 7; /*reserved*/ 413 uint32_t stop: 1; /*Set the bit to stop to use inlink descriptor.*/ 414 uint32_t start: 1; /*Set the bit to start to use inlink descriptor.*/ 415 uint32_t restart: 1; /*Set the bit to mount on new inlink descriptors.*/ 416 uint32_t reserved31: 1; /*reserved*/ 417 }; 418 uint32_t val; 419 } dma_in_link; 420 union { 421 struct { 422 uint32_t rx_en: 1; /*spi dma read data status bit.*/ 423 uint32_t tx_en: 1; /*spi dma write data status bit.*/ 424 uint32_t reserved2: 30; /*spi dma read data from memory count.*/ 425 }; 426 uint32_t val; 427 } dma_status; 428 union { 429 struct { 430 uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors.*/ 431 uint32_t outlink_dscr_error: 1; /*The enable bit for outlink descriptor error.*/ 432 uint32_t inlink_dscr_error: 1; /*The enable bit for inlink descriptor error.*/ 433 uint32_t in_done: 1; /*The enable bit for completing usage of a inlink descriptor.*/ 434 uint32_t in_err_eof: 1; /*The enable bit for receiving error.*/ 435 uint32_t in_suc_eof: 1; /*The enable bit for completing receiving all the packets from host.*/ 436 uint32_t out_done: 1; /*The enable bit for completing usage of a outlink descriptor .*/ 437 uint32_t out_eof: 1; /*The enable bit for sending a packet to host done.*/ 438 uint32_t out_total_eof: 1; /*The enable bit for sending all the packets to host done.*/ 439 uint32_t reserved9: 23; /*reserved*/ 440 }; 441 uint32_t val; 442 } dma_int_ena; 443 union { 444 struct { 445 uint32_t inlink_dscr_empty: 1; /*The raw bit for lack of enough inlink descriptors.*/ 446 uint32_t outlink_dscr_error: 1; /*The raw bit for outlink descriptor error.*/ 447 uint32_t inlink_dscr_error: 1; /*The raw bit for inlink descriptor error.*/ 448 uint32_t in_done: 1; /*The raw bit for completing usage of a inlink descriptor.*/ 449 uint32_t in_err_eof: 1; /*The raw bit for receiving error.*/ 450 uint32_t in_suc_eof: 1; /*The raw bit for completing receiving all the packets from host.*/ 451 uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor.*/ 452 uint32_t out_eof: 1; /*The raw bit for sending a packet to host done.*/ 453 uint32_t out_total_eof: 1; /*The raw bit for sending all the packets to host done.*/ 454 uint32_t reserved9: 23; /*reserved*/ 455 }; 456 uint32_t val; 457 } dma_int_raw; 458 union { 459 struct { 460 uint32_t inlink_dscr_empty: 1; /*The status bit for lack of enough inlink descriptors.*/ 461 uint32_t outlink_dscr_error: 1; /*The status bit for outlink descriptor error.*/ 462 uint32_t inlink_dscr_error: 1; /*The status bit for inlink descriptor error.*/ 463 uint32_t in_done: 1; /*The status bit for completing usage of a inlink descriptor.*/ 464 uint32_t in_err_eof: 1; /*The status bit for receiving error.*/ 465 uint32_t in_suc_eof: 1; /*The status bit for completing receiving all the packets from host.*/ 466 uint32_t out_done: 1; /*The status bit for completing usage of a outlink descriptor.*/ 467 uint32_t out_eof: 1; /*The status bit for sending a packet to host done.*/ 468 uint32_t out_total_eof: 1; /*The status bit for sending all the packets to host done.*/ 469 uint32_t reserved9: 23; /*reserved*/ 470 }; 471 uint32_t val; 472 } dma_int_st; 473 union { 474 struct { 475 uint32_t inlink_dscr_empty: 1; /*The clear bit for lack of enough inlink descriptors.*/ 476 uint32_t outlink_dscr_error: 1; /*The clear bit for outlink descriptor error.*/ 477 uint32_t inlink_dscr_error: 1; /*The clear bit for inlink descriptor error.*/ 478 uint32_t in_done: 1; /*The clear bit for completing usage of a inlink descriptor.*/ 479 uint32_t in_err_eof: 1; /*The clear bit for receiving error.*/ 480 uint32_t in_suc_eof: 1; /*The clear bit for completing receiving all the packets from host.*/ 481 uint32_t out_done: 1; /*The clear bit for completing usage of a outlink descriptor.*/ 482 uint32_t out_eof: 1; /*The clear bit for sending a packet to host done.*/ 483 uint32_t out_total_eof: 1; /*The clear bit for sending all the packets to host done.*/ 484 uint32_t reserved9: 23; /*reserved*/ 485 }; 486 uint32_t val; 487 } dma_int_clr; 488 uint32_t dma_in_err_eof_des_addr; /*The inlink descriptor address when spi dma produce receiving error.*/ 489 uint32_t dma_in_suc_eof_des_addr; /*The last inlink descriptor address when spi dma produce from_suc_eof.*/ 490 uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/ 491 uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/ 492 uint32_t dma_inlink_dscr_bf1; /*The content of current in descriptor data buffer pointer.*/ 493 uint32_t dma_out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produce eof.*/ 494 uint32_t dma_out_eof_des_addr; /*The last outlink descriptor address when spi dma produce to_eof.*/ 495 uint32_t dma_outlink_dscr; /*The content of current out descriptor pointer.*/ 496 uint32_t dma_outlink_dscr_bf0; /*The content of next out descriptor pointer.*/ 497 uint32_t dma_outlink_dscr_bf1; /*The content of current out descriptor data buffer pointer.*/ 498 uint32_t dma_rx_status; /*spi dma read data from memory status.*/ 499 uint32_t dma_tx_status; /*spi dma write data to memory status.*/ 500 uint32_t reserved_150; 501 uint32_t reserved_154; 502 uint32_t reserved_158; 503 uint32_t reserved_15c; 504 uint32_t reserved_160; 505 uint32_t reserved_164; 506 uint32_t reserved_168; 507 uint32_t reserved_16c; 508 uint32_t reserved_170; 509 uint32_t reserved_174; 510 uint32_t reserved_178; 511 uint32_t reserved_17c; 512 uint32_t reserved_180; 513 uint32_t reserved_184; 514 uint32_t reserved_188; 515 uint32_t reserved_18c; 516 uint32_t reserved_190; 517 uint32_t reserved_194; 518 uint32_t reserved_198; 519 uint32_t reserved_19c; 520 uint32_t reserved_1a0; 521 uint32_t reserved_1a4; 522 uint32_t reserved_1a8; 523 uint32_t reserved_1ac; 524 uint32_t reserved_1b0; 525 uint32_t reserved_1b4; 526 uint32_t reserved_1b8; 527 uint32_t reserved_1bc; 528 uint32_t reserved_1c0; 529 uint32_t reserved_1c4; 530 uint32_t reserved_1c8; 531 uint32_t reserved_1cc; 532 uint32_t reserved_1d0; 533 uint32_t reserved_1d4; 534 uint32_t reserved_1d8; 535 uint32_t reserved_1dc; 536 uint32_t reserved_1e0; 537 uint32_t reserved_1e4; 538 uint32_t reserved_1e8; 539 uint32_t reserved_1ec; 540 uint32_t reserved_1f0; 541 uint32_t reserved_1f4; 542 uint32_t reserved_1f8; 543 uint32_t reserved_1fc; 544 uint32_t reserved_200; 545 uint32_t reserved_204; 546 uint32_t reserved_208; 547 uint32_t reserved_20c; 548 uint32_t reserved_210; 549 uint32_t reserved_214; 550 uint32_t reserved_218; 551 uint32_t reserved_21c; 552 uint32_t reserved_220; 553 uint32_t reserved_224; 554 uint32_t reserved_228; 555 uint32_t reserved_22c; 556 uint32_t reserved_230; 557 uint32_t reserved_234; 558 uint32_t reserved_238; 559 uint32_t reserved_23c; 560 uint32_t reserved_240; 561 uint32_t reserved_244; 562 uint32_t reserved_248; 563 uint32_t reserved_24c; 564 uint32_t reserved_250; 565 uint32_t reserved_254; 566 uint32_t reserved_258; 567 uint32_t reserved_25c; 568 uint32_t reserved_260; 569 uint32_t reserved_264; 570 uint32_t reserved_268; 571 uint32_t reserved_26c; 572 uint32_t reserved_270; 573 uint32_t reserved_274; 574 uint32_t reserved_278; 575 uint32_t reserved_27c; 576 uint32_t reserved_280; 577 uint32_t reserved_284; 578 uint32_t reserved_288; 579 uint32_t reserved_28c; 580 uint32_t reserved_290; 581 uint32_t reserved_294; 582 uint32_t reserved_298; 583 uint32_t reserved_29c; 584 uint32_t reserved_2a0; 585 uint32_t reserved_2a4; 586 uint32_t reserved_2a8; 587 uint32_t reserved_2ac; 588 uint32_t reserved_2b0; 589 uint32_t reserved_2b4; 590 uint32_t reserved_2b8; 591 uint32_t reserved_2bc; 592 uint32_t reserved_2c0; 593 uint32_t reserved_2c4; 594 uint32_t reserved_2c8; 595 uint32_t reserved_2cc; 596 uint32_t reserved_2d0; 597 uint32_t reserved_2d4; 598 uint32_t reserved_2d8; 599 uint32_t reserved_2dc; 600 uint32_t reserved_2e0; 601 uint32_t reserved_2e4; 602 uint32_t reserved_2e8; 603 uint32_t reserved_2ec; 604 uint32_t reserved_2f0; 605 uint32_t reserved_2f4; 606 uint32_t reserved_2f8; 607 uint32_t reserved_2fc; 608 uint32_t reserved_300; 609 uint32_t reserved_304; 610 uint32_t reserved_308; 611 uint32_t reserved_30c; 612 uint32_t reserved_310; 613 uint32_t reserved_314; 614 uint32_t reserved_318; 615 uint32_t reserved_31c; 616 uint32_t reserved_320; 617 uint32_t reserved_324; 618 uint32_t reserved_328; 619 uint32_t reserved_32c; 620 uint32_t reserved_330; 621 uint32_t reserved_334; 622 uint32_t reserved_338; 623 uint32_t reserved_33c; 624 uint32_t reserved_340; 625 uint32_t reserved_344; 626 uint32_t reserved_348; 627 uint32_t reserved_34c; 628 uint32_t reserved_350; 629 uint32_t reserved_354; 630 uint32_t reserved_358; 631 uint32_t reserved_35c; 632 uint32_t reserved_360; 633 uint32_t reserved_364; 634 uint32_t reserved_368; 635 uint32_t reserved_36c; 636 uint32_t reserved_370; 637 uint32_t reserved_374; 638 uint32_t reserved_378; 639 uint32_t reserved_37c; 640 uint32_t reserved_380; 641 uint32_t reserved_384; 642 uint32_t reserved_388; 643 uint32_t reserved_38c; 644 uint32_t reserved_390; 645 uint32_t reserved_394; 646 uint32_t reserved_398; 647 uint32_t reserved_39c; 648 uint32_t reserved_3a0; 649 uint32_t reserved_3a4; 650 uint32_t reserved_3a8; 651 uint32_t reserved_3ac; 652 uint32_t reserved_3b0; 653 uint32_t reserved_3b4; 654 uint32_t reserved_3b8; 655 uint32_t reserved_3bc; 656 uint32_t reserved_3c0; 657 uint32_t reserved_3c4; 658 uint32_t reserved_3c8; 659 uint32_t reserved_3cc; 660 uint32_t reserved_3d0; 661 uint32_t reserved_3d4; 662 uint32_t reserved_3d8; 663 uint32_t reserved_3dc; 664 uint32_t reserved_3e0; 665 uint32_t reserved_3e4; 666 uint32_t reserved_3e8; 667 uint32_t reserved_3ec; 668 uint32_t reserved_3f0; 669 uint32_t reserved_3f4; 670 uint32_t reserved_3f8; 671 union { 672 struct { 673 uint32_t date: 28; /*SPI register version.*/ 674 uint32_t reserved28: 4; /*reserved*/ 675 }; 676 uint32_t val; 677 } date; 678 } spi_dev_t; 679 extern spi_dev_t SPI0; /* SPI0 IS FOR INTERNAL USE*/ 680 extern spi_dev_t SPI1; 681 extern spi_dev_t SPI2; 682 extern spi_dev_t SPI3; 683 684 #ifdef __cplusplus 685 } 686 #endif 687 688 #endif /* _SOC_SPI_STRUCT_H_ */ 689
