1 // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #include <string.h>
15 #include "esp_types.h"
16 #include "esp_attr.h"
17 #include "esp_intr_alloc.h"
18 #include "esp_log.h"
19 #include "esp_err.h"
20 #include "malloc.h"
21 #include "freertos/FreeRTOS.h"
22 #include "freertos/semphr.h"
23 #include "freertos/ringbuf.h"
24 #include "hal/uart_hal.h"
25 #include "hal/gpio_hal.h"
26 #include "soc/uart_periph.h"
27 #include "soc/rtc_cntl_reg.h"
28 #include "driver/uart.h"
29 #include "driver/gpio.h"
30 #include "driver/uart_select.h"
31 #include "driver/periph_ctrl.h"
32 #include "sdkconfig.h"
33 #include "esp_rom_gpio.h"
34
35 #if CONFIG_IDF_TARGET_ESP32
36 #include "esp32/clk.h"
37 #elif CONFIG_IDF_TARGET_ESP32S2
38 #include "esp32s2/clk.h"
39 #elif CONFIG_IDF_TARGET_ESP32S3
40 #include "esp32s3/clk.h"
41 #elif CONFIG_IDF_TARGET_ESP32C3
42 #include "esp32c3/clk.h"
43 #endif
44
45 #ifdef CONFIG_UART_ISR_IN_IRAM
46 #define UART_ISR_ATTR IRAM_ATTR
47 #else
48 #define UART_ISR_ATTR
49 #endif
50
51 #define XOFF (0x13)
52 #define XON (0x11)
53
54 static const char* UART_TAG = "uart";
55 #define UART_CHECK(a, str, ret_val) \
56 if (!(a)) { \
57 ESP_LOGE(UART_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
58 return (ret_val); \
59 }
60
61 #define UART_EMPTY_THRESH_DEFAULT (10)
62 #define UART_FULL_THRESH_DEFAULT (120)
63 #define UART_TOUT_THRESH_DEFAULT (10)
64 #define UART_CLKDIV_FRAG_BIT_WIDTH (3)
65 #define UART_TX_IDLE_NUM_DEFAULT (0)
66 #define UART_PATTERN_DET_QLEN_DEFAULT (10)
67 #define UART_MIN_WAKEUP_THRESH (UART_LL_MIN_WAKEUP_THRESH)
68
69 #define UART_INTR_CONFIG_FLAG ((UART_INTR_RXFIFO_FULL) \
70 | (UART_INTR_RXFIFO_TOUT) \
71 | (UART_INTR_RXFIFO_OVF) \
72 | (UART_INTR_BRK_DET) \
73 | (UART_INTR_PARITY_ERR))
74
75 #define UART_ENTER_CRITICAL_ISR(mux) portENTER_CRITICAL_ISR(mux)
76 #define UART_EXIT_CRITICAL_ISR(mux) portEXIT_CRITICAL_ISR(mux)
77 #define UART_ENTER_CRITICAL(mux) portENTER_CRITICAL(mux)
78 #define UART_EXIT_CRITICAL(mux) portEXIT_CRITICAL(mux)
79
80
81 // Check actual UART mode set
82 #define UART_IS_MODE_SET(uart_number, mode) ((p_uart_obj[uart_number]->uart_mode == mode))
83
84 #define UART_CONTEX_INIT_DEF(uart_num) {\
85 .hal.dev = UART_LL_GET_HW(uart_num),\
86 .spinlock = portMUX_INITIALIZER_UNLOCKED,\
87 .hw_enabled = false,\
88 }
89
90 #if SOC_UART_SUPPORT_RTC_CLK
91 #define RTC_ENABLED(uart_num) (BIT(uart_num))
92 #endif
93
94 typedef struct {
95 uart_event_type_t type; /*!< UART TX data type */
96 struct {
97 int brk_len;
98 size_t size;
99 uint8_t data[0];
100 } tx_data;
101 } uart_tx_data_t;
102
103 typedef struct {
104 int wr;
105 int rd;
106 int len;
107 int* data;
108 } uart_pat_rb_t;
109
110 typedef struct {
111 uart_port_t uart_num; /*!< UART port number*/
112 int queue_size; /*!< UART event queue size*/
113 QueueHandle_t xQueueUart; /*!< UART queue handler*/
114 intr_handle_t intr_handle; /*!< UART interrupt handle*/
115 uart_mode_t uart_mode; /*!< UART controller actual mode set by uart_set_mode() */
116 bool coll_det_flg; /*!< UART collision detection flag */
117 bool rx_always_timeout_flg; /*!< UART always detect rx timeout flag */
118
119 //rx parameters
120 int rx_buffered_len; /*!< UART cached data length */
121 SemaphoreHandle_t rx_mux; /*!< UART RX data mutex*/
122 int rx_buf_size; /*!< RX ring buffer size */
123 RingbufHandle_t rx_ring_buf; /*!< RX ring buffer handler*/
124 bool rx_buffer_full_flg; /*!< RX ring buffer full flag. */
125 uint32_t rx_cur_remain; /*!< Data number that waiting to be read out in ring buffer item*/
126 uint8_t* rx_ptr; /*!< pointer to the current data in ring buffer*/
127 uint8_t* rx_head_ptr; /*!< pointer to the head of RX item*/
128 uint8_t rx_data_buf[SOC_UART_FIFO_LEN]; /*!< Data buffer to stash FIFO data*/
129 uint8_t rx_stash_len; /*!< stashed data length.(When using flow control, after reading out FIFO data, if we fail to push to buffer, we can just stash them.) */
130 uart_pat_rb_t rx_pattern_pos;
131
132 //tx parameters
133 SemaphoreHandle_t tx_fifo_sem; /*!< UART TX FIFO semaphore*/
134 SemaphoreHandle_t tx_mux; /*!< UART TX mutex*/
135 SemaphoreHandle_t tx_done_sem; /*!< UART TX done semaphore*/
136 SemaphoreHandle_t tx_brk_sem; /*!< UART TX send break done semaphore*/
137 int tx_buf_size; /*!< TX ring buffer size */
138 RingbufHandle_t tx_ring_buf; /*!< TX ring buffer handler*/
139 bool tx_waiting_fifo; /*!< this flag indicates that some task is waiting for FIFO empty interrupt, used to send all data without any data buffer*/
140 uint8_t* tx_ptr; /*!< TX data pointer to push to FIFO in TX buffer mode*/
141 uart_tx_data_t* tx_head; /*!< TX data pointer to head of the current buffer in TX ring buffer*/
142 uint32_t tx_len_tot; /*!< Total length of current item in ring buffer*/
143 uint32_t tx_len_cur;
144 uint8_t tx_brk_flg; /*!< Flag to indicate to send a break signal in the end of the item sending procedure */
145 uint8_t tx_brk_len; /*!< TX break signal cycle length/number */
146 uint8_t tx_waiting_brk; /*!< Flag to indicate that TX FIFO is ready to send break signal after FIFO is empty, do not push data into TX FIFO right now.*/
147 uart_select_notif_callback_t uart_select_notif_callback; /*!< Notification about select() events */
148 } uart_obj_t;
149
150 typedef struct {
151 uart_hal_context_t hal; /*!< UART hal context*/
152 portMUX_TYPE spinlock;
153 bool hw_enabled;
154 } uart_context_t;
155
156 static uart_obj_t *p_uart_obj[UART_NUM_MAX] = {0};
157
158 static uart_context_t uart_context[UART_NUM_MAX] = {
159 UART_CONTEX_INIT_DEF(UART_NUM_0),
160 UART_CONTEX_INIT_DEF(UART_NUM_1),
161 #if UART_NUM_MAX > 2
162 UART_CONTEX_INIT_DEF(UART_NUM_2),
163 #endif
164 };
165
166 static portMUX_TYPE uart_selectlock = portMUX_INITIALIZER_UNLOCKED;
167
168 #if SOC_UART_SUPPORT_RTC_CLK
169
170 static uint8_t rtc_enabled = 0;
171 static portMUX_TYPE rtc_num_spinlock = portMUX_INITIALIZER_UNLOCKED;
172
rtc_clk_enable(uart_port_t uart_num)173 static void rtc_clk_enable(uart_port_t uart_num)
174 {
175 portENTER_CRITICAL(&rtc_num_spinlock);
176 if (!(rtc_enabled & RTC_ENABLED(uart_num))) {
177 rtc_enabled |= RTC_ENABLED(uart_num);
178 }
179 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
180 portEXIT_CRITICAL(&rtc_num_spinlock);
181 }
182
rtc_clk_disable(uart_port_t uart_num)183 static void rtc_clk_disable(uart_port_t uart_num)
184 {
185 assert(rtc_enabled & RTC_ENABLED(uart_num));
186
187 portENTER_CRITICAL(&rtc_num_spinlock);
188 rtc_enabled &= ~RTC_ENABLED(uart_num);
189 if (rtc_enabled == 0) {
190 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
191 }
192 portEXIT_CRITICAL(&rtc_num_spinlock);
193 }
194 #endif
195
uart_module_enable(uart_port_t uart_num)196 static void uart_module_enable(uart_port_t uart_num)
197 {
198 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
199 if (uart_context[uart_num].hw_enabled != true) {
200 if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
201 periph_module_reset(uart_periph_signal[uart_num].module);
202 }
203 periph_module_enable(uart_periph_signal[uart_num].module);
204 uart_context[uart_num].hw_enabled = true;
205 }
206 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
207 }
208
uart_module_disable(uart_port_t uart_num)209 static void uart_module_disable(uart_port_t uart_num)
210 {
211 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
212 if (uart_context[uart_num].hw_enabled != false) {
213 if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM ) {
214 periph_module_disable(uart_periph_signal[uart_num].module);
215 }
216 uart_context[uart_num].hw_enabled = false;
217 }
218 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
219 }
220
uart_set_word_length(uart_port_t uart_num,uart_word_length_t data_bit)221 esp_err_t uart_set_word_length(uart_port_t uart_num, uart_word_length_t data_bit)
222 {
223 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
224 UART_CHECK((data_bit < UART_DATA_BITS_MAX), "data bit error", ESP_FAIL);
225 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
226 uart_hal_set_data_bit_num(&(uart_context[uart_num].hal), data_bit);
227 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
228 return ESP_OK;
229 }
230
uart_get_word_length(uart_port_t uart_num,uart_word_length_t * data_bit)231 esp_err_t uart_get_word_length(uart_port_t uart_num, uart_word_length_t* data_bit)
232 {
233 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
234 uart_hal_get_data_bit_num(&(uart_context[uart_num].hal), data_bit);
235 return ESP_OK;
236 }
237
uart_set_stop_bits(uart_port_t uart_num,uart_stop_bits_t stop_bit)238 esp_err_t uart_set_stop_bits(uart_port_t uart_num, uart_stop_bits_t stop_bit)
239 {
240 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
241 UART_CHECK((stop_bit < UART_STOP_BITS_MAX), "stop bit error", ESP_FAIL);
242 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
243 uart_hal_set_stop_bits(&(uart_context[uart_num].hal), stop_bit);
244 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
245 return ESP_OK;
246 }
247
uart_get_stop_bits(uart_port_t uart_num,uart_stop_bits_t * stop_bit)248 esp_err_t uart_get_stop_bits(uart_port_t uart_num, uart_stop_bits_t* stop_bit)
249 {
250 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
251 uart_hal_get_stop_bits(&(uart_context[uart_num].hal), stop_bit);
252 return ESP_OK;
253 }
254
uart_set_parity(uart_port_t uart_num,uart_parity_t parity_mode)255 esp_err_t uart_set_parity(uart_port_t uart_num, uart_parity_t parity_mode)
256 {
257 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
258 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
259 uart_hal_set_parity(&(uart_context[uart_num].hal), parity_mode);
260 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
261 return ESP_OK;
262 }
263
uart_get_parity(uart_port_t uart_num,uart_parity_t * parity_mode)264 esp_err_t uart_get_parity(uart_port_t uart_num, uart_parity_t* parity_mode)
265 {
266 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
267 uart_hal_get_parity(&(uart_context[uart_num].hal), parity_mode);
268 return ESP_OK;
269 }
270
uart_set_baudrate(uart_port_t uart_num,uint32_t baud_rate)271 esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baud_rate)
272 {
273 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
274 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
275 uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate);
276 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
277 return ESP_OK;
278 }
279
uart_get_baudrate(uart_port_t uart_num,uint32_t * baudrate)280 esp_err_t uart_get_baudrate(uart_port_t uart_num, uint32_t *baudrate)
281 {
282 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
283 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
284 uart_hal_get_baudrate(&(uart_context[uart_num].hal), baudrate);
285 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
286 return ESP_OK;
287 }
288
uart_set_line_inverse(uart_port_t uart_num,uint32_t inverse_mask)289 esp_err_t uart_set_line_inverse(uart_port_t uart_num, uint32_t inverse_mask)
290 {
291 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
292 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
293 uart_hal_inverse_signal(&(uart_context[uart_num].hal), inverse_mask);
294 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
295 return ESP_OK;
296 }
297
uart_set_sw_flow_ctrl(uart_port_t uart_num,bool enable,uint8_t rx_thresh_xon,uint8_t rx_thresh_xoff)298 esp_err_t uart_set_sw_flow_ctrl(uart_port_t uart_num, bool enable, uint8_t rx_thresh_xon, uint8_t rx_thresh_xoff)
299 {
300 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
301 UART_CHECK((rx_thresh_xon < SOC_UART_FIFO_LEN), "rx flow xon thresh error", ESP_FAIL);
302 UART_CHECK((rx_thresh_xoff < SOC_UART_FIFO_LEN), "rx flow xon thresh error", ESP_FAIL);
303 uart_sw_flowctrl_t sw_flow_ctl = {
304 .xon_char = XON,
305 .xoff_char = XOFF,
306 .xon_thrd = rx_thresh_xon,
307 .xoff_thrd = rx_thresh_xoff,
308 };
309 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
310 uart_hal_set_sw_flow_ctrl(&(uart_context[uart_num].hal), &sw_flow_ctl, enable);
311 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
312 return ESP_OK;
313 }
314
uart_set_hw_flow_ctrl(uart_port_t uart_num,uart_hw_flowcontrol_t flow_ctrl,uint8_t rx_thresh)315 esp_err_t uart_set_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t flow_ctrl, uint8_t rx_thresh)
316 {
317 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
318 UART_CHECK((rx_thresh < SOC_UART_FIFO_LEN), "rx flow thresh error", ESP_FAIL);
319 UART_CHECK((flow_ctrl < UART_HW_FLOWCTRL_MAX), "hw_flowctrl mode error", ESP_FAIL);
320 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
321 uart_hal_set_hw_flow_ctrl(&(uart_context[uart_num].hal), flow_ctrl, rx_thresh);
322 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
323 return ESP_OK;
324 }
325
uart_get_hw_flow_ctrl(uart_port_t uart_num,uart_hw_flowcontrol_t * flow_ctrl)326 esp_err_t uart_get_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t* flow_ctrl)
327 {
328 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL)
329 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
330 uart_hal_get_hw_flow_ctrl(&(uart_context[uart_num].hal), flow_ctrl);
331 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
332 return ESP_OK;
333 }
334
uart_clear_intr_status(uart_port_t uart_num,uint32_t clr_mask)335 esp_err_t UART_ISR_ATTR uart_clear_intr_status(uart_port_t uart_num, uint32_t clr_mask)
336 {
337 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
338 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), clr_mask);
339 return ESP_OK;
340 }
341
uart_enable_intr_mask(uart_port_t uart_num,uint32_t enable_mask)342 esp_err_t uart_enable_intr_mask(uart_port_t uart_num, uint32_t enable_mask)
343 {
344 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
345 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
346 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), enable_mask);
347 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), enable_mask);
348 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
349 return ESP_OK;
350 }
351
uart_disable_intr_mask(uart_port_t uart_num,uint32_t disable_mask)352 esp_err_t uart_disable_intr_mask(uart_port_t uart_num, uint32_t disable_mask)
353 {
354 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
355 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
356 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), disable_mask);
357 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
358 return ESP_OK;
359 }
360
uart_pattern_link_free(uart_port_t uart_num)361 static esp_err_t uart_pattern_link_free(uart_port_t uart_num)
362 {
363 if (p_uart_obj[uart_num]->rx_pattern_pos.data != NULL) {
364 int* pdata = p_uart_obj[uart_num]->rx_pattern_pos.data;
365 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
366 p_uart_obj[uart_num]->rx_pattern_pos.data = NULL;
367 p_uart_obj[uart_num]->rx_pattern_pos.wr = 0;
368 p_uart_obj[uart_num]->rx_pattern_pos.rd = 0;
369 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
370 free(pdata);
371 }
372 return ESP_OK;
373 }
374
uart_pattern_enqueue(uart_port_t uart_num,int pos)375 static esp_err_t UART_ISR_ATTR uart_pattern_enqueue(uart_port_t uart_num, int pos)
376 {
377 esp_err_t ret = ESP_OK;
378 uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
379 int next = p_pos->wr + 1;
380 if (next >= p_pos->len) {
381 next = 0;
382 }
383 if (next == p_pos->rd) {
384 ESP_EARLY_LOGW(UART_TAG, "Fail to enqueue pattern position, pattern queue is full.");
385 ret = ESP_FAIL;
386 } else {
387 p_pos->data[p_pos->wr] = pos;
388 p_pos->wr = next;
389 ret = ESP_OK;
390 }
391 return ret;
392 }
393
uart_pattern_dequeue(uart_port_t uart_num)394 static esp_err_t uart_pattern_dequeue(uart_port_t uart_num)
395 {
396 if(p_uart_obj[uart_num]->rx_pattern_pos.data == NULL) {
397 return ESP_ERR_INVALID_STATE;
398 } else {
399 esp_err_t ret = ESP_OK;
400 uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
401 if (p_pos->rd == p_pos->wr) {
402 ret = ESP_FAIL;
403 } else {
404 p_pos->rd++;
405 }
406 if (p_pos->rd >= p_pos->len) {
407 p_pos->rd = 0;
408 }
409 return ret;
410 }
411 }
412
uart_pattern_queue_update(uart_port_t uart_num,int diff_len)413 static esp_err_t uart_pattern_queue_update(uart_port_t uart_num, int diff_len)
414 {
415 uart_pat_rb_t* p_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
416 int rd = p_pos->rd;
417 while(rd != p_pos->wr) {
418 p_pos->data[rd] -= diff_len;
419 int rd_rec = rd;
420 rd ++;
421 if (rd >= p_pos->len) {
422 rd = 0;
423 }
424 if (p_pos->data[rd_rec] < 0) {
425 p_pos->rd = rd;
426 }
427 }
428 return ESP_OK;
429 }
430
uart_pattern_pop_pos(uart_port_t uart_num)431 int uart_pattern_pop_pos(uart_port_t uart_num)
432 {
433 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
434 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
435 uart_pat_rb_t* pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
436 int pos = -1;
437 if (pat_pos != NULL && pat_pos->rd != pat_pos->wr) {
438 pos = pat_pos->data[pat_pos->rd];
439 uart_pattern_dequeue(uart_num);
440 }
441 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
442 return pos;
443 }
444
uart_pattern_get_pos(uart_port_t uart_num)445 int uart_pattern_get_pos(uart_port_t uart_num)
446 {
447 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
448 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
449 uart_pat_rb_t* pat_pos = &p_uart_obj[uart_num]->rx_pattern_pos;
450 int pos = -1;
451 if (pat_pos != NULL && pat_pos->rd != pat_pos->wr) {
452 pos = pat_pos->data[pat_pos->rd];
453 }
454 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
455 return pos;
456 }
457
uart_pattern_queue_reset(uart_port_t uart_num,int queue_length)458 esp_err_t uart_pattern_queue_reset(uart_port_t uart_num, int queue_length)
459 {
460 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
461 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_ERR_INVALID_STATE);
462
463 int* pdata = (int*) malloc(queue_length * sizeof(int));
464 if(pdata == NULL) {
465 return ESP_ERR_NO_MEM;
466 }
467 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
468 int* ptmp = p_uart_obj[uart_num]->rx_pattern_pos.data;
469 p_uart_obj[uart_num]->rx_pattern_pos.data = pdata;
470 p_uart_obj[uart_num]->rx_pattern_pos.len = queue_length;
471 p_uart_obj[uart_num]->rx_pattern_pos.rd = 0;
472 p_uart_obj[uart_num]->rx_pattern_pos.wr = 0;
473 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
474 free(ptmp);
475 return ESP_OK;
476 }
477
478 #if CONFIG_IDF_TARGET_ESP32
uart_enable_pattern_det_intr(uart_port_t uart_num,char pattern_chr,uint8_t chr_num,int chr_tout,int post_idle,int pre_idle)479 esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle)
480 {
481 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
482 UART_CHECK(chr_tout >= 0 && chr_tout <= UART_RX_GAP_TOUT_V, "uart pattern set error\n", ESP_FAIL);
483 UART_CHECK(post_idle >= 0 && post_idle <= UART_POST_IDLE_NUM_V, "uart pattern set error\n", ESP_FAIL);
484 UART_CHECK(pre_idle >= 0 && pre_idle <= UART_PRE_IDLE_NUM_V, "uart pattern set error\n", ESP_FAIL);
485 uart_at_cmd_t at_cmd = {0};
486 at_cmd.cmd_char = pattern_chr;
487 at_cmd.char_num = chr_num;
488 at_cmd.gap_tout = chr_tout;
489 at_cmd.pre_idle = pre_idle;
490 at_cmd.post_idle = post_idle;
491 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET);
492 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
493 uart_hal_set_at_cmd_char(&(uart_context[uart_num].hal), &at_cmd);
494 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET);
495 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
496 return ESP_OK;
497 }
498 #endif
499
uart_enable_pattern_det_baud_intr(uart_port_t uart_num,char pattern_chr,uint8_t chr_num,int chr_tout,int post_idle,int pre_idle)500 esp_err_t uart_enable_pattern_det_baud_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle)
501 {
502 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
503 UART_CHECK(chr_tout >= 0 && chr_tout <= UART_RX_GAP_TOUT_V, "uart pattern set error\n", ESP_FAIL);
504 UART_CHECK(post_idle >= 0 && post_idle <= UART_POST_IDLE_NUM_V, "uart pattern set error\n", ESP_FAIL);
505 UART_CHECK(pre_idle >= 0 && pre_idle <= UART_PRE_IDLE_NUM_V, "uart pattern set error\n", ESP_FAIL);
506 uart_at_cmd_t at_cmd = {0};
507 at_cmd.cmd_char = pattern_chr;
508 at_cmd.char_num = chr_num;
509
510 #if CONFIG_IDF_TARGET_ESP32
511 int apb_clk_freq = 0;
512 uint32_t uart_baud = 0;
513 uint32_t uart_div = 0;
514 uart_get_baudrate(uart_num, &uart_baud);
515 apb_clk_freq = esp_clk_apb_freq();
516 uart_div = apb_clk_freq / uart_baud;
517
518 at_cmd.gap_tout = chr_tout * uart_div;
519 at_cmd.pre_idle = pre_idle * uart_div;
520 at_cmd.post_idle = post_idle * uart_div;
521 #elif CONFIG_IDF_TARGET_ESP32S2
522 at_cmd.gap_tout = chr_tout;
523 at_cmd.pre_idle = pre_idle;
524 at_cmd.post_idle = post_idle;
525 #endif
526 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET);
527 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
528 uart_hal_set_at_cmd_char(&(uart_context[uart_num].hal), &at_cmd);
529 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET);
530 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
531 return ESP_OK;
532 }
533
534
uart_disable_pattern_det_intr(uart_port_t uart_num)535 esp_err_t uart_disable_pattern_det_intr(uart_port_t uart_num)
536 {
537 return uart_disable_intr_mask(uart_num, UART_INTR_CMD_CHAR_DET);
538 }
539
uart_enable_rx_intr(uart_port_t uart_num)540 esp_err_t uart_enable_rx_intr(uart_port_t uart_num)
541 {
542 return uart_enable_intr_mask(uart_num, UART_INTR_RXFIFO_FULL|UART_INTR_RXFIFO_TOUT);
543 }
544
uart_disable_rx_intr(uart_port_t uart_num)545 esp_err_t uart_disable_rx_intr(uart_port_t uart_num)
546 {
547 return uart_disable_intr_mask(uart_num, UART_INTR_RXFIFO_FULL|UART_INTR_RXFIFO_TOUT);
548 }
549
uart_disable_tx_intr(uart_port_t uart_num)550 esp_err_t uart_disable_tx_intr(uart_port_t uart_num)
551 {
552 return uart_disable_intr_mask(uart_num, UART_INTR_TXFIFO_EMPTY);
553 }
554
uart_enable_tx_intr(uart_port_t uart_num,int enable,int thresh)555 esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh)
556 {
557 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
558 UART_CHECK((thresh < SOC_UART_FIFO_LEN), "empty intr threshold error", ESP_FAIL);
559 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
560 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
561 uart_hal_set_txfifo_empty_thr(&(uart_context[uart_num].hal), thresh);
562 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
563 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
564 return ESP_OK;
565 }
566
uart_isr_register(uart_port_t uart_num,void (* fn)(void *),void * arg,int intr_alloc_flags,uart_isr_handle_t * handle)567 esp_err_t uart_isr_register(uart_port_t uart_num, void (*fn)(void*), void * arg, int intr_alloc_flags, uart_isr_handle_t *handle)
568 {
569 int ret;
570 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
571 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
572 ret=esp_intr_alloc(uart_periph_signal[uart_num].irq, intr_alloc_flags, fn, arg, handle);
573 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
574 return ret;
575 }
576
uart_isr_free(uart_port_t uart_num)577 esp_err_t uart_isr_free(uart_port_t uart_num)
578 {
579 esp_err_t ret;
580 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
581 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
582 UART_CHECK((p_uart_obj[uart_num]->intr_handle != NULL), "uart driver error", ESP_ERR_INVALID_ARG);
583 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
584 ret=esp_intr_free(p_uart_obj[uart_num]->intr_handle);
585 p_uart_obj[uart_num]->intr_handle=NULL;
586 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
587 return ret;
588 }
589
590 //internal signal can be output to multiple GPIO pads
591 //only one GPIO pad can connect with input signal
uart_set_pin(uart_port_t uart_num,int tx_io_num,int rx_io_num,int rts_io_num,int cts_io_num)592 esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int rts_io_num, int cts_io_num)
593 {
594 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
595 UART_CHECK((tx_io_num < 0 || (GPIO_IS_VALID_OUTPUT_GPIO(tx_io_num))), "tx_io_num error", ESP_FAIL);
596 UART_CHECK((rx_io_num < 0 || (GPIO_IS_VALID_GPIO(rx_io_num))), "rx_io_num error", ESP_FAIL);
597 UART_CHECK((rts_io_num < 0 || (GPIO_IS_VALID_OUTPUT_GPIO(rts_io_num))), "rts_io_num error", ESP_FAIL);
598 UART_CHECK((cts_io_num < 0 || (GPIO_IS_VALID_GPIO(cts_io_num))), "cts_io_num error", ESP_FAIL);
599
600 if(tx_io_num >= 0) {
601 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[tx_io_num], PIN_FUNC_GPIO);
602 gpio_set_level(tx_io_num, 1);
603 esp_rom_gpio_connect_out_signal(tx_io_num, uart_periph_signal[uart_num].tx_sig, 0, 0);
604 }
605 if(rx_io_num >= 0) {
606 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rx_io_num], PIN_FUNC_GPIO);
607 gpio_set_pull_mode(rx_io_num, GPIO_PULLUP_ONLY);
608 gpio_set_direction(rx_io_num, GPIO_MODE_INPUT);
609 esp_rom_gpio_connect_in_signal(rx_io_num, uart_periph_signal[uart_num].rx_sig, 0);
610 }
611 if(rts_io_num >= 0) {
612 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rts_io_num], PIN_FUNC_GPIO);
613 gpio_set_direction(rts_io_num, GPIO_MODE_OUTPUT);
614 esp_rom_gpio_connect_out_signal(rts_io_num, uart_periph_signal[uart_num].rts_sig, 0, 0);
615 }
616 if(cts_io_num >= 0) {
617 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cts_io_num], PIN_FUNC_GPIO);
618 gpio_set_pull_mode(cts_io_num, GPIO_PULLUP_ONLY);
619 gpio_set_direction(cts_io_num, GPIO_MODE_INPUT);
620 esp_rom_gpio_connect_in_signal(cts_io_num, uart_periph_signal[uart_num].cts_sig, 0);
621 }
622 return ESP_OK;
623 }
624
uart_set_rts(uart_port_t uart_num,int level)625 esp_err_t uart_set_rts(uart_port_t uart_num, int level)
626 {
627 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
628 UART_CHECK((!uart_hal_is_hw_rts_en(&(uart_context[uart_num].hal))), "disable hw flowctrl before using sw control", ESP_FAIL);
629 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
630 uart_hal_set_rts(&(uart_context[uart_num].hal), level);
631 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
632 return ESP_OK;
633 }
634
uart_set_dtr(uart_port_t uart_num,int level)635 esp_err_t uart_set_dtr(uart_port_t uart_num, int level)
636 {
637 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
638 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
639 uart_hal_set_dtr(&(uart_context[uart_num].hal), level);
640 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
641 return ESP_OK;
642 }
643
uart_set_tx_idle_num(uart_port_t uart_num,uint16_t idle_num)644 esp_err_t uart_set_tx_idle_num(uart_port_t uart_num, uint16_t idle_num)
645 {
646 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
647 UART_CHECK((idle_num <= UART_TX_IDLE_NUM_V), "uart idle num error", ESP_FAIL);
648 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
649 uart_hal_set_tx_idle_num(&(uart_context[uart_num].hal), idle_num);
650 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
651 return ESP_OK;
652 }
653
uart_param_config(uart_port_t uart_num,const uart_config_t * uart_config)654 esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_config)
655 {
656 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
657 UART_CHECK((uart_config), "param null", ESP_FAIL);
658 UART_CHECK((uart_config->rx_flow_ctrl_thresh < SOC_UART_FIFO_LEN), "rx flow thresh error", ESP_FAIL);
659 UART_CHECK((uart_config->flow_ctrl < UART_HW_FLOWCTRL_MAX), "hw_flowctrl mode error", ESP_FAIL);
660 UART_CHECK((uart_config->data_bits < UART_DATA_BITS_MAX), "data bit error", ESP_FAIL);
661 uart_module_enable(uart_num);
662 #if SOC_UART_SUPPORT_RTC_CLK
663 if (uart_config->source_clk == UART_SCLK_RTC) {
664 rtc_clk_enable(uart_num);
665 }
666 #endif
667 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
668 uart_hal_init(&(uart_context[uart_num].hal), uart_num);
669 uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_config->source_clk);
670 uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate);
671 uart_hal_set_parity(&(uart_context[uart_num].hal), uart_config->parity);
672 uart_hal_set_data_bit_num(&(uart_context[uart_num].hal), uart_config->data_bits);
673 uart_hal_set_stop_bits(&(uart_context[uart_num].hal), uart_config->stop_bits);
674 uart_hal_set_tx_idle_num(&(uart_context[uart_num].hal), UART_TX_IDLE_NUM_DEFAULT);
675 uart_hal_set_hw_flow_ctrl(&(uart_context[uart_num].hal), uart_config->flow_ctrl, uart_config->rx_flow_ctrl_thresh);
676 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
677 uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
678 uart_hal_txfifo_rst(&(uart_context[uart_num].hal));
679 return ESP_OK;
680 }
681
uart_intr_config(uart_port_t uart_num,const uart_intr_config_t * intr_conf)682 esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_conf)
683 {
684 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
685 UART_CHECK((intr_conf), "param null", ESP_FAIL);
686 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
687 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
688 if(intr_conf->intr_enable_mask & UART_INTR_RXFIFO_TOUT) {
689 uart_hal_set_rx_timeout(&(uart_context[uart_num].hal), intr_conf->rx_timeout_thresh);
690 } else {
691 //Disable rx_tout intr
692 uart_hal_set_rx_timeout(&(uart_context[uart_num].hal), 0);
693 }
694 if(intr_conf->intr_enable_mask & UART_INTR_RXFIFO_FULL) {
695 uart_hal_set_rxfifo_full_thr(&(uart_context[uart_num].hal), intr_conf->rxfifo_full_thresh);
696 }
697 if(intr_conf->intr_enable_mask & UART_INTR_TXFIFO_EMPTY) {
698 uart_hal_set_txfifo_empty_thr(&(uart_context[uart_num].hal), intr_conf->txfifo_empty_intr_thresh);
699 }
700 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), intr_conf->intr_enable_mask);
701 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
702 return ESP_OK;
703 }
704
uart_find_pattern_from_last(uint8_t * buf,int length,uint8_t pat_chr,uint8_t pat_num)705 static int UART_ISR_ATTR uart_find_pattern_from_last(uint8_t* buf, int length, uint8_t pat_chr, uint8_t pat_num)
706 {
707 int cnt = 0;
708 int len = length;
709 while (len >= 0) {
710 if (buf[len] == pat_chr) {
711 cnt++;
712 } else {
713 cnt = 0;
714 }
715 if (cnt >= pat_num) {
716 break;
717 }
718 len --;
719 }
720 return len;
721 }
722
723 //internal isr handler for default driver code.
uart_rx_intr_handler_default(void * param)724 static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
725 {
726 uart_obj_t *p_uart = (uart_obj_t*) param;
727 uint8_t uart_num = p_uart->uart_num;
728 int rx_fifo_len = 0;
729 uint32_t uart_intr_status = 0;
730 uart_event_t uart_event;
731 portBASE_TYPE HPTaskAwoken = 0;
732 static uint8_t pat_flg = 0;
733 while(1) {
734 // The `continue statement` may cause the interrupt to loop infinitely
735 // we exit the interrupt here
736 uart_intr_status = uart_hal_get_intsts_mask(&(uart_context[uart_num].hal));
737 //Exit form while loop
738 if(uart_intr_status == 0){
739 break;
740 }
741 uart_event.type = UART_EVENT_MAX;
742 if(uart_intr_status & UART_INTR_TXFIFO_EMPTY) {
743 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
744 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
745 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
746 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
747 if(p_uart->tx_waiting_brk) {
748 continue;
749 }
750 //TX semaphore will only be used when tx_buf_size is zero.
751 if(p_uart->tx_waiting_fifo == true && p_uart->tx_buf_size == 0) {
752 p_uart->tx_waiting_fifo = false;
753 xSemaphoreGiveFromISR(p_uart->tx_fifo_sem, &HPTaskAwoken);
754 } else {
755 //We don't use TX ring buffer, because the size is zero.
756 if(p_uart->tx_buf_size == 0) {
757 continue;
758 }
759 bool en_tx_flg = false;
760 uint32_t tx_fifo_rem = uart_hal_get_txfifo_len(&(uart_context[uart_num].hal));
761 //We need to put a loop here, in case all the buffer items are very short.
762 //That would cause a watch_dog reset because empty interrupt happens so often.
763 //Although this is a loop in ISR, this loop will execute at most 128 turns.
764 while(tx_fifo_rem) {
765 if(p_uart->tx_len_tot == 0 || p_uart->tx_ptr == NULL || p_uart->tx_len_cur == 0) {
766 size_t size;
767 p_uart->tx_head = (uart_tx_data_t*) xRingbufferReceiveFromISR(p_uart->tx_ring_buf, &size);
768 if(p_uart->tx_head) {
769 //The first item is the data description
770 //Get the first item to get the data information
771 if(p_uart->tx_len_tot == 0) {
772 p_uart->tx_ptr = NULL;
773 p_uart->tx_len_tot = p_uart->tx_head->tx_data.size;
774 if(p_uart->tx_head->type == UART_DATA_BREAK) {
775 p_uart->tx_brk_flg = 1;
776 p_uart->tx_brk_len = p_uart->tx_head->tx_data.brk_len;
777 }
778 //We have saved the data description from the 1st item, return buffer.
779 vRingbufferReturnItemFromISR(p_uart->tx_ring_buf, p_uart->tx_head, &HPTaskAwoken);
780 } else if(p_uart->tx_ptr == NULL) {
781 //Update the TX item pointer, we will need this to return item to buffer.
782 p_uart->tx_ptr = (uint8_t*)p_uart->tx_head;
783 en_tx_flg = true;
784 p_uart->tx_len_cur = size;
785 }
786 } else {
787 //Can not get data from ring buffer, return;
788 break;
789 }
790 }
791 if (p_uart->tx_len_tot > 0 && p_uart->tx_ptr && p_uart->tx_len_cur > 0) {
792 //To fill the TX FIFO.
793 uint32_t send_len = 0;
794 // Set RS485 RTS pin before transmission if the half duplex mode is enabled
795 if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)) {
796 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
797 uart_hal_set_rts(&(uart_context[uart_num].hal), 0);
798 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
799 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
800 }
801 uart_hal_write_txfifo(&(uart_context[uart_num].hal),
802 (const uint8_t *)p_uart->tx_ptr,
803 (p_uart->tx_len_cur > tx_fifo_rem) ? tx_fifo_rem : p_uart->tx_len_cur,
804 &send_len);
805 p_uart->tx_ptr += send_len;
806 p_uart->tx_len_tot -= send_len;
807 p_uart->tx_len_cur -= send_len;
808 tx_fifo_rem -= send_len;
809 if (p_uart->tx_len_cur == 0) {
810 //Return item to ring buffer.
811 vRingbufferReturnItemFromISR(p_uart->tx_ring_buf, p_uart->tx_head, &HPTaskAwoken);
812 p_uart->tx_head = NULL;
813 p_uart->tx_ptr = NULL;
814 //Sending item done, now we need to send break if there is a record.
815 //Set TX break signal after FIFO is empty
816 if(p_uart->tx_len_tot == 0 && p_uart->tx_brk_flg == 1) {
817 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
818 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
819 uart_hal_tx_break(&(uart_context[uart_num].hal), p_uart->tx_brk_len);
820 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
821 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
822 p_uart->tx_waiting_brk = 1;
823 //do not enable TX empty interrupt
824 en_tx_flg = false;
825 } else {
826 //enable TX empty interrupt
827 en_tx_flg = true;
828 }
829 } else {
830 //enable TX empty interrupt
831 en_tx_flg = true;
832 }
833 }
834 }
835 if (en_tx_flg) {
836 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
837 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
838 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
839 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
840 }
841 }
842 }
843 else if ((uart_intr_status & UART_INTR_RXFIFO_TOUT)
844 || (uart_intr_status & UART_INTR_RXFIFO_FULL)
845 || (uart_intr_status & UART_INTR_CMD_CHAR_DET)
846 ) {
847 if(pat_flg == 1) {
848 uart_intr_status |= UART_INTR_CMD_CHAR_DET;
849 pat_flg = 0;
850 }
851 if (p_uart->rx_buffer_full_flg == false) {
852 rx_fifo_len = uart_hal_get_rxfifo_len(&(uart_context[uart_num].hal));
853 if ((p_uart_obj[uart_num]->rx_always_timeout_flg) && !(uart_intr_status & UART_INTR_RXFIFO_TOUT)) {
854 rx_fifo_len--; // leave one byte in the fifo in order to trigger uart_intr_rxfifo_tout
855 }
856 uart_hal_read_rxfifo(&(uart_context[uart_num].hal), p_uart->rx_data_buf, &rx_fifo_len);
857 uint8_t pat_chr = 0;
858 uint8_t pat_num = 0;
859 int pat_idx = -1;
860 uart_hal_get_at_cmd_char(&(uart_context[uart_num].hal), &pat_chr, &pat_num);
861
862 //Get the buffer from the FIFO
863 if (uart_intr_status & UART_INTR_CMD_CHAR_DET) {
864 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET);
865 uart_event.type = UART_PATTERN_DET;
866 uart_event.size = rx_fifo_len;
867 pat_idx = uart_find_pattern_from_last(p_uart->rx_data_buf, rx_fifo_len - 1, pat_chr, pat_num);
868 } else {
869 //After Copying the Data From FIFO ,Clear intr_status
870 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_TOUT | UART_INTR_RXFIFO_FULL);
871 uart_event.type = UART_DATA;
872 uart_event.size = rx_fifo_len;
873 uart_event.timeout_flag = (uart_intr_status & UART_INTR_RXFIFO_TOUT) ? true : false;
874 UART_ENTER_CRITICAL_ISR(&uart_selectlock);
875 if (p_uart->uart_select_notif_callback) {
876 p_uart->uart_select_notif_callback(uart_num, UART_SELECT_READ_NOTIF, &HPTaskAwoken);
877 }
878 UART_EXIT_CRITICAL_ISR(&uart_selectlock);
879 }
880 p_uart->rx_stash_len = rx_fifo_len;
881 //If we fail to push data to ring buffer, we will have to stash the data, and send next time.
882 //Mainly for applications that uses flow control or small ring buffer.
883 if(pdFALSE == xRingbufferSendFromISR(p_uart->rx_ring_buf, p_uart->rx_data_buf, p_uart->rx_stash_len, &HPTaskAwoken)) {
884 p_uart->rx_buffer_full_flg = true;
885 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
886 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_TOUT | UART_INTR_RXFIFO_FULL);
887 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
888 if (uart_event.type == UART_PATTERN_DET) {
889 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
890 if (rx_fifo_len < pat_num) {
891 //some of the characters are read out in last interrupt
892 uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len - (pat_num - rx_fifo_len));
893 } else {
894 uart_pattern_enqueue(uart_num,
895 pat_idx <= -1 ?
896 //can not find the pattern in buffer,
897 p_uart->rx_buffered_len + p_uart->rx_stash_len :
898 // find the pattern in buffer
899 p_uart->rx_buffered_len + pat_idx);
900 }
901 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
902 if ((p_uart->xQueueUart != NULL) && (pdFALSE == xQueueSendFromISR(p_uart->xQueueUart, (void * )&uart_event, &HPTaskAwoken))) {
903 ESP_EARLY_LOGV(UART_TAG, "UART event queue full");
904 }
905 }
906 uart_event.type = UART_BUFFER_FULL;
907 } else {
908 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
909 if (uart_intr_status & UART_INTR_CMD_CHAR_DET) {
910 if (rx_fifo_len < pat_num) {
911 //some of the characters are read out in last interrupt
912 uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len - (pat_num - rx_fifo_len));
913 } else if(pat_idx >= 0) {
914 // find the pattern in stash buffer.
915 uart_pattern_enqueue(uart_num, p_uart->rx_buffered_len + pat_idx);
916 }
917 }
918 p_uart->rx_buffered_len += p_uart->rx_stash_len;
919 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
920 }
921 } else {
922 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
923 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT);
924 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
925 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_TOUT);
926 if(uart_intr_status & UART_INTR_CMD_CHAR_DET) {
927 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET);
928 uart_event.type = UART_PATTERN_DET;
929 uart_event.size = rx_fifo_len;
930 pat_flg = 1;
931 }
932 }
933 } else if(uart_intr_status & UART_INTR_RXFIFO_OVF) {
934 // When fifo overflows, we reset the fifo.
935 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
936 uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
937 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
938 UART_ENTER_CRITICAL_ISR(&uart_selectlock);
939 if (p_uart->uart_select_notif_callback) {
940 p_uart->uart_select_notif_callback(uart_num, UART_SELECT_ERROR_NOTIF, &HPTaskAwoken);
941 }
942 UART_EXIT_CRITICAL_ISR(&uart_selectlock);
943 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_OVF);
944 uart_event.type = UART_FIFO_OVF;
945 } else if(uart_intr_status & UART_INTR_BRK_DET) {
946 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_BRK_DET);
947 uart_event.type = UART_BREAK;
948 } else if(uart_intr_status & UART_INTR_FRAM_ERR) {
949 UART_ENTER_CRITICAL_ISR(&uart_selectlock);
950 if (p_uart->uart_select_notif_callback) {
951 p_uart->uart_select_notif_callback(uart_num, UART_SELECT_ERROR_NOTIF, &HPTaskAwoken);
952 }
953 UART_EXIT_CRITICAL_ISR(&uart_selectlock);
954 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_FRAM_ERR);
955 uart_event.type = UART_FRAME_ERR;
956 } else if(uart_intr_status & UART_INTR_PARITY_ERR) {
957 UART_ENTER_CRITICAL_ISR(&uart_selectlock);
958 if (p_uart->uart_select_notif_callback) {
959 p_uart->uart_select_notif_callback(uart_num, UART_SELECT_ERROR_NOTIF, &HPTaskAwoken);
960 }
961 UART_EXIT_CRITICAL_ISR(&uart_selectlock);
962 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_PARITY_ERR);
963 uart_event.type = UART_PARITY_ERR;
964 } else if(uart_intr_status & UART_INTR_TX_BRK_DONE) {
965 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
966 uart_hal_tx_break(&(uart_context[uart_num].hal), 0);
967 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
968 if(p_uart->tx_brk_flg == 1) {
969 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY);
970 }
971 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
972 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
973 if(p_uart->tx_brk_flg == 1) {
974 p_uart->tx_brk_flg = 0;
975 p_uart->tx_waiting_brk = 0;
976 } else {
977 xSemaphoreGiveFromISR(p_uart->tx_brk_sem, &HPTaskAwoken);
978 }
979 } else if(uart_intr_status & UART_INTR_TX_BRK_IDLE) {
980 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
981 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_IDLE);
982 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
983 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_IDLE);
984 } else if(uart_intr_status & UART_INTR_CMD_CHAR_DET) {
985 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET);
986 uart_event.type = UART_PATTERN_DET;
987 } else if ((uart_intr_status & UART_INTR_RS485_PARITY_ERR)
988 || (uart_intr_status & UART_INTR_RS485_FRM_ERR)
989 || (uart_intr_status & UART_INTR_RS485_CLASH)) {
990 // RS485 collision or frame error interrupt triggered
991 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
992 uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
993 // Set collision detection flag
994 p_uart_obj[uart_num]->coll_det_flg = true;
995 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
996 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_RS485_CLASH | UART_INTR_RS485_FRM_ERR | UART_INTR_RS485_PARITY_ERR);
997 uart_event.type = UART_EVENT_MAX;
998 } else if(uart_intr_status & UART_INTR_TX_DONE) {
999 if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX) && uart_hal_is_tx_idle(&(uart_context[uart_num].hal)) != true) {
1000 // The TX_DONE interrupt is triggered but transmit is active
1001 // then postpone interrupt processing for next interrupt
1002 uart_event.type = UART_EVENT_MAX;
1003 } else {
1004 // Workaround for RS485: If the RS485 half duplex mode is active
1005 // and transmitter is in idle state then reset received buffer and reset RTS pin
1006 // skip this behavior for other UART modes
1007 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
1008 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
1009 if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)) {
1010 uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
1011 uart_hal_set_rts(&(uart_context[uart_num].hal), 1);
1012 }
1013 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
1014 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
1015 xSemaphoreGiveFromISR(p_uart_obj[uart_num]->tx_done_sem, &HPTaskAwoken);
1016 }
1017 } else {
1018 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), uart_intr_status); /*simply clear all other intr status*/
1019 uart_event.type = UART_EVENT_MAX;
1020 }
1021
1022 if(uart_event.type != UART_EVENT_MAX && p_uart->xQueueUart) {
1023 if (pdFALSE == xQueueSendFromISR(p_uart->xQueueUart, (void * )&uart_event, &HPTaskAwoken)) {
1024 ESP_EARLY_LOGV(UART_TAG, "UART event queue full");
1025 }
1026 }
1027 }
1028 if(HPTaskAwoken == pdTRUE) {
1029 portYIELD_FROM_ISR();
1030 }
1031 }
1032
1033 /**************************************************************/
uart_wait_tx_done(uart_port_t uart_num,TickType_t ticks_to_wait)1034 esp_err_t uart_wait_tx_done(uart_port_t uart_num, TickType_t ticks_to_wait)
1035 {
1036 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
1037 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
1038 BaseType_t res;
1039 portTickType ticks_start = xTaskGetTickCount();
1040 //Take tx_mux
1041 res = xSemaphoreTake(p_uart_obj[uart_num]->tx_mux, (portTickType)ticks_to_wait);
1042 if(res == pdFALSE) {
1043 return ESP_ERR_TIMEOUT;
1044 }
1045 xSemaphoreTake(p_uart_obj[uart_num]->tx_done_sem, 0);
1046 if(uart_hal_is_tx_idle(&(uart_context[uart_num].hal))) {
1047 xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
1048 return ESP_OK;
1049 }
1050 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
1051 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1052 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
1053 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1054
1055 TickType_t ticks_end = xTaskGetTickCount();
1056 if (ticks_end - ticks_start > ticks_to_wait) {
1057 ticks_to_wait = 0;
1058 } else {
1059 ticks_to_wait = ticks_to_wait - (ticks_end - ticks_start);
1060 }
1061 //take 2nd tx_done_sem, wait given from ISR
1062 res = xSemaphoreTake(p_uart_obj[uart_num]->tx_done_sem, (portTickType)ticks_to_wait);
1063 if(res == pdFALSE) {
1064 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1065 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
1066 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1067 xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
1068 return ESP_ERR_TIMEOUT;
1069 }
1070 xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
1071 return ESP_OK;
1072 }
1073
uart_tx_chars(uart_port_t uart_num,const char * buffer,uint32_t len)1074 int uart_tx_chars(uart_port_t uart_num, const char* buffer, uint32_t len)
1075 {
1076 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1));
1077 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
1078 UART_CHECK(buffer, "buffer null", (-1));
1079 if(len == 0) {
1080 return 0;
1081 }
1082 int tx_len = 0;
1083 xSemaphoreTake(p_uart_obj[uart_num]->tx_mux, (portTickType)portMAX_DELAY);
1084 if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)) {
1085 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1086 uart_hal_set_rts(&(uart_context[uart_num].hal), 0);
1087 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
1088 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1089 }
1090 uart_hal_write_txfifo(&(uart_context[uart_num].hal), (const uint8_t*) buffer, len, (uint32_t *)&tx_len);
1091 xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
1092 return tx_len;
1093 }
1094
uart_tx_all(uart_port_t uart_num,const char * src,size_t size,bool brk_en,int brk_len)1095 static int uart_tx_all(uart_port_t uart_num, const char* src, size_t size, bool brk_en, int brk_len)
1096 {
1097 if(size == 0) {
1098 return 0;
1099 }
1100 size_t original_size = size;
1101
1102 //lock for uart_tx
1103 xSemaphoreTake(p_uart_obj[uart_num]->tx_mux, (portTickType)portMAX_DELAY);
1104 p_uart_obj[uart_num]->coll_det_flg = false;
1105 if(p_uart_obj[uart_num]->tx_buf_size > 0) {
1106 size_t max_size = xRingbufferGetMaxItemSize(p_uart_obj[uart_num]->tx_ring_buf);
1107 int offset = 0;
1108 uart_tx_data_t evt;
1109 evt.tx_data.size = size;
1110 evt.tx_data.brk_len = brk_len;
1111 if(brk_en) {
1112 evt.type = UART_DATA_BREAK;
1113 } else {
1114 evt.type = UART_DATA;
1115 }
1116 xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void*) &evt, sizeof(uart_tx_data_t), portMAX_DELAY);
1117 while(size > 0) {
1118 size_t send_size = size > max_size / 2 ? max_size / 2 : size;
1119 xRingbufferSend(p_uart_obj[uart_num]->tx_ring_buf, (void*) (src + offset), send_size, portMAX_DELAY);
1120 size -= send_size;
1121 offset += send_size;
1122 uart_enable_tx_intr(uart_num, 1, UART_EMPTY_THRESH_DEFAULT);
1123 }
1124 } else {
1125 while(size) {
1126 //semaphore for tx_fifo available
1127 if(pdTRUE == xSemaphoreTake(p_uart_obj[uart_num]->tx_fifo_sem, (portTickType)portMAX_DELAY)) {
1128 uint32_t sent = 0;
1129 if (UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)) {
1130 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1131 uart_hal_set_rts(&(uart_context[uart_num].hal), 0);
1132 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE);
1133 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1134 }
1135 uart_hal_write_txfifo(&(uart_context[uart_num].hal), (const uint8_t*)src, size, &sent);
1136 if(sent < size) {
1137 p_uart_obj[uart_num]->tx_waiting_fifo = true;
1138 uart_enable_tx_intr(uart_num, 1, UART_EMPTY_THRESH_DEFAULT);
1139 }
1140 size -= sent;
1141 src += sent;
1142 }
1143 }
1144 if(brk_en) {
1145 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
1146 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1147 uart_hal_tx_break(&(uart_context[uart_num].hal), brk_len);
1148 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE);
1149 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1150 xSemaphoreTake(p_uart_obj[uart_num]->tx_brk_sem, (portTickType)portMAX_DELAY);
1151 }
1152 xSemaphoreGive(p_uart_obj[uart_num]->tx_fifo_sem);
1153 }
1154 xSemaphoreGive(p_uart_obj[uart_num]->tx_mux);
1155 return original_size;
1156 }
1157
uart_write_bytes(uart_port_t uart_num,const void * src,size_t size)1158 int uart_write_bytes(uart_port_t uart_num, const void* src, size_t size)
1159 {
1160 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1));
1161 UART_CHECK((p_uart_obj[uart_num] != NULL), "uart driver error", (-1));
1162 UART_CHECK(src, "buffer null", (-1));
1163 return uart_tx_all(uart_num, src, size, 0, 0);
1164 }
1165
uart_write_bytes_with_break(uart_port_t uart_num,const void * src,size_t size,int brk_len)1166 int uart_write_bytes_with_break(uart_port_t uart_num, const void* src, size_t size, int brk_len)
1167 {
1168 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1));
1169 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
1170 UART_CHECK((size > 0), "uart size error", (-1));
1171 UART_CHECK((src), "uart data null", (-1));
1172 UART_CHECK((brk_len > 0 && brk_len < 256), "break_num error", (-1));
1173 return uart_tx_all(uart_num, src, size, 1, brk_len);
1174 }
1175
uart_check_buf_full(uart_port_t uart_num)1176 static bool uart_check_buf_full(uart_port_t uart_num)
1177 {
1178 if(p_uart_obj[uart_num]->rx_buffer_full_flg) {
1179 BaseType_t res = xRingbufferSend(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_data_buf, p_uart_obj[uart_num]->rx_stash_len, 1);
1180 if(res == pdTRUE) {
1181 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1182 p_uart_obj[uart_num]->rx_buffered_len += p_uart_obj[uart_num]->rx_stash_len;
1183 p_uart_obj[uart_num]->rx_buffer_full_flg = false;
1184 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1185 uart_enable_rx_intr(p_uart_obj[uart_num]->uart_num);
1186 return true;
1187 }
1188 }
1189 return false;
1190 }
1191
uart_read_bytes(uart_port_t uart_num,void * buf,uint32_t length,TickType_t ticks_to_wait)1192 int uart_read_bytes(uart_port_t uart_num, void* buf, uint32_t length, TickType_t ticks_to_wait)
1193 {
1194 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", (-1));
1195 UART_CHECK((buf), "uart data null", (-1));
1196 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", (-1));
1197 uint8_t* data = NULL;
1198 size_t size;
1199 size_t copy_len = 0;
1200 int len_tmp;
1201 if(xSemaphoreTake(p_uart_obj[uart_num]->rx_mux,(portTickType)ticks_to_wait) != pdTRUE) {
1202 return -1;
1203 }
1204 while(length) {
1205 if(p_uart_obj[uart_num]->rx_cur_remain == 0) {
1206 data = (uint8_t*) xRingbufferReceive(p_uart_obj[uart_num]->rx_ring_buf, &size, (portTickType) ticks_to_wait);
1207 if(data) {
1208 p_uart_obj[uart_num]->rx_head_ptr = data;
1209 p_uart_obj[uart_num]->rx_ptr = data;
1210 p_uart_obj[uart_num]->rx_cur_remain = size;
1211 } else {
1212 //When using dual cores, `rx_buffer_full_flg` may read and write on different cores at same time,
1213 //which may lose synchronization. So we also need to call `uart_check_buf_full` once when ringbuffer is empty
1214 //to solve the possible asynchronous issues.
1215 if(uart_check_buf_full(uart_num)) {
1216 //This condition will never be true if `uart_read_bytes`
1217 //and `uart_rx_intr_handler_default` are scheduled on the same core.
1218 continue;
1219 } else {
1220 xSemaphoreGive(p_uart_obj[uart_num]->rx_mux);
1221 return copy_len;
1222 }
1223 }
1224 }
1225 if(p_uart_obj[uart_num]->rx_cur_remain > length) {
1226 len_tmp = length;
1227 } else {
1228 len_tmp = p_uart_obj[uart_num]->rx_cur_remain;
1229 }
1230 memcpy((uint8_t *)buf + copy_len, p_uart_obj[uart_num]->rx_ptr, len_tmp);
1231 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1232 p_uart_obj[uart_num]->rx_buffered_len -= len_tmp;
1233 uart_pattern_queue_update(uart_num, len_tmp);
1234 p_uart_obj[uart_num]->rx_ptr += len_tmp;
1235 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1236 p_uart_obj[uart_num]->rx_cur_remain -= len_tmp;
1237 copy_len += len_tmp;
1238 length -= len_tmp;
1239 if(p_uart_obj[uart_num]->rx_cur_remain == 0) {
1240 vRingbufferReturnItem(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_head_ptr);
1241 p_uart_obj[uart_num]->rx_head_ptr = NULL;
1242 p_uart_obj[uart_num]->rx_ptr = NULL;
1243 uart_check_buf_full(uart_num);
1244 }
1245 }
1246
1247 xSemaphoreGive(p_uart_obj[uart_num]->rx_mux);
1248 return copy_len;
1249 }
1250
uart_get_buffered_data_len(uart_port_t uart_num,size_t * size)1251 esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t* size)
1252 {
1253 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
1254 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
1255 *size = p_uart_obj[uart_num]->rx_buffered_len;
1256 return ESP_OK;
1257 }
1258
1259 esp_err_t uart_flush(uart_port_t uart_num) __attribute__((alias("uart_flush_input")));
1260
uart_flush_input(uart_port_t uart_num)1261 esp_err_t uart_flush_input(uart_port_t uart_num)
1262 {
1263 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
1264 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
1265 uart_obj_t* p_uart = p_uart_obj[uart_num];
1266 uint8_t* data;
1267 size_t size;
1268
1269 //rx sem protect the ring buffer read related functions
1270 xSemaphoreTake(p_uart->rx_mux, (portTickType)portMAX_DELAY);
1271 uart_disable_rx_intr(p_uart_obj[uart_num]->uart_num);
1272 while(true) {
1273 if(p_uart->rx_head_ptr) {
1274 vRingbufferReturnItem(p_uart->rx_ring_buf, p_uart->rx_head_ptr);
1275 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1276 p_uart_obj[uart_num]->rx_buffered_len -= p_uart->rx_cur_remain;
1277 uart_pattern_queue_update(uart_num, p_uart->rx_cur_remain);
1278 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1279 p_uart->rx_ptr = NULL;
1280 p_uart->rx_cur_remain = 0;
1281 p_uart->rx_head_ptr = NULL;
1282 }
1283 data = (uint8_t*) xRingbufferReceive(p_uart->rx_ring_buf, &size, (portTickType) 0);
1284 if(data == NULL) {
1285 if( p_uart_obj[uart_num]->rx_buffered_len != 0 ) {
1286 ESP_LOGE(UART_TAG, "rx_buffered_len error");
1287 p_uart_obj[uart_num]->rx_buffered_len = 0;
1288 }
1289 //We also need to clear the `rx_buffer_full_flg` here.
1290 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1291 p_uart_obj[uart_num]->rx_buffer_full_flg = false;
1292 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1293 break;
1294 }
1295 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1296 p_uart_obj[uart_num]->rx_buffered_len -= size;
1297 uart_pattern_queue_update(uart_num, size);
1298 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1299 vRingbufferReturnItem(p_uart->rx_ring_buf, data);
1300 if(p_uart_obj[uart_num]->rx_buffer_full_flg) {
1301 BaseType_t res = xRingbufferSend(p_uart_obj[uart_num]->rx_ring_buf, p_uart_obj[uart_num]->rx_data_buf, p_uart_obj[uart_num]->rx_stash_len, 1);
1302 if(res == pdTRUE) {
1303 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1304 p_uart_obj[uart_num]->rx_buffered_len += p_uart_obj[uart_num]->rx_stash_len;
1305 p_uart_obj[uart_num]->rx_buffer_full_flg = false;
1306 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1307 }
1308 }
1309 }
1310 p_uart->rx_ptr = NULL;
1311 p_uart->rx_cur_remain = 0;
1312 p_uart->rx_head_ptr = NULL;
1313 uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
1314 uart_enable_rx_intr(p_uart_obj[uart_num]->uart_num);
1315 xSemaphoreGive(p_uart->rx_mux);
1316 return ESP_OK;
1317 }
1318
uart_driver_install(uart_port_t uart_num,int rx_buffer_size,int tx_buffer_size,int queue_size,QueueHandle_t * uart_queue,int intr_alloc_flags)1319 esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_buffer_size, int queue_size, QueueHandle_t *uart_queue, int intr_alloc_flags)
1320 {
1321 esp_err_t r;
1322 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
1323 UART_CHECK((rx_buffer_size > SOC_UART_FIFO_LEN), "uart rx buffer length error", ESP_FAIL);
1324 UART_CHECK((tx_buffer_size > SOC_UART_FIFO_LEN) || (tx_buffer_size == 0), "uart tx buffer length error", ESP_FAIL);
1325 #if CONFIG_UART_ISR_IN_IRAM
1326 if ((intr_alloc_flags & ESP_INTR_FLAG_IRAM) == 0) {
1327 ESP_LOGI(UART_TAG, "ESP_INTR_FLAG_IRAM flag not set while CONFIG_UART_ISR_IN_IRAM is enabled, flag updated");
1328 intr_alloc_flags |= ESP_INTR_FLAG_IRAM;
1329 }
1330 #else
1331 if ((intr_alloc_flags & ESP_INTR_FLAG_IRAM) != 0) {
1332 ESP_LOGW(UART_TAG, "ESP_INTR_FLAG_IRAM flag is set while CONFIG_UART_ISR_IN_IRAM is not enabled, flag updated");
1333 intr_alloc_flags &= ~ESP_INTR_FLAG_IRAM;
1334 }
1335 #endif
1336
1337 if(p_uart_obj[uart_num] == NULL) {
1338 p_uart_obj[uart_num] = (uart_obj_t*) heap_caps_calloc(1, sizeof(uart_obj_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
1339 if(p_uart_obj[uart_num] == NULL) {
1340 ESP_LOGE(UART_TAG, "UART driver malloc error");
1341 return ESP_FAIL;
1342 }
1343 p_uart_obj[uart_num]->uart_num = uart_num;
1344 p_uart_obj[uart_num]->uart_mode = UART_MODE_UART;
1345 p_uart_obj[uart_num]->coll_det_flg = false;
1346 p_uart_obj[uart_num]->rx_always_timeout_flg = false;
1347 p_uart_obj[uart_num]->tx_fifo_sem = xSemaphoreCreateBinary();
1348 xSemaphoreGive(p_uart_obj[uart_num]->tx_fifo_sem);
1349 p_uart_obj[uart_num]->tx_done_sem = xSemaphoreCreateBinary();
1350 p_uart_obj[uart_num]->tx_brk_sem = xSemaphoreCreateBinary();
1351 p_uart_obj[uart_num]->tx_mux = xSemaphoreCreateMutex();
1352 p_uart_obj[uart_num]->rx_mux = xSemaphoreCreateMutex();
1353 p_uart_obj[uart_num]->queue_size = queue_size;
1354 p_uart_obj[uart_num]->tx_ptr = NULL;
1355 p_uart_obj[uart_num]->tx_head = NULL;
1356 p_uart_obj[uart_num]->tx_len_tot = 0;
1357 p_uart_obj[uart_num]->tx_brk_flg = 0;
1358 p_uart_obj[uart_num]->tx_brk_len = 0;
1359 p_uart_obj[uart_num]->tx_waiting_brk = 0;
1360 p_uart_obj[uart_num]->rx_buffered_len = 0;
1361 uart_pattern_queue_reset(uart_num, UART_PATTERN_DET_QLEN_DEFAULT);
1362
1363 if(uart_queue) {
1364 p_uart_obj[uart_num]->xQueueUart = xQueueCreate(queue_size, sizeof(uart_event_t));
1365 *uart_queue = p_uart_obj[uart_num]->xQueueUart;
1366 ESP_LOGI(UART_TAG, "queue free spaces: %d", uxQueueSpacesAvailable(p_uart_obj[uart_num]->xQueueUart));
1367 } else {
1368 p_uart_obj[uart_num]->xQueueUart = NULL;
1369 }
1370 p_uart_obj[uart_num]->rx_buffer_full_flg = false;
1371 p_uart_obj[uart_num]->tx_waiting_fifo = false;
1372 p_uart_obj[uart_num]->rx_ptr = NULL;
1373 p_uart_obj[uart_num]->rx_cur_remain = 0;
1374 p_uart_obj[uart_num]->rx_head_ptr = NULL;
1375 p_uart_obj[uart_num]->rx_ring_buf = xRingbufferCreate(rx_buffer_size, RINGBUF_TYPE_BYTEBUF);
1376 if(tx_buffer_size > 0) {
1377 p_uart_obj[uart_num]->tx_ring_buf = xRingbufferCreate(tx_buffer_size, RINGBUF_TYPE_NOSPLIT);
1378 p_uart_obj[uart_num]->tx_buf_size = tx_buffer_size;
1379 } else {
1380 p_uart_obj[uart_num]->tx_ring_buf = NULL;
1381 p_uart_obj[uart_num]->tx_buf_size = 0;
1382 }
1383 p_uart_obj[uart_num]->uart_select_notif_callback = NULL;
1384 } else {
1385 ESP_LOGE(UART_TAG, "UART driver already installed");
1386 return ESP_FAIL;
1387 }
1388
1389 uart_intr_config_t uart_intr = {
1390 .intr_enable_mask = UART_INTR_CONFIG_FLAG,
1391 .rxfifo_full_thresh = UART_FULL_THRESH_DEFAULT,
1392 .rx_timeout_thresh = UART_TOUT_THRESH_DEFAULT,
1393 .txfifo_empty_intr_thresh = UART_EMPTY_THRESH_DEFAULT,
1394 };
1395 uart_module_enable(uart_num);
1396 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
1397 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
1398 r=uart_isr_register(uart_num, uart_rx_intr_handler_default, p_uart_obj[uart_num], intr_alloc_flags, &p_uart_obj[uart_num]->intr_handle);
1399 if (r!=ESP_OK) goto err;
1400 r=uart_intr_config(uart_num, &uart_intr);
1401 if (r!=ESP_OK) goto err;
1402 return r;
1403
1404 err:
1405 uart_driver_delete(uart_num);
1406 return r;
1407 }
1408
1409 //Make sure no other tasks are still using UART before you call this function
uart_driver_delete(uart_port_t uart_num)1410 esp_err_t uart_driver_delete(uart_port_t uart_num)
1411 {
1412 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);
1413 if(p_uart_obj[uart_num] == NULL) {
1414 ESP_LOGI(UART_TAG, "ALREADY NULL");
1415 return ESP_OK;
1416 }
1417 esp_intr_free(p_uart_obj[uart_num]->intr_handle);
1418 uart_disable_rx_intr(uart_num);
1419 uart_disable_tx_intr(uart_num);
1420 uart_pattern_link_free(uart_num);
1421
1422 if(p_uart_obj[uart_num]->tx_fifo_sem) {
1423 vSemaphoreDelete(p_uart_obj[uart_num]->tx_fifo_sem);
1424 p_uart_obj[uart_num]->tx_fifo_sem = NULL;
1425 }
1426 if(p_uart_obj[uart_num]->tx_done_sem) {
1427 vSemaphoreDelete(p_uart_obj[uart_num]->tx_done_sem);
1428 p_uart_obj[uart_num]->tx_done_sem = NULL;
1429 }
1430 if(p_uart_obj[uart_num]->tx_brk_sem) {
1431 vSemaphoreDelete(p_uart_obj[uart_num]->tx_brk_sem);
1432 p_uart_obj[uart_num]->tx_brk_sem = NULL;
1433 }
1434 if(p_uart_obj[uart_num]->tx_mux) {
1435 vSemaphoreDelete(p_uart_obj[uart_num]->tx_mux);
1436 p_uart_obj[uart_num]->tx_mux = NULL;
1437 }
1438 if(p_uart_obj[uart_num]->rx_mux) {
1439 vSemaphoreDelete(p_uart_obj[uart_num]->rx_mux);
1440 p_uart_obj[uart_num]->rx_mux = NULL;
1441 }
1442 if(p_uart_obj[uart_num]->xQueueUart) {
1443 vQueueDelete(p_uart_obj[uart_num]->xQueueUart);
1444 p_uart_obj[uart_num]->xQueueUart = NULL;
1445 }
1446 if(p_uart_obj[uart_num]->rx_ring_buf) {
1447 vRingbufferDelete(p_uart_obj[uart_num]->rx_ring_buf);
1448 p_uart_obj[uart_num]->rx_ring_buf = NULL;
1449 }
1450 if(p_uart_obj[uart_num]->tx_ring_buf) {
1451 vRingbufferDelete(p_uart_obj[uart_num]->tx_ring_buf);
1452 p_uart_obj[uart_num]->tx_ring_buf = NULL;
1453 }
1454
1455 heap_caps_free(p_uart_obj[uart_num]);
1456 p_uart_obj[uart_num] = NULL;
1457
1458 #if SOC_UART_SUPPORT_RTC_CLK
1459
1460 uart_sclk_t sclk = 0;
1461 uart_hal_get_sclk(&(uart_context[uart_num].hal), &sclk);
1462 if (sclk == UART_SCLK_RTC) {
1463 rtc_clk_disable(uart_num);
1464 }
1465 #endif
1466 uart_module_disable(uart_num);
1467 return ESP_OK;
1468 }
1469
uart_is_driver_installed(uart_port_t uart_num)1470 bool uart_is_driver_installed(uart_port_t uart_num)
1471 {
1472 return uart_num < UART_NUM_MAX && (p_uart_obj[uart_num] != NULL);
1473 }
1474
uart_set_select_notif_callback(uart_port_t uart_num,uart_select_notif_callback_t uart_select_notif_callback)1475 void uart_set_select_notif_callback(uart_port_t uart_num, uart_select_notif_callback_t uart_select_notif_callback)
1476 {
1477 if (uart_num < UART_NUM_MAX && p_uart_obj[uart_num]) {
1478 p_uart_obj[uart_num]->uart_select_notif_callback = (uart_select_notif_callback_t) uart_select_notif_callback;
1479 }
1480 }
1481
uart_get_selectlock(void)1482 portMUX_TYPE *uart_get_selectlock(void)
1483 {
1484 return &uart_selectlock;
1485 }
1486
1487 // Set UART mode
uart_set_mode(uart_port_t uart_num,uart_mode_t mode)1488 esp_err_t uart_set_mode(uart_port_t uart_num, uart_mode_t mode)
1489 {
1490 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
1491 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_ERR_INVALID_STATE);
1492 if ((mode == UART_MODE_RS485_COLLISION_DETECT) || (mode == UART_MODE_RS485_APP_CTRL)
1493 || (mode == UART_MODE_RS485_HALF_DUPLEX)) {
1494 UART_CHECK((!uart_hal_is_hw_rts_en(&(uart_context[uart_num].hal))),
1495 "disable hw flowctrl before using RS485 mode", ESP_ERR_INVALID_ARG);
1496 }
1497 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1498 uart_hal_set_mode(&(uart_context[uart_num].hal), mode);
1499 if(mode == UART_MODE_RS485_COLLISION_DETECT) {
1500 // This mode allows read while transmitting that allows collision detection
1501 p_uart_obj[uart_num]->coll_det_flg = false;
1502 // Enable collision detection interrupts
1503 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_TOUT
1504 | UART_INTR_RXFIFO_FULL
1505 | UART_INTR_RS485_CLASH
1506 | UART_INTR_RS485_FRM_ERR
1507 | UART_INTR_RS485_PARITY_ERR);
1508 }
1509 p_uart_obj[uart_num]->uart_mode = mode;
1510 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1511 return ESP_OK;
1512 }
1513
uart_set_rx_full_threshold(uart_port_t uart_num,int threshold)1514 esp_err_t uart_set_rx_full_threshold(uart_port_t uart_num, int threshold)
1515 {
1516 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
1517 UART_CHECK((threshold < UART_RXFIFO_FULL_THRHD_V) && (threshold > 0),
1518 "rx fifo full threshold value error", ESP_ERR_INVALID_ARG);
1519 if (p_uart_obj[uart_num] == NULL) {
1520 ESP_LOGE(UART_TAG, "call uart_driver_install API first");
1521 return ESP_ERR_INVALID_STATE;
1522 }
1523 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1524 if (uart_hal_get_intr_ena_status(&(uart_context[uart_num].hal)) & UART_INTR_RXFIFO_FULL) {
1525 uart_hal_set_rxfifo_full_thr(&(uart_context[uart_num].hal), threshold);
1526 }
1527 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1528 return ESP_OK;
1529 }
1530
uart_set_tx_empty_threshold(uart_port_t uart_num,int threshold)1531 esp_err_t uart_set_tx_empty_threshold(uart_port_t uart_num, int threshold)
1532 {
1533 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
1534 UART_CHECK((threshold < UART_TXFIFO_EMPTY_THRHD_V) && (threshold > 0),
1535 "tx fifo empty threshold value error", ESP_ERR_INVALID_ARG);
1536 if (p_uart_obj[uart_num] == NULL) {
1537 ESP_LOGE(UART_TAG, "call uart_driver_install API first");
1538 return ESP_ERR_INVALID_STATE;
1539 }
1540 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1541 if (uart_hal_get_intr_ena_status(&(uart_context[uart_num].hal)) & UART_INTR_TXFIFO_EMPTY) {
1542 uart_hal_set_txfifo_empty_thr(&(uart_context[uart_num].hal), threshold);
1543 }
1544 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1545 return ESP_OK;
1546 }
1547
uart_set_rx_timeout(uart_port_t uart_num,const uint8_t tout_thresh)1548 esp_err_t uart_set_rx_timeout(uart_port_t uart_num, const uint8_t tout_thresh)
1549 {
1550 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
1551 // get maximum timeout threshold
1552 uint16_t tout_max_thresh = uart_hal_get_max_rx_timeout_thrd(&(uart_context[uart_num].hal));
1553 if (tout_thresh > tout_max_thresh) {
1554 ESP_LOGE(UART_TAG, "tout_thresh = %d > maximum value = %d", tout_thresh, tout_max_thresh);
1555 return ESP_ERR_INVALID_ARG;
1556 }
1557 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1558 uart_hal_set_rx_timeout(&(uart_context[uart_num].hal), tout_thresh);
1559 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1560 return ESP_OK;
1561 }
1562
uart_get_collision_flag(uart_port_t uart_num,bool * collision_flag)1563 esp_err_t uart_get_collision_flag(uart_port_t uart_num, bool* collision_flag)
1564 {
1565 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
1566 UART_CHECK((p_uart_obj[uart_num]), "uart driver error", ESP_FAIL);
1567 UART_CHECK((collision_flag != NULL), "wrong parameter pointer", ESP_ERR_INVALID_ARG);
1568 UART_CHECK((UART_IS_MODE_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX)
1569 || UART_IS_MODE_SET(uart_num, UART_MODE_RS485_COLLISION_DETECT)),
1570 "wrong mode", ESP_ERR_INVALID_ARG);
1571 *collision_flag = p_uart_obj[uart_num]->coll_det_flg;
1572 return ESP_OK;
1573 }
1574
uart_set_wakeup_threshold(uart_port_t uart_num,int wakeup_threshold)1575 esp_err_t uart_set_wakeup_threshold(uart_port_t uart_num, int wakeup_threshold)
1576 {
1577 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
1578 UART_CHECK((wakeup_threshold <= UART_ACTIVE_THRESHOLD_V &&
1579 wakeup_threshold > UART_MIN_WAKEUP_THRESH),
1580 "wakeup_threshold out of bounds", ESP_ERR_INVALID_ARG);
1581 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
1582 uart_hal_set_wakeup_thrd(&(uart_context[uart_num].hal), wakeup_threshold);
1583 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
1584 return ESP_OK;
1585 }
1586
uart_get_wakeup_threshold(uart_port_t uart_num,int * out_wakeup_threshold)1587 esp_err_t uart_get_wakeup_threshold(uart_port_t uart_num, int* out_wakeup_threshold)
1588 {
1589 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
1590 UART_CHECK((out_wakeup_threshold != NULL), "argument is NULL", ESP_ERR_INVALID_ARG);
1591 uart_hal_get_wakeup_thrd(&(uart_context[uart_num].hal), (uint32_t *)out_wakeup_threshold);
1592 return ESP_OK;
1593 }
1594
uart_wait_tx_idle_polling(uart_port_t uart_num)1595 esp_err_t uart_wait_tx_idle_polling(uart_port_t uart_num)
1596 {
1597 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
1598 while(!uart_hal_is_tx_idle(&(uart_context[uart_num].hal)));
1599 return ESP_OK;
1600 }
1601
uart_set_loop_back(uart_port_t uart_num,bool loop_back_en)1602 esp_err_t uart_set_loop_back(uart_port_t uart_num, bool loop_back_en)
1603 {
1604 UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_ERR_INVALID_ARG);
1605 uart_hal_set_loop_back(&(uart_context[uart_num].hal), loop_back_en);
1606 return ESP_OK;
1607 }
1608
uart_set_always_rx_timeout(uart_port_t uart_num,bool always_rx_timeout)1609 void uart_set_always_rx_timeout(uart_port_t uart_num, bool always_rx_timeout)
1610 {
1611 uint16_t rx_tout = uart_hal_get_rx_tout_thr(&(uart_context[uart_num].hal));
1612 if (rx_tout) {
1613 p_uart_obj[uart_num]->rx_always_timeout_flg = always_rx_timeout;
1614 } else {
1615 p_uart_obj[uart_num]->rx_always_timeout_flg = false;
1616 }
1617 }
1618
