1 /** Copyright 2021 Espressif Systems (Shanghai) PTE LTD 2 * 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #pragma once 16 17 #include <stdint.h> 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 /** SYSTEM TIMER REGISTER */ 23 /** Type of conf register 24 * Configure system timer clock 25 */ 26 typedef union { 27 struct { 28 /** clk_fo : R/W; bitpos: [0]; default: 0; 29 * system timer force clock enable 30 */ 31 uint32_t clk_fo: 1; 32 uint32_t reserved_1: 30; 33 /** clk_en : R/W; bitpos: [31]; default: 0; 34 * register clock enable 35 */ 36 uint32_t clk_en: 1; 37 }; 38 uint32_t val; 39 } systimer_conf_reg_t; 40 41 /** Type of load register 42 * load value to system timer 43 */ 44 typedef union { 45 struct { 46 uint32_t reserved_0: 31; 47 /** timer_load : WO; bitpos: [31]; default: 0; 48 * load value to system timer 49 */ 50 uint32_t timer_load: 1; 51 }; 52 uint32_t val; 53 } systimer_load_reg_t; 54 55 /** Type of load_hi register 56 * High 32-bit load to system timer 57 */ 58 typedef union { 59 struct { 60 /** timer_load_hi : R/W; bitpos: [31:0]; default: 0; 61 * High 32-bit load to system timer 62 */ 63 uint32_t timer_load_hi: 32; 64 }; 65 uint32_t val; 66 } systimer_load_hi_reg_t; 67 68 /** Type of load_lo register 69 * Low 32-bit load to system timer 70 */ 71 typedef union { 72 struct { 73 /** timer_load_lo : R/W; bitpos: [31:0]; default: 0; 74 * Low 32-bit load to system timer 75 */ 76 uint32_t timer_load_lo: 32; 77 }; 78 uint32_t val; 79 } systimer_load_lo_reg_t; 80 81 /** Type of step register 82 * system timer accumulation step 83 */ 84 typedef union { 85 struct { 86 /** timer_xtal_step : R/W; bitpos: [9:0]; default: 80; 87 * system timer accumulation step when using XTAL 88 */ 89 uint32_t timer_xtal_step: 10; 90 /** timer_pll_step : R/W; bitpos: [19:10]; default: 1; 91 * system timer accumulation step when using PLL 92 */ 93 uint32_t timer_pll_step: 10; 94 uint32_t reserved20: 12; 95 }; 96 uint32_t val; 97 } systimer_step_reg_t; 98 99 /** Type of target_val register 100 * System timer target value 101 */ 102 typedef struct { 103 union { 104 struct { 105 /** timer_target_hi : R/W; bitpos: [31:0]; default: 0; 106 * System timer target0 high 32-bit 107 */ 108 uint32_t timer_target_hi: 32; 109 }; 110 uint32_t val; 111 } hi; 112 union { 113 struct { 114 /** timer_target_lo : R/W; bitpos: [31:0]; default: 0; 115 * System timer target0 low 32-bit 116 */ 117 uint32_t timer_target_lo: 32; 118 }; 119 uint32_t val; 120 } lo; 121 } systimer_target_val_reg_t; 122 123 /** Type of target_conf register 124 * Configure system timer target work mode 125 */ 126 typedef union { 127 struct { 128 /** target_period : R/W; bitpos: [29:0]; default: 0; 129 * System timer target alarm period 130 */ 131 uint32_t target_period: 30; 132 /** target_period_mode : R/W; bitpos: [30]; default: 0; 133 * Whether system timer target work in period mode 134 */ 135 uint32_t target_period_mode: 1; 136 /** target_work_en : R/W; bitpos: [31]; default: 0; 137 * system timer target work enable 138 */ 139 uint32_t target_work_en: 1; 140 }; 141 uint32_t val; 142 } systimer_target_conf_reg_t; 143 144 /** Type of update register 145 * Read out system timer value 146 */ 147 typedef union { 148 struct { 149 uint32_t reserved_0: 30; 150 /** timer_value_valid : RO; bitpos: [30]; default: 0; 151 * If it is valid to read out timer value from register 152 */ 153 uint32_t timer_value_valid: 1; 154 /** timer_update : WO; bitpos: [31]; default: 0; 155 * Update system timer value to register 156 */ 157 uint32_t timer_update: 1; 158 }; 159 uint32_t val; 160 } systimer_update_reg_t; 161 162 /** Type of value_hi register 163 * system timer high 32-bit 164 */ 165 typedef union { 166 struct { 167 /** timer_value_hi : RO; bitpos: [31:0]; default: 0; 168 * system timer high 32-bit 169 */ 170 uint32_t timer_value_hi: 32; 171 }; 172 uint32_t val; 173 } systimer_value_hi_reg_t; 174 175 /** Type of value_lo register 176 * system timer low 32-bit 177 */ 178 typedef union { 179 struct { 180 /** timer_value_lo : RO; bitpos: [31:0]; default: 0; 181 * system timer low 32-bit 182 */ 183 uint32_t timer_value_lo: 32; 184 }; 185 uint32_t val; 186 } systimer_value_lo_reg_t; 187 188 /** Type of int_ena register 189 * system timer interrupt enable 190 */ 191 typedef union { 192 struct { 193 /** systimer_int0_ena : R/W; bitpos: [0]; default: 0; 194 * system timer target0 interrupt enable 195 */ 196 uint32_t systimer_int0_ena: 1; 197 /** systimer_int1_ena : R/W; bitpos: [1]; default: 0; 198 * system timer target1 interrupt enable 199 */ 200 uint32_t systimer_int1_ena: 1; 201 /** systimer_int2_ena : R/W; bitpos: [2]; default: 0; 202 * system timer target2 interrupt enable 203 */ 204 uint32_t systimer_int2_ena: 1; 205 uint32_t reserved3: 29; 206 }; 207 uint32_t val; 208 } systimer_int_ena_reg_t; 209 210 /** Type of int_raw register 211 * system timer interrupt raw 212 */ 213 typedef union { 214 struct { 215 /** systimer_int0_raw : RO; bitpos: [0]; default: 0; 216 * system timer target0 interrupt raw 217 */ 218 uint32_t systimer_int0_raw: 1; 219 /** systimer_int1_raw : RO; bitpos: [1]; default: 0; 220 * system timer target1 interrupt raw 221 */ 222 uint32_t systimer_int1_raw: 1; 223 /** systimer_int2_raw : RO; bitpos: [2]; default: 0; 224 * system timer target2 interrupt raw 225 */ 226 uint32_t systimer_int2_raw: 1; 227 uint32_t reserved3: 29; 228 }; 229 uint32_t val; 230 } systimer_int_raw_reg_t; 231 232 /** Type of int_clr register 233 * system timer interrupt clear 234 */ 235 typedef union { 236 struct { 237 /** systimer_int0_clr : WO; bitpos: [0]; default: 0; 238 * system timer target0 interrupt clear 239 */ 240 uint32_t systimer_int0_clr: 1; 241 /** systimer_int1_clr : WO; bitpos: [1]; default: 0; 242 * system timer target1 interrupt clear 243 */ 244 uint32_t systimer_int1_clr: 1; 245 /** systimer_int2_clr : WO; bitpos: [2]; default: 0; 246 * system timer target2 interrupt clear 247 */ 248 uint32_t systimer_int2_clr: 1; 249 uint32_t reserved3: 29; 250 }; 251 uint32_t val; 252 } systimer_int_clr_reg_t; 253 254 255 /** DATE */ 256 /** Type of date register 257 * system timer register version 258 */ 259 typedef union { 260 struct { 261 /** date : R/W; bitpos: [31:0]; default: 25194848; 262 * system timer register version 263 */ 264 uint32_t date: 32; 265 }; 266 uint32_t val; 267 } systimer_date_reg_t; 268 269 270 typedef struct { 271 volatile systimer_conf_reg_t conf; 272 volatile systimer_load_reg_t load; 273 volatile systimer_load_hi_reg_t load_hi; 274 volatile systimer_load_lo_reg_t load_lo; 275 volatile systimer_step_reg_t step; 276 volatile systimer_target_val_reg_t target_val[3]; 277 volatile systimer_target_conf_reg_t target_conf[3]; 278 volatile systimer_update_reg_t update; 279 volatile systimer_value_hi_reg_t value_hi; 280 volatile systimer_value_lo_reg_t value_lo; 281 volatile systimer_int_ena_reg_t int_ena; 282 volatile systimer_int_raw_reg_t int_raw; 283 volatile systimer_int_clr_reg_t int_clr; 284 uint32_t reserved_050; 285 uint32_t reserved_054; 286 uint32_t reserved_058; 287 uint32_t reserved_05c; 288 uint32_t reserved_060; 289 uint32_t reserved_064; 290 uint32_t reserved_068; 291 uint32_t reserved_06c; 292 uint32_t reserved_070; 293 uint32_t reserved_074; 294 uint32_t reserved_078; 295 uint32_t reserved_07c; 296 uint32_t reserved_080; 297 uint32_t reserved_084; 298 uint32_t reserved_088; 299 uint32_t reserved_08c; 300 uint32_t reserved_090; 301 uint32_t reserved_094; 302 uint32_t reserved_098; 303 uint32_t reserved_09c; 304 uint32_t reserved_0a0; 305 uint32_t reserved_0a4; 306 uint32_t reserved_0a8; 307 uint32_t reserved_0ac; 308 uint32_t reserved_0b0; 309 uint32_t reserved_0b4; 310 uint32_t reserved_0b8; 311 uint32_t reserved_0bc; 312 uint32_t reserved_0c0; 313 uint32_t reserved_0c4; 314 uint32_t reserved_0c8; 315 uint32_t reserved_0cc; 316 uint32_t reserved_0d0; 317 uint32_t reserved_0d4; 318 uint32_t reserved_0d8; 319 uint32_t reserved_0dc; 320 uint32_t reserved_0e0; 321 uint32_t reserved_0e4; 322 uint32_t reserved_0e8; 323 uint32_t reserved_0ec; 324 uint32_t reserved_0f0; 325 uint32_t reserved_0f4; 326 uint32_t reserved_0f8; 327 volatile systimer_date_reg_t date; 328 } systimer_dev_t; 329 330 extern systimer_dev_t SYSTIMER; 331 332 #ifdef __cplusplus 333 } 334 #endif 335