1 // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 
7 //     http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 
15 #include <string.h>
16 #include "esp_log.h"
17 #include "esp_err.h"
18 #include "esp_intr_alloc.h"
19 #include "freertos/FreeRTOS.h"
20 #include "driver/timer.h"
21 #include "driver/periph_ctrl.h"
22 #include "hal/timer_hal.h"
23 #include "soc/timer_periph.h"
24 #include "soc/rtc.h"
25 
26 static const char *TIMER_TAG = "timer_group";
27 
28 #define TIMER_CHECK(a, str, ret_val) \
29     if (!(a)) { \
30         ESP_LOGE(TIMER_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
31         return (ret_val); \
32     }
33 
34 #define TIMER_GROUP_NUM_ERROR   "TIMER GROUP NUM ERROR"
35 #define TIMER_NUM_ERROR         "HW TIMER NUM ERROR"
36 #define TIMER_PARAM_ADDR_ERROR  "HW TIMER PARAM ADDR ERROR"
37 #define TIMER_NEVER_INIT_ERROR  "HW TIMER NEVER INIT ERROR"
38 #define TIMER_COUNT_DIR_ERROR   "HW TIMER COUNTER DIR ERROR"
39 #define TIMER_AUTORELOAD_ERROR  "HW TIMER AUTORELOAD ERROR"
40 #define TIMER_SCALE_ERROR       "HW TIMER SCALE ERROR"
41 #define TIMER_ALARM_ERROR       "HW TIMER ALARM ERROR"
42 #define DIVIDER_RANGE_ERROR     "HW TIMER divider outside of [2, 65536] range error"
43 
44 #define TIMER_ENTER_CRITICAL(mux)      portENTER_CRITICAL_SAFE(mux);
45 #define TIMER_EXIT_CRITICAL(mux)       portEXIT_CRITICAL_SAFE(mux);
46 
47 typedef struct {
48     timer_isr_t fn;  /*!< isr function */
49     void *args;      /*!< isr function args */
50     timer_isr_handle_t timer_isr_handle;  /*!< interrupt handle */
51     timer_group_t isr_timer_group;        /*!< timer group of interrupt triggered */
52 } timer_isr_func_t;
53 
54 typedef struct {
55     timer_hal_context_t hal;
56     timer_isr_func_t timer_isr_fun;
57 } timer_obj_t;
58 
59 static timer_obj_t *p_timer_obj[TIMER_GROUP_MAX][TIMER_MAX] = {0};
60 static portMUX_TYPE timer_spinlock[TIMER_GROUP_MAX] = {portMUX_INITIALIZER_UNLOCKED, portMUX_INITIALIZER_UNLOCKED};
61 
timer_get_counter_value(timer_group_t group_num,timer_idx_t timer_num,uint64_t * timer_val)62 esp_err_t timer_get_counter_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t *timer_val)
63 {
64     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
65     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
66     TIMER_CHECK(timer_val != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
67     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
68     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
69     timer_hal_get_counter_value(&(p_timer_obj[group_num][timer_num]->hal), timer_val);
70     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
71     return ESP_OK;
72 }
73 
timer_get_counter_time_sec(timer_group_t group_num,timer_idx_t timer_num,double * time)74 esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_num, double *time)
75 {
76     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
77     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
78     TIMER_CHECK(time != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
79     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
80     uint64_t timer_val;
81     esp_err_t err = timer_get_counter_value(group_num, timer_num, &timer_val);
82     if (err == ESP_OK) {
83         uint32_t div;
84         timer_hal_get_divider(&(p_timer_obj[group_num][timer_num]->hal), &div);
85         *time = (double)timer_val * div / rtc_clk_apb_freq_get();
86 #if SOC_TIMER_GROUP_SUPPORT_XTAL
87         if (timer_hal_get_use_xtal(&(p_timer_obj[group_num][timer_num]->hal))) {
88             *time = (double)timer_val * div / ((int)rtc_clk_xtal_freq_get() * 1000000);
89         }
90 #endif
91     }
92     return err;
93 }
94 
timer_set_counter_value(timer_group_t group_num,timer_idx_t timer_num,uint64_t load_val)95 esp_err_t timer_set_counter_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t load_val)
96 {
97     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
98     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
99     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
100     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
101     timer_hal_set_counter_value(&(p_timer_obj[group_num][timer_num]->hal), load_val);
102     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
103     return ESP_OK;
104 }
105 
timer_start(timer_group_t group_num,timer_idx_t timer_num)106 esp_err_t timer_start(timer_group_t group_num, timer_idx_t timer_num)
107 {
108     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
109     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
110     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
111     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
112     timer_hal_set_counter_enable(&(p_timer_obj[group_num][timer_num]->hal), TIMER_START);
113     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
114     return ESP_OK;
115 }
116 
timer_pause(timer_group_t group_num,timer_idx_t timer_num)117 esp_err_t timer_pause(timer_group_t group_num, timer_idx_t timer_num)
118 {
119     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
120     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
121     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
122     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
123     timer_hal_set_counter_enable(&(p_timer_obj[group_num][timer_num]->hal), TIMER_PAUSE);
124     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
125     return ESP_OK;
126 }
127 
timer_set_counter_mode(timer_group_t group_num,timer_idx_t timer_num,timer_count_dir_t counter_dir)128 esp_err_t timer_set_counter_mode(timer_group_t group_num, timer_idx_t timer_num, timer_count_dir_t counter_dir)
129 {
130     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
131     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
132     TIMER_CHECK(counter_dir < TIMER_COUNT_MAX, TIMER_COUNT_DIR_ERROR, ESP_ERR_INVALID_ARG);
133     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
134     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
135     timer_hal_set_counter_increase(&(p_timer_obj[group_num][timer_num]->hal), counter_dir);
136     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
137     return ESP_OK;
138 }
139 
timer_set_auto_reload(timer_group_t group_num,timer_idx_t timer_num,timer_autoreload_t reload)140 esp_err_t timer_set_auto_reload(timer_group_t group_num, timer_idx_t timer_num, timer_autoreload_t reload)
141 {
142     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
143     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
144     TIMER_CHECK(reload < TIMER_AUTORELOAD_MAX, TIMER_AUTORELOAD_ERROR, ESP_ERR_INVALID_ARG);
145     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
146     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
147     timer_hal_set_auto_reload(&(p_timer_obj[group_num][timer_num]->hal), reload);
148     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
149     return ESP_OK;
150 }
151 
timer_set_divider(timer_group_t group_num,timer_idx_t timer_num,uint32_t divider)152 esp_err_t timer_set_divider(timer_group_t group_num, timer_idx_t timer_num, uint32_t divider)
153 {
154     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
155     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
156     TIMER_CHECK(divider > 1 && divider < 65537, DIVIDER_RANGE_ERROR, ESP_ERR_INVALID_ARG);
157     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
158     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
159     timer_hal_set_divider(&(p_timer_obj[group_num][timer_num]->hal), (uint16_t) divider);
160     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
161     return ESP_OK;
162 }
163 
timer_set_alarm_value(timer_group_t group_num,timer_idx_t timer_num,uint64_t alarm_value)164 esp_err_t timer_set_alarm_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t alarm_value)
165 {
166     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
167     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
168     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
169     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
170     timer_hal_set_alarm_value(&(p_timer_obj[group_num][timer_num]->hal), alarm_value);
171     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
172     return ESP_OK;
173 }
174 
timer_get_alarm_value(timer_group_t group_num,timer_idx_t timer_num,uint64_t * alarm_value)175 esp_err_t timer_get_alarm_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t *alarm_value)
176 {
177     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
178     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
179     TIMER_CHECK(alarm_value != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
180     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
181     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
182     timer_hal_get_alarm_value(&(p_timer_obj[group_num][timer_num]->hal), alarm_value);
183     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
184     return ESP_OK;
185 }
186 
timer_set_alarm(timer_group_t group_num,timer_idx_t timer_num,timer_alarm_t alarm_en)187 esp_err_t timer_set_alarm(timer_group_t group_num, timer_idx_t timer_num, timer_alarm_t alarm_en)
188 {
189     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
190     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
191     TIMER_CHECK(alarm_en < TIMER_ALARM_MAX, TIMER_ALARM_ERROR, ESP_ERR_INVALID_ARG);
192     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
193     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
194     timer_hal_set_alarm_enable(&(p_timer_obj[group_num][timer_num]->hal), alarm_en);
195     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
196     return ESP_OK;
197 }
198 
timer_isr_default(void * arg)199 static void IRAM_ATTR timer_isr_default(void *arg)
200 {
201     bool is_awoken = false;
202 
203     timer_obj_t *timer_obj = (timer_obj_t *)arg;
204     if (timer_obj == NULL) {
205         return;
206     }
207     if (timer_obj->timer_isr_fun.fn == NULL) {
208         return;
209     }
210 
211     TIMER_ENTER_CRITICAL(&timer_spinlock[timer_obj->timer_isr_fun.isr_timer_group]);
212     {
213         uint32_t intr_status = 0;
214         timer_hal_get_intr_status(&(timer_obj->hal), &intr_status);
215         if (intr_status & BIT(timer_obj->hal.idx)) {
216             is_awoken = timer_obj->timer_isr_fun.fn(timer_obj->timer_isr_fun.args);
217             //Clear intrrupt status
218             timer_hal_clear_intr_status(&(timer_obj->hal));
219             //After the alarm has been triggered, we need enable it again, so it is triggered the next time.
220             timer_hal_set_alarm_enable(&(timer_obj->hal), TIMER_ALARM_EN);
221         }
222     }
223     TIMER_EXIT_CRITICAL(&timer_spinlock[timer_obj->timer_isr_fun.isr_timer_group]);
224 
225     if (is_awoken) {
226         portYIELD_FROM_ISR();
227     }
228 }
229 
timer_isr_callback_add(timer_group_t group_num,timer_idx_t timer_num,timer_isr_t isr_handler,void * args,int intr_alloc_flags)230 esp_err_t timer_isr_callback_add(timer_group_t group_num, timer_idx_t timer_num, timer_isr_t isr_handler, void *args, int intr_alloc_flags)
231 {
232     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
233     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
234     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
235 
236     timer_disable_intr(group_num, timer_num);
237     p_timer_obj[group_num][timer_num]->timer_isr_fun.fn = isr_handler;
238     p_timer_obj[group_num][timer_num]->timer_isr_fun.args = args;
239     p_timer_obj[group_num][timer_num]->timer_isr_fun.isr_timer_group = group_num;
240     timer_isr_register(group_num, timer_num, timer_isr_default, (void *)p_timer_obj[group_num][timer_num],
241                        intr_alloc_flags, &(p_timer_obj[group_num][timer_num]->timer_isr_fun.timer_isr_handle));
242     timer_enable_intr(group_num, timer_num);
243 
244     return ESP_OK;
245 }
246 
timer_isr_callback_remove(timer_group_t group_num,timer_idx_t timer_num)247 esp_err_t timer_isr_callback_remove(timer_group_t group_num, timer_idx_t timer_num)
248 {
249     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
250     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
251     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
252 
253     timer_disable_intr(group_num, timer_num);
254     p_timer_obj[group_num][timer_num]->timer_isr_fun.fn = NULL;
255     p_timer_obj[group_num][timer_num]->timer_isr_fun.args = NULL;
256     esp_intr_free(p_timer_obj[group_num][timer_num]->timer_isr_fun.timer_isr_handle);
257 
258     return ESP_OK;
259 }
260 
timer_isr_register(timer_group_t group_num,timer_idx_t timer_num,void (* fn)(void *),void * arg,int intr_alloc_flags,timer_isr_handle_t * handle)261 esp_err_t timer_isr_register(timer_group_t group_num, timer_idx_t timer_num,
262                              void (*fn)(void *), void *arg, int intr_alloc_flags, timer_isr_handle_t *handle)
263 {
264     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
265     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
266     TIMER_CHECK(fn != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
267     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
268 
269     uint32_t status_reg = 0;
270     uint32_t mask = 0;
271     timer_hal_get_status_reg_mask_bit(&(p_timer_obj[group_num][timer_num]->hal), &status_reg, &mask);
272     return esp_intr_alloc_intrstatus(timer_group_periph_signals.groups[group_num].t0_irq_id + timer_num, intr_alloc_flags, status_reg, mask, fn, arg, handle);
273 }
274 
timer_init(timer_group_t group_num,timer_idx_t timer_num,const timer_config_t * config)275 esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer_config_t *config)
276 {
277     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
278     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
279     TIMER_CHECK(config != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
280     TIMER_CHECK(config->divider > 1 && config->divider < 65537, DIVIDER_RANGE_ERROR, ESP_ERR_INVALID_ARG);
281 
282     periph_module_enable(timer_group_periph_signals.groups[group_num].module);
283 
284     if (p_timer_obj[group_num][timer_num] == NULL) {
285         p_timer_obj[group_num][timer_num] = (timer_obj_t *) heap_caps_calloc(1, sizeof(timer_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
286         if (p_timer_obj[group_num][timer_num] == NULL) {
287             ESP_LOGE(TIMER_TAG, "TIMER driver malloc error");
288             return ESP_FAIL;
289         }
290     }
291 
292     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
293     timer_hal_init(&(p_timer_obj[group_num][timer_num]->hal), group_num, timer_num);
294     timer_hal_intr_disable(&(p_timer_obj[group_num][timer_num]->hal));
295     timer_hal_clear_intr_status(&(p_timer_obj[group_num][timer_num]->hal));
296     timer_hal_set_auto_reload(&(p_timer_obj[group_num][timer_num]->hal), config->auto_reload);
297     timer_hal_set_divider(&(p_timer_obj[group_num][timer_num]->hal), config->divider);
298     timer_hal_set_counter_increase(&(p_timer_obj[group_num][timer_num]->hal), config->counter_dir);
299     timer_hal_set_alarm_enable(&(p_timer_obj[group_num][timer_num]->hal), config->alarm_en);
300     timer_hal_set_level_int_enable(&(p_timer_obj[group_num][timer_num]->hal), true);
301     if (config->intr_type != TIMER_INTR_LEVEL) {
302         ESP_LOGW(TIMER_TAG, "only support Level Interrupt, switch to Level Interrupt instead");
303     }
304     timer_hal_set_counter_enable(&(p_timer_obj[group_num][timer_num]->hal), config->counter_en);
305 #if SOC_TIMER_GROUP_SUPPORT_XTAL
306     timer_hal_set_use_xtal(&(p_timer_obj[group_num][timer_num]->hal), config->clk_src);
307 #endif
308     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
309 
310     return ESP_OK;
311 }
312 
timer_deinit(timer_group_t group_num,timer_idx_t timer_num)313 esp_err_t timer_deinit(timer_group_t group_num, timer_idx_t timer_num)
314 {
315     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
316     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
317     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
318 
319     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
320     timer_hal_set_counter_enable(&(p_timer_obj[group_num][timer_num]->hal), TIMER_PAUSE);
321     timer_hal_intr_disable(&(p_timer_obj[group_num][timer_num]->hal));
322     timer_hal_clear_intr_status(&(p_timer_obj[group_num][timer_num]->hal));
323     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
324 
325     heap_caps_free(p_timer_obj[group_num][timer_num]);
326     p_timer_obj[group_num][timer_num] = NULL;
327 
328     return ESP_OK;
329 }
330 
timer_get_config(timer_group_t group_num,timer_idx_t timer_num,timer_config_t * config)331 esp_err_t timer_get_config(timer_group_t group_num, timer_idx_t timer_num, timer_config_t *config)
332 {
333     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
334     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
335     TIMER_CHECK(config != NULL, TIMER_PARAM_ADDR_ERROR, ESP_ERR_INVALID_ARG);
336     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
337 
338     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
339     config->alarm_en = timer_hal_get_alarm_enable(&(p_timer_obj[group_num][timer_num]->hal));
340     config->auto_reload = timer_hal_get_auto_reload(&(p_timer_obj[group_num][timer_num]->hal));
341     config->counter_dir = timer_hal_get_counter_increase(&(p_timer_obj[group_num][timer_num]->hal));
342     config->counter_en = timer_hal_get_counter_enable(&(p_timer_obj[group_num][timer_num]->hal));
343 
344     uint32_t div;
345     timer_hal_get_divider(&(p_timer_obj[group_num][timer_num]->hal), &div);
346     config->divider = div;
347 
348     if (timer_hal_get_level_int_enable(&(p_timer_obj[group_num][timer_num]->hal))) {
349         config->intr_type = TIMER_INTR_LEVEL;
350     } else {
351         config->intr_type = TIMER_INTR_MAX;
352     }
353     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
354     return ESP_OK;
355 }
356 
timer_group_intr_enable(timer_group_t group_num,timer_intr_t en_mask)357 esp_err_t timer_group_intr_enable(timer_group_t group_num, timer_intr_t en_mask)
358 {
359     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
360     TIMER_CHECK(p_timer_obj[group_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
361     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
362     for (int i = 0; i < TIMER_MAX; i++) {
363         if (en_mask & BIT(i)) {
364             timer_hal_intr_enable(&(p_timer_obj[group_num][i]->hal));
365         }
366     }
367     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
368     return ESP_OK;
369 }
370 
timer_group_intr_disable(timer_group_t group_num,timer_intr_t disable_mask)371 esp_err_t timer_group_intr_disable(timer_group_t group_num, timer_intr_t disable_mask)
372 {
373     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
374     TIMER_CHECK(p_timer_obj[group_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
375     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
376     for (int i = 0; i < TIMER_MAX; i++) {
377         if (disable_mask & BIT(i)) {
378             timer_hal_intr_disable(&(p_timer_obj[group_num][i]->hal));
379         }
380     }
381     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
382     return ESP_OK;
383 }
384 
timer_enable_intr(timer_group_t group_num,timer_idx_t timer_num)385 esp_err_t timer_enable_intr(timer_group_t group_num, timer_idx_t timer_num)
386 {
387     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
388     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
389     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
390     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
391     timer_hal_intr_enable(&(p_timer_obj[group_num][timer_num]->hal));
392     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
393     return ESP_OK;
394 }
395 
timer_disable_intr(timer_group_t group_num,timer_idx_t timer_num)396 esp_err_t timer_disable_intr(timer_group_t group_num, timer_idx_t timer_num)
397 {
398     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
399     TIMER_CHECK(timer_num < TIMER_MAX, TIMER_NUM_ERROR, ESP_ERR_INVALID_ARG);
400     TIMER_CHECK(p_timer_obj[group_num][timer_num] != NULL, TIMER_NEVER_INIT_ERROR, ESP_ERR_INVALID_ARG);
401     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
402     timer_hal_intr_disable(&(p_timer_obj[group_num][timer_num]->hal));
403     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
404     return ESP_OK;
405 }
406 
407 /* This function is deprecated */
timer_group_intr_get_in_isr(timer_group_t group_num)408 timer_intr_t IRAM_ATTR timer_group_intr_get_in_isr(timer_group_t group_num)
409 {
410     uint32_t intr_raw_status = 0;
411     timer_hal_get_intr_raw_status(group_num, &intr_raw_status);
412     return intr_raw_status;
413 }
414 
timer_group_get_intr_status_in_isr(timer_group_t group_num)415 uint32_t IRAM_ATTR timer_group_get_intr_status_in_isr(timer_group_t group_num)
416 {
417     uint32_t intr_status = 0;
418     if (p_timer_obj[group_num][TIMER_0] != NULL) {
419         timer_hal_get_intr_status(&(p_timer_obj[group_num][TIMER_0]->hal), &intr_status);
420     }
421 #if SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1
422     else if (p_timer_obj[group_num][TIMER_1] != NULL) {
423         timer_hal_get_intr_status(&(p_timer_obj[group_num][TIMER_1]->hal), &intr_status);
424     }
425 #endif
426     return intr_status;
427 }
428 
429 /* This function is deprecated */
timer_group_intr_clr_in_isr(timer_group_t group_num,timer_idx_t timer_num)430 void IRAM_ATTR timer_group_intr_clr_in_isr(timer_group_t group_num, timer_idx_t timer_num)
431 {
432     timer_group_clr_intr_status_in_isr(group_num, timer_num);
433 }
434 
timer_group_clr_intr_status_in_isr(timer_group_t group_num,timer_idx_t timer_num)435 void IRAM_ATTR timer_group_clr_intr_status_in_isr(timer_group_t group_num, timer_idx_t timer_num)
436 {
437     timer_hal_clear_intr_status(&(p_timer_obj[group_num][timer_num]->hal));
438 }
439 
timer_group_enable_alarm_in_isr(timer_group_t group_num,timer_idx_t timer_num)440 void IRAM_ATTR timer_group_enable_alarm_in_isr(timer_group_t group_num, timer_idx_t timer_num)
441 {
442     timer_hal_set_alarm_enable(&(p_timer_obj[group_num][timer_num]->hal), true);
443 }
444 
timer_group_get_counter_value_in_isr(timer_group_t group_num,timer_idx_t timer_num)445 uint64_t IRAM_ATTR timer_group_get_counter_value_in_isr(timer_group_t group_num, timer_idx_t timer_num)
446 {
447     uint64_t val;
448     timer_hal_get_counter_value(&(p_timer_obj[group_num][timer_num]->hal), &val);
449     return val;
450 }
451 
timer_group_set_alarm_value_in_isr(timer_group_t group_num,timer_idx_t timer_num,uint64_t alarm_val)452 void IRAM_ATTR timer_group_set_alarm_value_in_isr(timer_group_t group_num, timer_idx_t timer_num, uint64_t alarm_val)
453 {
454     timer_hal_set_alarm_value(&(p_timer_obj[group_num][timer_num]->hal), alarm_val);
455 }
456 
timer_group_set_counter_enable_in_isr(timer_group_t group_num,timer_idx_t timer_num,timer_start_t counter_en)457 void IRAM_ATTR timer_group_set_counter_enable_in_isr(timer_group_t group_num, timer_idx_t timer_num, timer_start_t counter_en)
458 {
459     timer_hal_set_counter_enable(&(p_timer_obj[group_num][timer_num]->hal), counter_en);
460 }
461 
462 /* This function is deprecated */
timer_group_clr_intr_sta_in_isr(timer_group_t group_num,timer_intr_t intr_mask)463 void IRAM_ATTR timer_group_clr_intr_sta_in_isr(timer_group_t group_num, timer_intr_t intr_mask)
464 {
465     for (uint32_t timer_idx = 0; timer_idx < TIMER_MAX; timer_idx++) {
466         if (intr_mask & BIT(timer_idx)) {
467             timer_group_clr_intr_status_in_isr(group_num, timer_idx);
468         }
469     }
470 }
471 
timer_group_get_auto_reload_in_isr(timer_group_t group_num,timer_idx_t timer_num)472 bool IRAM_ATTR timer_group_get_auto_reload_in_isr(timer_group_t group_num, timer_idx_t timer_num)
473 {
474     return timer_hal_get_auto_reload(&(p_timer_obj[group_num][timer_num]->hal));
475 }
476 
timer_spinlock_take(timer_group_t group_num)477 esp_err_t timer_spinlock_take(timer_group_t group_num)
478 {
479     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
480     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
481     return ESP_OK;
482 }
483 
timer_spinlock_give(timer_group_t group_num)484 esp_err_t timer_spinlock_give(timer_group_t group_num)
485 {
486     TIMER_CHECK(group_num < TIMER_GROUP_MAX, TIMER_GROUP_NUM_ERROR, ESP_ERR_INVALID_ARG);
487     TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
488     return ESP_OK;
489 }
490